Within-feature-shape (WiF) control of mega pillars for high density fan-out (HDFO) technology

IC packaging technology has evolved in a quite diverse manner over the past decade, addressing both high-end and low-end applications, resulting in approaches such as package-on-package (PoP), fan-out wafer-level package (FOWLP), 3D IC integration with through-silicon via (TSV), and 2.5D with TSV-Si interposer. FOWLP technology offers significant cost and performance advantages relative to other packaging approaches and is, therefore, receiving widespread adoption throughout the industry for applications such as smartphone/tablet application processor (AP), baseband (BB) module, field-programmable gate array (FPGA), graphics processing unit (GPU), etc. As a result, FOWLP technology is expected to ramp at a strong growth rate over the immediate future [1]. FOWLP technology comprises conventional under-bump metallization (UBM) and pillar/micro-pillar, as well as new routing/connection applications such as fine line redistribution layer (RDL) (sub 5×5 μm), integrated via-RDL structures and mega pillars (>150 μm) [2]. These new applications drive fundamental challenges in electrodeposition. For instance, the mega pillars consist of 180–220 μm (200 μm average) copper thickness while standard copper pillar applications typically vary between 20 and 40 μm (30 μm average) thickness. This large disparity in thickness can translate to approximately 6x plating times if a similar deposition rate was to be used. Furthermore, some integration requirements for mega pillars warrant extremely high within-die uniformities and flat bump shape. Attaining such high quality plating performance can greatly minimize the need for downstream grinding requirements. This paper will focus on the advancement of copper electrodeposition for mega pillars.