IEEE Journal of the Electron Devices Society最新文献_第9页

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs 使用硅 CMOS 和异质 IGZO FET 单片叠加结构的 1-Mbit 3D DRAM

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-03-01 DOI: 10.1109/JEDS.2024.3372053

Takeya Hirose;Yuki Okamoto;Yusuke Komura;Toshiki Mizuguchi;Toshihiko Saito;Minato Ito;Kiyotaka Kimura;Hiroki Inoue;Tatsuya Onuki;Yoshinori Ando;Hiromi Sawai;Tsutomu Murakawa;Hitoshi Kunitake;Hajime Kimura;Takanori Matsuzaki;Makoto Ikeda;Shunpei Yamazaki

{"title":"1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs","authors":"Takeya Hirose;Yuki Okamoto;Yusuke Komura;Toshiki Mizuguchi;Toshihiko Saito;Minato Ito;Kiyotaka Kimura;Hiroki Inoue;Tatsuya Onuki;Yoshinori Ando;Hiromi Sawai;Tsutomu Murakawa;Hitoshi Kunitake;Hajime Kimura;Takanori Matsuzaki;Makoto Ikeda;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3372053","DOIUrl":"10.1109/JEDS.2024.3372053","url":null,"abstract":"We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an \u0000<inline-formula> <tex-math>$2.2times 10^{-19}$ </tex-math></inline-formula>\u0000 A/cell at 85°C), indicating that over 99% of the data are retained in the memory array after one hour at 85°C without refresh.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10457845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140018245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancement of Selectivity for Chemical Mechanical Polishing by Ultra-High-Dose C and Si Ion Implantation 通过超高剂量 C 和硅离子注入提高化学机械抛光的选择性

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-29 DOI: 10.1109/JEDS.2024.3371455

S. Yuan;K. Omori;T. Yamaguchi;T. Ide;S. Muranaka;M. Inoue

引用次数: 0

Investigation of Noise Properties in the InP HEMT for LNAs in Qubit Amplification: Effects From Channel Indium Content 调查用于 Qubit 放大 LNA 的 InP HEMT 的噪声特性：通道铟含量的影响

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-29 DOI: 10.1109/JEDS.2024.3371905

Junjie Li;Johan Bergsten;Arsalan Pourkabirian;Jan Grahn

{"title":"Investigation of Noise Properties in the InP HEMT for LNAs in Qubit Amplification: Effects From Channel Indium Content","authors":"Junjie Li;Johan Bergsten;Arsalan Pourkabirian;Jan Grahn","doi":"10.1109/JEDS.2024.3371905","DOIUrl":"10.1109/JEDS.2024.3371905","url":null,"abstract":"The InP high-electron-mobility transistor (HEMT) is employed in cryogenic low-noise amplifiers (LNAs) for the readout of faint microwave signals in quantum computing. The performance of such LNAs is ultimately limited by the properties of the active \u0000<inline-formula> <tex-math>$mathrm {In_{x}Ga_{1-x}As}$ </tex-math></inline-formula>\u0000 channel in the InP HEMT. In this study, we have investigated the noise performance of 100-nm gate-length InP HEMTs used in cryogenic LNAs for amplification of qubits. The channel indium content in the InP HEMTs was 53, 60 and 70%. Hall measurements of the epitaxial materials and dc characterization of the InP HEMTs confirmed the superior transport properties of the channel structures. An indirect method involving an LNA and small-signal noise modeling was used for extracting the channel noise with high accuracy. Under noise-optimized bias, we observed that the 60% indium channel InP HEMT exhibited the lowest drain noise temperature. The difference in LNA noise temperature among InP HEMTs became more pronounced with decreasing drain voltage and current. An average noise temperature and average gain of 3.3 K and 21 dB, respectively, for a 4–8 GHz three-stage hybrid cryogenic LNA using 60% indium channel InP HEMTs was measured at a dc power consumption of \u0000<inline-formula> <tex-math>$108 ~mu text{W}$ </tex-math></inline-formula>\u0000. To the best of the authors’ knowledge, this is a new state-of-the-art for a C-band LNA operating below 1 mW. The higher drain noise temperature observed for 53 and 70% indium channels InP HEMTs can be attributed to a combination of thermal noise in the channel and real-space transfer of electrons from the channel to the barrier. This report gives experimental evidence of an optimum channel indium content in the InP HEMT used in LNAs for qubit amplification.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10454583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140002001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers 通过二维排列硅显示驱动器实现单片集成 CAAC-OS FET 和硅 CMOS 的 OLED 微型显示器

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-19 DOI: 10.1109/JEDS.2024.3366938

Munehiro Kozuma;Yusuke Komura;Shoki Miyata;Yuki Okamoto;Yuki Tamatsukuri;Hiroki Inoue;Toshihiko Saito;Hidetomo Kobayashi;Tatsuya Onuki;Yuichi Yanagisawa;Toshihiko Takeuchi;Yutaka Okazaki;Hitoshi Kunitake;Daiki Nakamura;Takaaki Nagata;Yasumasa Yamane;Makoto Ikeda;Shunpei Yamazaki

{"title":"OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers","authors":"Munehiro Kozuma;Yusuke Komura;Shoki Miyata;Yuki Okamoto;Yuki Tamatsukuri;Hiroki Inoue;Toshihiko Saito;Hidetomo Kobayashi;Tatsuya Onuki;Yuichi Yanagisawa;Toshihiko Takeuchi;Yutaka Okazaki;Hitoshi Kunitake;Daiki Nakamura;Takaaki Nagata;Yasumasa Yamane;Makoto Ikeda;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3366938","DOIUrl":"10.1109/JEDS.2024.3366938","url":null,"abstract":"We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS display drivers can be arranged two-dimensionally by monolithically stacking \u0000<inline-formula> <tex-math>${c}$ </tex-math></inline-formula>\u0000-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs over Si CMOS. A CAAC-OS FET exhibits a higher withstand voltage than a SiFET of the same size, enabling considerable pixel area reduction. The CAAC-OS FET can be driven even at a low refresh rate owing to its extremely low off-state current, making it an ideal choice for constructing pixel circuits. This integration of CAAC-OS FETs empowers our display system to offer enhanced resolution and reduced power consumption. The two-dimensionally arranged drivers have two features. (1) Si drivers can be arranged in two-dimensional driver blocks with a desired size, which provides flexibility to increase the number of driver stages and adjust resolution and frame rates for each driver block via logic processing. (2) The circuit performance of the system can be changed to prioritize frame rate and power consumption, which have a trade-off relation, of the driver by providing a redundant circuit in the driver. To demonstrate these features, we fabricated a prototype display and confirmed that our driver had a power consumption of 1,094.96 mW at 30 Gbps in a normal mode and 524.55 mW at 3.75 Gbps in a foveated rendering (FR) mode, revealing a 52% reduction in power consumption in the FR mode. This technology is expected to achieve high-frame-rate performance, which has been difficult to achieve in conventional microdisplays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10439975","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Performance Optimized Operational Amplifier Using Transconductance Enhancement Topology Based on a-IGZO TFTs 基于 a-IGZO TFT 的跨导增强拓扑结构的性能优化型运算放大器

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-16 DOI: 10.1109/JEDS.2024.3366554

Fanzhao Meng;Yi Li;Jun Li;Jie Liang;Jianhua Zhang

引用次数: 0

Improving the Manufacturability of Low-Temperature GaN Ohmic Contact by Blocking the Fluorine Ion Injection 通过阻断氟离子注入提高低温氮化镓欧姆触点的可制造性

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-16 DOI: 10.1109/JEDS.2024.3366804

Tong Liu;Xiangdong Li;Zhanfei Han;Lili Zhai;Junbo Wang;Shuzhen You;Jincheng Zhang;Jie Zhang;Zhibo Cheng;Yuanhang Zhang;Qiushuang Li;Yue Hao

{"title":"Improving the Manufacturability of Low-Temperature GaN Ohmic Contact by Blocking the Fluorine Ion Injection","authors":"Tong Liu;Xiangdong Li;Zhanfei Han;Lili Zhai;Junbo Wang;Shuzhen You;Jincheng Zhang;Jie Zhang;Zhibo Cheng;Yuanhang Zhang;Qiushuang Li;Yue Hao","doi":"10.1109/JEDS.2024.3366804","DOIUrl":"10.1109/JEDS.2024.3366804","url":null,"abstract":"Stabilizing the CMOS-compatible low-temperature Au-free GaN Ohmic contact is a critical work that determines the performance and yield of GaN power HEMTs in mass production. The instability of this contact has been puzzling the industry and academia for years. In this work, an overlooked factor, fluorine injection, is unambiguously verified to widely exist during dielectric etching and can easily destroy the low-temperature GaN Ohmic contact formation. The injection depth is confirmed to be over 30 nm with a fluorine peak concentration of 1023 at/cm3 in vicinity of the surface. Traditional method of partial AlGaN recessing with a pretty tiny processing window is proven unfriendly for production and vulnerable to the fluorine injection. Two methods to get rid of the fluorine are proposed. The first one is to over-etch the AlGaN barrier to the GaN channel to fully remove the fluorine ions. The second is to deposit an etch-stop blocking layer of Al2O3, which is also compatible with CMOS process.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10438851","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139956693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unsupervised Learning in a Ternary SNN Using STDP 使用 STDP 在三元 SNN 中进行无监督学习

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-15 DOI: 10.1109/JEDS.2024.3366199

Abhinav Gupta;Sneh Saurabh

{"title":"Unsupervised Learning in a Ternary SNN Using STDP","authors":"Abhinav Gupta;Sneh Saurabh","doi":"10.1109/JEDS.2024.3366199","DOIUrl":"10.1109/JEDS.2024.3366199","url":null,"abstract":"This paper proposes a novel implementation of a ternary Spiking Neural Network (SNN) and investigates it using a hierarchical simulation framework. The proposed ternary SNN is trained in an unsupervised manner using the Spike Timing Dependent Plasticity (STDP) learning rule. A ternary neuron is implemented using a Dual-Pocket Tunnel Field effect transistor (DP-TFET). The synapse consists of a Magnetic Tunnel Junction (MTJ) with a Heavy Metal (HM) underlayer, allowing for the adjustment of its conductance by directing a current through the HM layer. Further, we show that a pair of dual-pocket Fully-Depleted Silicon-on-Insulator (FD-SOI) MOSFETs can be utilized to generate a current, which reduces exponentially with increasing duration of firing events between pre- and post-synaptic neurons. This current modulates the synapse’s conductance according to STDP. Furthermore, it is demonstrated that the proposed ternary SNN can be trained to classify digits in the MNIST dataset with an accuracy of 82%, which is better (75%) than that obtained using a binary SNN. Moreover, the runtime required to train the proposed ternary SNN is \u0000<inline-formula> <tex-math>$8times $ </tex-math></inline-formula>\u0000 less than that required for a binary SNN.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10437991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient Annealing Process of Ferroelectric Hf0.5Zr0.5O2 Capacitor Using Ultraviolet-LED for Green Manufacturing 使用紫外 LED 的铁电 Hf0.5Zr0.5O2 电容器节能退火工艺，实现绿色制造

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-13 DOI: 10.1109/JEDS.2024.3365150

Hirotaka Yamada;Satoru Furue;Takehiko Yokomori;Yuki Itoya;Takuya Saraya;Toshiro Hiramoto;Masaharu Kobayashi

{"title":"Energy-Efficient Annealing Process of Ferroelectric Hf0.5Zr0.5O2 Capacitor Using Ultraviolet-LED for Green Manufacturing","authors":"Hirotaka Yamada;Satoru Furue;Takehiko Yokomori;Yuki Itoya;Takuya Saraya;Toshiro Hiramoto;Masaharu Kobayashi","doi":"10.1109/JEDS.2024.3365150","DOIUrl":"10.1109/JEDS.2024.3365150","url":null,"abstract":"Thermal annealing process plays an important role in the formation of ferroelectric phase in Hf0.5Zr0.5O2 (HZO) thin films. In this study, the annealing process of the HZO capacitors is demonstrated using ultraviolet (UV)-LED, for the first time. Since the absorptance of the HZO films with TiN electrodes is highest in UV region, the UV-LED annealing process is promising to achieve a much more energy-efficient annealing process than a conventional halogen lamp RTA method. It was experimentally confirmed that UV-LED annealing reduces the energy consumption by nearly half compared to the conventional method. The ferroelectric characteristics obtained by this method are comparable to those achieved by the halogen lamp RTA process at 400-450°C. Grazing incidence X-ray diffraction (GIXRD) pattern shows that no monoclinic phase is formed and only the tetragonal and orthorhombic phases are confirmed. It is also confirmed that there is the in-plane tensile stress remaining after the UV-LED annealing process, which is necessary for the formation of the ferroelectric orthorhombic phase.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10433786","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139956629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Fast Response Back-Illuminated 3-D Composite Electrode Silicon Detector Utilizing the RIE-Lag Phenomenon 利用 RIE 滞后现象设计快速响应背照式三维复合电极硅探测器

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-13 DOI: 10.1109/JEDS.2024.3365732

Wenzheng Cheng;Manwen Liu;Chenchen Zhang;Daimo Li;Zhihua Li

引用次数: 0

Flicker Noise (1/f) in 45-nm PDSOI N-Channel FETs at Cryogenic Temperatures for Quantum Computing Applications 用于量子计算应用的 45 纳米 PDSOI N 沟道场效应晶体管在低温条件下的闪烁噪声 (1/f)

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-13 DOI: 10.1109/JEDS.2024.3365216

Shruti Pathak;Sumreti Gupta;P. Srinivasan;Oscar H. Gonzalez;Fernando Guarin;Abhisek Dixit

{"title":"Flicker Noise (1/f) in 45-nm PDSOI N-Channel FETs at Cryogenic Temperatures for Quantum Computing Applications","authors":"Shruti Pathak;Sumreti Gupta;P. Srinivasan;Oscar H. Gonzalez;Fernando Guarin;Abhisek Dixit","doi":"10.1109/JEDS.2024.3365216","DOIUrl":"10.1109/JEDS.2024.3365216","url":null,"abstract":"In this paper, we have investigated the flicker noise (1/\u0000<inline-formula> <tex-math>$f$ </tex-math></inline-formula>\u0000) in 45-nm RFSOI NFETs for quantum computing applications. 1/\u0000<inline-formula> <tex-math>$f$ </tex-math></inline-formula>\u0000 noise characterization and analysis were performed in linear region at cryogenic temperatures down to 10K. A Lorentzian-like noise is also observed depending on bias conditions, possibly due to the floating body of PDSOI. The extracted frequency exponent \u0000<inline-formula> <tex-math>$(gamma)$ </tex-math></inline-formula>\u0000 shows an inverted U-shape behavior with temperature mainly attributed to non-uniform energy distribution of traps in the gate dielectric. The dominant source of 1/\u0000<inline-formula> <tex-math>$f$ </tex-math></inline-formula>\u0000 noise is carrier number fluctuation. Thermal-activation behavior of 1/\u0000<inline-formula> <tex-math>$f$ </tex-math></inline-formula>\u0000 noise is studied, which shows the traps responsible for noise are not thermally activated. Volume trap densities are also extracted from 300K down to 10K. The volume trap density increases with a decrease in temperature, but no significant increase in normalized noise is observed at cryogenic temperatures in the measured NFETs. The non-uniform distribution along with the thermal inactive behavior of traps over the studied temperature range is expected to be a plausible reason for the temperature-independent behavior of normalized noise.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10433783","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0