IEEE Journal of the Electron Devices Society最新文献_第9页

IGZO 2T1C DRAM With Low Operation Voltage and High Current Window 具有低工作电压和大电流窗的IGZO 2T1C DRAM

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-02 DOI: 10.1109/JEDS.2025.3566162

Wendong Lu;Kaifei Chen;Menggan Liu;Fuxi Liao;Zijing Wu;Naide Mao;Zihan Li;Xuanming Zhang;Congyan Lu;Jiebin Niu;Bok-Moon Kang;Jing-Hong Shi;Xie-Shuai Wu;Gui-Lei Wang;Zhengyong Zhu;Jiawei Wang;Lingfei Wang;Di Geng;Nianduan Lu;Guanhua Yang;Chao Zhao;Ling Li

{"title":"IGZO 2T1C DRAM With Low Operation Voltage and High Current Window","authors":"Wendong Lu;Kaifei Chen;Menggan Liu;Fuxi Liao;Zijing Wu;Naide Mao;Zihan Li;Xuanming Zhang;Congyan Lu;Jiebin Niu;Bok-Moon Kang;Jing-Hong Shi;Xie-Shuai Wu;Gui-Lei Wang;Zhengyong Zhu;Jiawei Wang;Lingfei Wang;Di Geng;Nianduan Lu;Guanhua Yang;Chao Zhao;Ling Li","doi":"10.1109/JEDS.2025.3566162","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3566162","url":null,"abstract":"In this work, we propose and experimentally demonstrate a novel IGZO 2T1C cell. Novel bit-cell applies read-word-line to the capacitor terminal and utilize the coupling effect of the capacitor to achieve storage node (SN) voltage modulation. By this design, a larger current window can be achieved by biasing the read transistor to the region with the steepest subthreshold slope. Through optimizing the gate dielectric thickness, DG IGZO transistor of <inline-formula> <tex-math>${mathrm { L}}_{mathrm {CH}}$ </tex-math></inline-formula>=50 nm achieves ultra-low subthreshold slope of 63.9 mV/dec. Based on optimized devices, the implementation of DRAM features an ultra-high current window (Idata‘1’/Idata‘0’) of <inline-formula> <tex-math>$sim {mathrm {10}}^{mathrm {3}}$ </tex-math></inline-formula> at ultra-low write voltage of 0.2 V. Furthermore, the proposed novel 2T1C bit-cell provides a more reliable gate-controlled read scheme. This work paves the forward way for low voltage and reliable sensing IGZO DRAM application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"444-449"},"PeriodicalIF":2.0,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981849","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) 负电容互补场效应管（CFET）设计优化的几点思考

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-27 DOI: 10.1109/JEDS.2025.3546314

Sandeep Semwal;Pin Su

引用次数: 0

Nanomole Process: Enabling Localized Metallic Back-Gates for Enhanced Cryogenic Front-to-Back Coupling in FDSOI Quantum Dots 纳米分子工艺：在FDSOI量子点中实现局部金属后门以增强低温前后耦合

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-25 DOI: 10.1109/JEDS.2025.3545661

Fabio Bersano;Niccolò Martinolli;Ilan Bouquet;Michele Ghini;Eloi Collette;Liza Žaper;Floris Braakman;Martino Poggio;Mathieu Luisier;Adrian Mihai Ionescu

{"title":"Nanomole Process: Enabling Localized Metallic Back-Gates for Enhanced Cryogenic Front-to-Back Coupling in FDSOI Quantum Dots","authors":"Fabio Bersano;Niccolò Martinolli;Ilan Bouquet;Michele Ghini;Eloi Collette;Liza Žaper;Floris Braakman;Martino Poggio;Mathieu Luisier;Adrian Mihai Ionescu","doi":"10.1109/JEDS.2025.3545661","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3545661","url":null,"abstract":"This paper introduces a novel integration method of localized metallic back-gates into fully-depleted silicon-on-insulator (FDSOI) multi-gate FETs, enabling robust front-to-back electrostatic coupling from room temperature to cryogenic conditions, without the need for substrate implantation. The fabrication process, termed the Nanomole process, utilizes nanometric vapor-phase etching of the buried oxide or silicon substrate with vapor-HF and XeF2 gases. This is followed by atomic layer deposition (ALD) of a dielectric material and Pt, with precise patterning achieved through inductively coupled plasma etching. Detailed analysis of the process demonstrates controllable etch rates based on device geometry, providing calibrated guidelines for scalable manufacturing. Symmetric mid-k dual-gating is reported in devices featuring a Si-film thickness of 24 nm, with a top and bottom gate oxide equivalent thickness (EOT) of 6.5 nm. Electrical characterization of multi-gate FDSOI SETs, operated as FETs, confirms effective threshold voltage tuning through dual-gate operation, with consistent performance from room temperature to millikelvin regimes. Additionally, quantum mechanical simulations based on the effective mass approximation at 4 K offer insights into the electrostatic behavior of dual-gated SOI quantum dot devices in both planar and nanowire geometries. This scalable and versatile technological solution opens new possibilities for advanced quantum devices, such as charge and spin qubits, by enabling in situ control over volume inversion, electron valley splitting, and spin-orbit interaction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"210-218"},"PeriodicalIF":2.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10902357","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Oxide Phototransistor Array With Multiply-and-Accumulation Functions for In-Sensor Image Processing 用于传感器内图像处理的具有乘法和累加函数的氧化物光电晶体管阵列

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-25 DOI: 10.1109/JEDS.2025.3545885

Saisai Wang;Xiaotao Jing;Wanlin Zhang;Rui Wang;Hong Wang;Qi Huang

{"title":"Oxide Phototransistor Array With Multiply-and-Accumulation Functions for In-Sensor Image Processing","authors":"Saisai Wang;Xiaotao Jing;Wanlin Zhang;Rui Wang;Hong Wang;Qi Huang","doi":"10.1109/JEDS.2025.3545885","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3545885","url":null,"abstract":"Advanced in-sensor computing paradigm has gradually become a research hotspot in this IOT era of sensor data proliferation. However, most existing in-sensor computing devices are plagued by a complex structure, and the uniformity of the sensor array is difficult to ensure. Moreover, photoconductive devices are incapable of achieving on-chip current summation because the regulation of photoresponsivity usually leads to inconsistent dark current, thereby impeding the practical implementation of artificial neural networks (ANNs) on the sensor array. In this work, we developed a <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> ultraviolet (UV) image sensor array based on solution-processed indium oxide (In2O3) phototransistors. The devices exhibit tunable responsivity and unified dark current under negative gate voltage (Vgs), enabling the direct execution of multiply-and-accumulation (MAC) operations. Consequently, two key applications of ANN were successfully demonstrated: image convolution and classification.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"378-382"},"PeriodicalIF":2.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10904187","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Power a-IGZO TFT Emission Driver With Shoot-Through Current-Free QB Control Block 具有通射无电流QB控制块的低功耗a-IGZO TFT发射驱动器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-24 DOI: 10.1109/JEDS.2025.3544840

Won-Been Jeong;Sang-Hoon Kim;Seung-Woo Lee

引用次数: 0

Characterization and Modeling of MOSFET Series Resistance Down to 4 K 低至4k的MOSFET串联电阻的表征与建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-21 DOI: 10.1109/JEDS.2025.3544738

Yuhuan Lin;Zhizhao Ma;Shilong Li;Tianyue Wen;Yuxuan Zhou;Hao Su;Shenghua Zhou;Longyang Lin;Yida Li;Kai Chen

引用次数: 0

Design of an Integrated MEMS Magnetic Gradiometer Rejecting Vibrations and Stray Fields 抑制振动和杂散场的集成MEMS磁梯度计设计

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-19 DOI: 10.1109/JEDS.2025.3543662

Enrico Gasparin;Arno Hoogerwerf;Dara Bayat;Guido Spinola Durante;Yves Petremand;Maurizio Tormen;Michel Despont;Gaël Close

{"title":"Design of an Integrated MEMS Magnetic Gradiometer Rejecting Vibrations and Stray Fields","authors":"Enrico Gasparin;Arno Hoogerwerf;Dara Bayat;Guido Spinola Durante;Yves Petremand;Maurizio Tormen;Michel Despont;Gaël Close","doi":"10.1109/JEDS.2025.3543662","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543662","url":null,"abstract":"Magnetic sensors are often used near current-carrying wires or electrical motors generating significant magnetic interference. To mitigate the effects of these stray fields, the traditional design approach relies on a differential sensing scheme: multiple magnetometers are spaced apart, and the field differences are measured. Despite being rejected, stray fields still constrain the design space. Extra linear range and matched channels are required to accommodate their peak amplitude without saturation or residual common-mode leakage. On the contrary, single-point MEMS gradiometers rely on the force acting on a magnet, which is directly proportional to the magnetic field gradient. The stray field is intrinsically rejected by the magnetic transducing mechanism, even before entering the measurement chain. The range of the measurement chain can then be largely optimized for the gradient, independently of the stray field amplitude. This paper discusses the design of a single-point MEMS gradiometer. By design, it rejects magnetic stray fields and mechanical disturbances like vibrations and gravity. It is the first single-point MEMS gradiometer capable of operating unshielded and in various orientations. The prototype achieves a noise density of 4 nT/mm/<inline-formula> <tex-math>$sqrt {mathrm { Hz}}$ </tex-math></inline-formula> within a measurement range of <inline-formula> <tex-math>${pm } 300~{mu }$ </tex-math></inline-formula>T/mm. The paper demonstrates the sensor’s effectiveness in a bus-bar current sensing application. Design limitations and future design prospects are also outlined.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"228-236"},"PeriodicalIF":2.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892099","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays 基于有机TFTs的高鲁棒集成栅极驱动器用于有源矩阵显示器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-18 DOI: 10.1109/JEDS.2025.3542951

Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li

{"title":"A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays","authors":"Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li","doi":"10.1109/JEDS.2025.3542951","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542951","url":null,"abstract":"A highly robust integrated gate driver based on organic thin-film transistors (OTFTs) is proposed that effectively addresses the output degradation caused by depletion-mode operation, instability and variation. The series-connected two-transistor structures and the inverters generate positive gateto- source voltages for internal nodes, which eliminate the leakage current and voltage ripples in depletion-mode operation and extend the support threshold voltage (<inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula>) range. The simulation waveforms of the 538th stage have no degradation, considering the <inline-formula> <tex-math>$Delta V_{TH}$ </tex-math></inline-formula> range from 1.18 to -0.53 V for single-gate (SG) OTFT and that from 2.13 to -8.07 V for dual-gate (DG) OTFT. The fabricated gate drivers generate stable scan signals with almost negligible voltage ripples for SG- and DG-OTFT with <inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula> of +7.9 and +1.8 V, respectively. In a 5.8-inch AMOLED panel (resolution: 538×302), the circuit can operate at a frame rate range from 1 to 45 Hz, driven by clocks with a frequency of 12.5 kHz and a swing from 0 to -15 V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"128-133"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891473","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Self-Aligned Staggered Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors With Ultra-Low Contact Resistance for High-Speed Circuits Application 自对准交错非晶铟镓锌氧化物薄膜晶体管的超低接触电阻应用于高速电路

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-18 DOI: 10.1109/JEDS.2025.3543212

Chuanke Chen;Xinlv Duan;Congyan Lu;Xichen Chuai;Wanming Wu;Chunyu Zhang;Chen Gu;Guanhua Yang;Nianduan Lu;Di Geng;Ling Li

引用次数: 0

Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform for Reliable Cryogenic IC Design 通用低温CMOS器件建模和eda兼容平台的可靠低温IC设计

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-17 DOI: 10.1109/JEDS.2025.3542589

Zhidong Tang;Zewei Wang;Yumeng Yuan;Chang He;Xin Luo;Ao Guo;Renhe Chen;Yongqi Hu;Longfei Yang;Chengwei Cao;Lin Lin Liu;Liujiang Yu;Ganbing Shang;Yongfeng Cao;Shoumian Chen;Yuhang Zhao;Shaojian Hu;Xufeng Kou

引用次数: 0