IEEE Journal of the Electron Devices Society最新文献

Call for Nominations for Editor-in-Chief 征集总编辑提名

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-07 DOI: 10.1109/JEDS.2024.3489072

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IEEE ELECTRON DEVICES SOCIETY 电子器件学会

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IEEE Journal of the Electron Devices Society Pub Date : 2025-01-07 DOI: 10.1109/JEDS.2023.3348195

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Foreword Special Issue on the 5th Latin American Electron Device Conference 第五届拉丁美洲电子器件会议特刊

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IEEE Journal of the Electron Devices Society Pub Date : 2024-12-30 DOI: 10.1109/JEDS.2024.3518273

Lluís F. Marsal;Arturo Escobosa;Benjamin Iñiguez;Fernando Guarín

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Golden List of Reviewers for 2024 2024年评论家金名单

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IEEE Journal of the Electron Devices Society Pub Date : 2024-12-30 DOI: 10.1109/JEDS.2024.3512073

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Impact of Self-Heating Effect on DC and AC Performance of FD-SOI CMOS Inverter 自热效应对FD-SOI CMOS逆变器直流和交流性能的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-12-27 DOI: 10.1109/JEDS.2024.3523286

Kang Hee Lee;Mincheol Kim;Jongmin Lee;Jang Hyun Kim

{"title":"Impact of Self-Heating Effect on DC and AC Performance of FD-SOI CMOS Inverter","authors":"Kang Hee Lee;Mincheol Kim;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2024.3523286","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3523286","url":null,"abstract":"We analyzed the impact of self-heating effect (SHE) on fully depleted-silicon on insulator (FD-SOI) CMOS inverter at the 28 nm technology node, considering both DC and AC operations. Specifically, we focused on investigating the principles behind how SHE influences inverter operating characteristics. To analyze the operating characteristics, we employed 2-D technology computer-aided design (TCAD) mixed mode simulation by Synopsys SentaurusTM. In DC operation, the maximum lattice temperature for n-MOSFET and p-MOSFET are 436 K and 449 K, respectively, resulting in a current degradation of 7.9%. Due to the shifted p/n ratio, the gain also varied, with values of 3.65 V/V for without SHE and 4.21 V/V for with SHE. In AC operation, the maximum temperature varies for each operating frequency: 439 K, 358 K, 324 K, and 319 K, from 10 MHz to 4 GHz. Consequently, the rate of p/n ratio deviation and the rate of voltage change over time vary accordingly. SHE exhibits a faster rate of change, showing a difference of 5.43% at 10 MHz. Analysis of propagation delay through an inverter chain showed a 10% increase at 10 MHz. The results indicate that with SHE, the propagation delay increases, and the slew rate becomes steeper, suggesting improved switching characteristics and gain. However, this unintended consequence highlights the necessity of considering SHE-induced changes in CMOS inverter design to ensure reliable operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"41-48"},"PeriodicalIF":2.0,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816664","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Novel Triple Diode Solar Cells Equivalent Circuit Models With Lambert W Function Expressions 基于Lambert W函数表达式的新型三二极管太阳能电池等效电路模型

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-12-26 DOI: 10.1109/JEDS.2024.3523278

Martin Ćalasan;Snežana Vujošević

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Charge-Based Compact Modeling of OECTs for Neuromorphic Applications 神经形态应用中基于电荷的oect紧凑建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-12-25 DOI: 10.1109/JEDS.2024.3522577

Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes

{"title":"Charge-Based Compact Modeling of OECTs for Neuromorphic Applications","authors":"Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes","doi":"10.1109/JEDS.2024.3522577","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3522577","url":null,"abstract":"Organic electrochemical transistors (OECTs) are a class of promising neuromorphic devices due to their exceptional conductivity, ease of fabrication, and cost-effectiveness. These devices exhibit ionic behavior similar to biological synapses, enabling efficient switching. Developing a compact model for OECTs is challenging due to the complex interplay of electrochemical reactions, ion transport, interactions with electrons or holes, and charge carrier dynamics that must be accurately captured and integrated into a simplified framework. In this work, we develop a combined physics-based compact model that integrates the Nernst equation from electrochemistry with thermally activated charges from semiconductor physics. This model enables easy incorporation into circuit simulations and provides a simple core framework for further extensions to account for additional effects. We fabricated, characterized, and analyzed OECTs based on PEDOT:PSS, and the proposed compact model shows good agreement with our experimental data.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"34-40"},"PeriodicalIF":2.0,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816051","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications 基于物理的spice -兼容的具有多晶硅通道的闪存紧凑型模型，用于内存计算应用

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-12-04 DOI: 10.1109/JEDS.2024.3511581

Jung Rae Cho;Donghyun Ryu;Donguk Kim;Wonjung Kim;Yeonwoo Kim;Changwook Kim;Yoon Kim;Myounggon Kang;Jiyong Woo;Dae Hwan Kim

{"title":"Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications","authors":"Jung Rae Cho;Donghyun Ryu;Donguk Kim;Wonjung Kim;Yeonwoo Kim;Changwook Kim;Yoon Kim;Myounggon Kang;Jiyong Woo;Dae Hwan Kim","doi":"10.1109/JEDS.2024.3511581","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3511581","url":null,"abstract":"Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1-7"},"PeriodicalIF":2.0,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778276","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Channel Mobility and Inversion Carrier Density in MFIS FEFET: Deep Insights Into Device Physics for Non-Volatile Memory Applications MFIS ffet中的通道迁移率和反转载流子密度：非易失性存储器应用的器件物理的深刻见解

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-11-27 DOI: 10.1109/JEDS.2024.3507379

Song-Hyeon Kuk;Kyul Ko;Bong Ho Kim;Joon Pyo Kim;Jae-Hoon Han;Sang-Hyeon Kim

{"title":"Channel Mobility and Inversion Carrier Density in MFIS FEFET: Deep Insights Into Device Physics for Non-Volatile Memory Applications","authors":"Song-Hyeon Kuk;Kyul Ko;Bong Ho Kim;Joon Pyo Kim;Jae-Hoon Han;Sang-Hyeon Kim","doi":"10.1109/JEDS.2024.3507379","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3507379","url":null,"abstract":"Ferroelectric polarization charge in doped-HfO2 such as HfZrOx (HZO) has a high surface density (~1014 cm-2) compared to the channel carrier (~1013 cm-2), thereby, ferroelectric polarization induces high electric field near the channel surface, critically impacting on the channel carrier behaviors in metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric field-effect-transistor (FEFET). In this context, channel mobility degradation by ferroelectric polarization and trapped charges will become a concern, because it is well-known that a huge number of charges (~1014 cm-2) are trapped at the gate stack. Especially, channel mobility during the read operation is required to be discussed, because FEFETs are typically targeted for non-volatile memory applications. In this work, we show that channel mobility (μch) and surface inversion carrier density (Ns,inv) in the n-channel FEFET (nFEFET) during read can be significantly different in the multi-level-cell (MLC) operation. This indicates that trapped carriers significantly degrade mobility and the degradation has a “history” effect, revealing that μch and Ns,inv are determined by overlapped effects of ferroelectric polarization and trapped charges. In addition, it is suggested that ferroelectric polarization induces remote phonon scattering. The complicated device physics of the MFIS FEFET indicates that channel mobility should be carefully modeled in the device simulation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"8-14"},"PeriodicalIF":2.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769066","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures 高温下碳化硅低压n/p沟道mosfet的表征

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-11-27 DOI: 10.1109/JEDS.2024.3506922

Hui Wang;Pengyu Lai;Affan Abbasi;Md Maksudul Hossain;Asif Faruque;H. Alan Mantooth;Zhong Chen

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