IEEE Journal of the Electron Devices Society最新文献

IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications 基于VTH补偿技术的多比特IGZO 2T0C DRAM

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-29 DOI: 10.1109/JEDS.2025.3565658

Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu

{"title":"IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications","authors":"Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu","doi":"10.1109/JEDS.2025.3565658","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3565658","url":null,"abstract":"In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"439-443"},"PeriodicalIF":2.0,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10979978","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications 用于射频、功率和光电子应用的超宽带隙半导体器件

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-28 DOI: 10.1109/JEDS.2025.3562252

引用次数: 0

Investigating the Switching Dynamics of Antiferroelectric Capacitor Using Multidomain Phase-Field Approach

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-25 DOI: 10.1109/JEDS.2025.3564212

Muhammad Mainul Islam;Mohammad Adnaan;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi

引用次数: 0

Analysis of InAs/InAsSb Superlattice Miniband Positions for a Cascade LWIR Detector 级联LWIR探测器InAs/InAsSb超晶格微带位置分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-24 DOI: 10.1109/JEDS.2025.3563981

K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk

{"title":"Analysis of InAs/InAsSb Superlattice Miniband Positions for a Cascade LWIR Detector","authors":"K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk","doi":"10.1109/JEDS.2025.3563981","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563981","url":null,"abstract":"The paper presents an analysis of the miniband transitions of long- infrared (LWIR) interband cascade photodetectors (ICIP), with type-II superlattices (T2SLs), gallium-free (“Ga-free”) InAs/InAsSb (xSb <inline-formula> <tex-math>${=}0.39$ </tex-math></inline-formula>) absorber, grown by molecular beam epitaxy (MBE) on a GaAs (001) substrate. The results collected based on the photoluminescence (PL) and spectral response (SR) measurements were combined with theoretical calculations using the (<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> Hamiltonian) k<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>p model for both strained and strain-free structure. The temperature dependence of HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, LH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, SO<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>C1 and HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1 was determined. Their respective 300 K energies were 114 meV, 195 meV, 290 meV and 380 meV, respectively. Moreover, the Varshni parameters were determined. For the PL results, 85 meV was observed across the entire temperature range. Remarkably, at cryogenic temperatures additional blue-shifted 5 meV and 14 meV transitions within the energy gap (Eg) occurred, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"390-395"},"PeriodicalIF":2.0,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Precision GaN-Based-SenseFET Design Based on a Lumped Parameter Electro-Thermal Network Model 基于集总参数电热网络模型的高精度gan传感场效应管设计

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-23 DOI: 10.1109/JEDS.2025.3563644

Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu

{"title":"High-Precision GaN-Based-SenseFET Design Based on a Lumped Parameter Electro-Thermal Network Model","authors":"Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu","doi":"10.1109/JEDS.2025.3563644","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563644","url":null,"abstract":"The lossless and accurate current sensing technology is highly desirable for feedback control, fast over-current protection, and diagnostics-prognostics development for high-frequency and high-efficiency power systems. The SenseFET technology, where a current sensor is monolithically integrated with a power transistor, has been widely used in power ICs due to its high precision and low cost. However, for a gallium nitride (GaN) lateral power device in multi-finger configurations, the non-uniform temperature distribution hinders its application in high-precision scenarios. This paper aims to address this issue through a design method of SenseFETs based on a lumped parameter electro-thermal network (LPETN) model. Based on the proposed model, the time-dependent temperature and conduction current distribution are obtained, and the optimized finger selection for the accurate current sense is performed. The thermal network part of the model is validated by the finite element method (FEM) results, and the electrical part is validated through LTSPICE simulation. Finally, taking a 50-finger GaN high electron mobility transistor (HEMT) device as an example, this model is used to select the fingers of a SenseFET for current sensing. Compared with the traditional method, the proposed approach significantly improves the accuracy of the SenseFET, which demonstrates its effectiveness.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"414-421"},"PeriodicalIF":2.0,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10974612","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Self-Heating Effects in RF Region of FDSOI MOSFETs at Cryogenic Temperatures 低温下FDSOI mosfet射频区的自热效应

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-21 DOI: 10.1109/JEDS.2025.3562752

Hung-Chi Han;Edoardo Charbon;Christian Enz

引用次数: 0

A Low Static-Power D Flip-Flop With Unipolar Thin Film Transistors on a Flexible Substrate 柔性衬底上单极薄膜晶体管的低静态功率D触发器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-21 DOI: 10.1109/JEDS.2025.3562575

Shubham Ranjan;Sparsh Kapar;Czang-Ho Lee;William Wong;Manoj Sachdev

{"title":"A Low Static-Power D Flip-Flop With Unipolar Thin Film Transistors on a Flexible Substrate","authors":"Shubham Ranjan;Sparsh Kapar;Czang-Ho Lee;William Wong;Manoj Sachdev","doi":"10.1109/JEDS.2025.3562575","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562575","url":null,"abstract":"There is increasing interest in affordable and flexible electronics, driven by the need for displays, conformable body sensors, and Internet-of-Things (IoT) gadgets. Amorphous silicon (a-Si:H), transition metal oxides, and organic thin-film transistors (TFTs) have demonstrated cost-effective large-scale production. As TFTs are typically unipolar in nature, they pose challenges for implementing CMOS-like circuits. Conventional methods to realize circuits in these technologies often lead to restricted voltage swing and excessive direct path current. While several methods have been proposed to counter the voltage swing issue, these methods fail to address the direct path current problem. This article presents low static-power D flip-flops (DFFs) using unipolar TFTs, which significantly reduces the direct path current. The proposed and conventional DFF designs were fabricated on a glass and flexible substrate using a-Si:H TFTs. Additionally, the impact of bending the flexible substrates was examined to assess the robustness and performance of the DFFs under mechanical strain. The measurement results show that the proposed design based DFF saves average total power by 79.8% compared to conventional design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"406-413"},"PeriodicalIF":2.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970726","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliable Multistate RRAM Devices for Reconfigurable CAM and IMC Applications 用于可重构CAM和IMC应用的可靠多状态RRAM器件

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-18 DOI: 10.1109/JEDS.2025.3562399

Shengpeng Xing;Zijian Wang;Zhen Wang;Pengtao Li;Xuemeng Fan;Ziyang Zhang;Guobin Zhang;Jianhao Kan;Qi Luo;Shuai Zhong;Yishu Zhang

{"title":"Reliable Multistate RRAM Devices for Reconfigurable CAM and IMC Applications","authors":"Shengpeng Xing;Zijian Wang;Zhen Wang;Pengtao Li;Xuemeng Fan;Ziyang Zhang;Guobin Zhang;Jianhao Kan;Qi Luo;Shuai Zhong;Yishu Zhang","doi":"10.1109/JEDS.2025.3562399","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562399","url":null,"abstract":"This work presents a reliable multistate RRAM device based on a Cu/Ta2O5/WO<inline-formula> <tex-math>${}_{text {3-x}}$ </tex-math></inline-formula>/Pt structure, utilizing fully CMOS-compatible materials. The device demonstrates four distinct resistive states under varying switching voltages, achieving a swift response time of 25 ns and an on/off ratio exceeding <inline-formula> <tex-math>$10{^{{4}}}$ </tex-math></inline-formula>. Additionally, it demonstrates a robust data retention time exceeding <inline-formula> <tex-math>$10^{6}$ </tex-math></inline-formula> seconds and endures more than <inline-formula> <tex-math>$10^{4}$ </tex-math></inline-formula> pulses in endurance tests. Statistical analysis conducted over 100 cycles across ten devices reveals consistent resistance characteristics, with variations maintained below 10%. Leveraging these advantages, the RRAM devices were integrated with MOS transistors to construct a 4T2R unit-based array, enabling reconfigurable applications such as analog voltage-based content-addressable memory (CAM) and in-memory computing (IMC) accelerators. Notably, the proposed solution reduces energy consumption by over 20% in CAM applications and significantly enhances energy efficiency for fingerprint recognition tasks through convolution operations, achieving more than three times the energy efficiency compared to conventional GPU and CPU systems while maintaining an accuracy of 98%.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"383-389"},"PeriodicalIF":2.0,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10969850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

>3kV NiO/Ga2O3 Heterojunction Diodes With Space-Modulated Junction Termination Extension and Sub-1V Turn-On >3kV NiO/Ga2O3异质结二极管，具有空间调制结端延伸和亚1v导通

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-17 DOI: 10.1109/JEDS.2025.3562028

Advait Gilankar;Abishek Katta;Nabasindhu Das;Nidhin Kurian Kalarickal

{"title":">3kV NiO/Ga2O3 Heterojunction Diodes With Space-Modulated Junction Termination Extension and Sub-1V Turn-On","authors":"Advait Gilankar;Abishek Katta;Nabasindhu Das;Nidhin Kurian Kalarickal","doi":"10.1109/JEDS.2025.3562028","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562028","url":null,"abstract":"This work demonstrates high-performance vertical NiO/Ga2O3 heterojunction diodes (HJDs) with a 2-step space-modulated junction termination extension. Distinct from the current state-of-the-art Ga2O3 HJDs, we achieve breakdown voltage exceeding 3 kV with a low turn on voltage (VON) of 0.8V, estimated at a forward current density (IF) of 1 <inline-formula> <tex-math>$A-cm^{text {-2}}$ </tex-math></inline-formula>. The measured devices exhibit excellent turn-on characteristics achieving 100 <inline-formula> <tex-math>$A-cm^{text {-2}}$ </tex-math></inline-formula> current density at a forward bias of 1.5V along with a low differential specific on-resistance (Ron,sp) of 4.4 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-cm2. The SM-JTE was realized using concentric NiO rings with varying widths and spacing that approximates a gradual reduction in JTE charge. The unipolar figure of merit (FOM) calculated exceeds 2 GW-cm2 and is among the best reported for devices with a sub-1V turn-on. The fabricated devices also displayed minimal change in forward I-V characteristics post reverse bias stress of 3 kV applied during breakdown voltage testing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"373-377"},"PeriodicalIF":2.0,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10967383","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Call for Nominations for Editor-in-Chief IEEE Electron Device Letters IEEE电子设备通讯总编辑提名

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-10 DOI: 10.1109/JEDS.2025.3558645

引用次数: 0