IEEE Journal of the Electron Devices Society最新文献

Call for Nominations for Editor-in-Chief IEEE Electron Device Letters

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-10 DOI: 10.1109/JEDS.2025.3558645

引用次数: 0

Call for Nominations for Editor-in-Chief IEEE Transactions on Electron Devices(TED)

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-10 DOI: 10.1109/JEDS.2025.3558646

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Cryogenic InP HEMTs With Enhanced fmax and Reduced On-Resistance Using Double Recess

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-03 DOI: 10.1109/JEDS.2025.3557432

Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin

{"title":"Cryogenic InP HEMTs With Enhanced fmax and Reduced On-Resistance Using Double Recess","authors":"Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin","doi":"10.1109/JEDS.2025.3557432","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557432","url":null,"abstract":"Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device’s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device’s RON is <inline-formula> <tex-math>$410~Omega cdot mu $ </tex-math></inline-formula>m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device’s maximum oscillation frequency(<inline-formula> <tex-math>$f_{max }$ </tex-math></inline-formula>) by reducing the parasitic capacitance. At 7 K, the device’s <inline-formula> <tex-math>$f_{max }$ </tex-math></inline-formula> reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the <inline-formula> <tex-math>$rm Si_{3}N_{4}$ </tex-math></inline-formula> passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device’s cryogenic performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"366-372"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10948522","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing Pulse Conditions for Enhanced Memory Performance of Se-Based Selector-Only Memory

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-03 DOI: 10.1109/JEDS.2025.3557732

Jangseop Lee;Taras Ravsher;Daniele Garbin;Sergiu Clima;Robin Degraeve;Attilio Belmonte;Hyunsang Hwang;Inhee Lee

{"title":"Optimizing Pulse Conditions for Enhanced Memory Performance of Se-Based Selector-Only Memory","authors":"Jangseop Lee;Taras Ravsher;Daniele Garbin;Sergiu Clima;Robin Degraeve;Attilio Belmonte;Hyunsang Hwang;Inhee Lee","doi":"10.1109/JEDS.2025.3557732","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557732","url":null,"abstract":"In this study, we investigated the effect of pulse falling time (Tfall) on the electrical characteristics of SiGeAsSe-based selector-only memory (SOM) devices. Our experimental results demonstrate that increasing the <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> leads to an increased threshold voltage (Vth) and reduced <inline-formula> <tex-math>$mathrm { V_{th}}$ </tex-math></inline-formula> drift in SiGeAsSe devices. The optimized devices exhibit a remarkable memory window (> 1 V) and significantly suppressed drift characteristics (~10 mV/dec.). Electrical measurements at high temperatures demonstrate that <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> is one of the important factors in material relaxation, and these improvements are attributed to the intentionally induced reconfiguration of the chalcogenide film. Furthermore, our results reveal that a suitable <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> can effectively mitigate the degradation of the memory window at high temperatures. These findings afford valuable insights into the role of material relaxation in SOM devices, potentially aiding the development of high-performance memory devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"362-365"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10949046","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143830515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Modeling the Increase in Effective Mobility in Short-Channel Oxide Thin-Film Transistors 短沟道氧化物薄膜晶体管有效迁移率增长建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-03 DOI: 10.1109/JEDS.2025.3557401

Oliver Durnan;Reem Alshanbari;Hong-Rae Cho;Ioannis Kymissis;Chang-Hyun Kim

引用次数: 0

Proposal and Simulation of β-Ga₂O₃ Hetero- Junction Schottky Diodes With Low Work-Function Anode and High Breakdown Voltage

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-01 DOI: 10.1109/JEDS.2025.3556408

Ce Wang;Hong Zhou;Sami Alghamdi;Chunxu Su;Zhihong Liu;Kui Dang;Xuefeng Zheng;Xiaohua Ma;Peijun Ma;Yue Hao;Jincheng Zhang

{"title":"Proposal and Simulation of β-Ga₂O₃ Hetero- Junction Schottky Diodes With Low Work-Function Anode and High Breakdown Voltage","authors":"Ce Wang;Hong Zhou;Sami Alghamdi;Chunxu Su;Zhihong Liu;Kui Dang;Xuefeng Zheng;Xiaohua Ma;Peijun Ma;Yue Hao;Jincheng Zhang","doi":"10.1109/JEDS.2025.3556408","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556408","url":null,"abstract":"In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (Von) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm2, simultaneously. The proposed structure provides a new approach for realizing high performance <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 SBDs with high reverse blocking and low loss capabilities.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"334-342"},"PeriodicalIF":2.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945755","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-31 DOI: 10.1109/JEDS.2025.3552036

Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter

{"title":"Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory","authors":"Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter","doi":"10.1109/JEDS.2025.3552036","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552036","url":null,"abstract":"This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of (<inline-formula> <tex-math>$10{^{{7}}}~I_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{0}$ </tex-math></inline-formula> sense current ratio) and prolonged retention. The memory is enabled by the bistable <inline-formula> <tex-math>$I_{D}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V_{G}$ </tex-math></inline-formula> transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to <inline-formula> <tex-math>$approx ~45$ </tex-math></inline-formula> ns at T < 10 K and cycling endurance surpassing <inline-formula> <tex-math>$10^{9}$ </tex-math></inline-formula> cycles while maintaining the <inline-formula> <tex-math>$I_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{0}$ </tex-math></inline-formula> memory window. Retention times of >10 s with a 30x memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W-range) candidate for local cache memory to support quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"355-361"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10946245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors 应变工程二维 MoTe2 相变晶闸管的性能和可扩展性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-31 DOI: 10.1109/JEDS.2025.3556316

Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu

{"title":"Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors","authors":"Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu","doi":"10.1109/JEDS.2025.3556316","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556316","url":null,"abstract":"This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math>$leq 0.5$ </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math>$geq 10{^{{5}}}$ </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math>$leq 0.6mu $ </tex-math></inline-formula>m and A<inline-formula> <tex-math>$leq 0.3mu $ </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math>$leq 1.2mu $ </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math>$leq 65{^{text {o}}}$ </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"343-349"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945750","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-27 DOI: 10.1109/JEDS.2025.3555327

Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu

{"title":"AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications","authors":"Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu","doi":"10.1109/JEDS.2025.3555327","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3555327","url":null,"abstract":"Fin Field-Effect-Transistor (FinFET) has become fundamental components in advanced integrated circuit, while the drain-extended FinFET (DE-FinFET) features a lightly doped drain extension region to improve the device’s breakdown voltage. However, both structural refinement and the optimal integration of various parameters remain limited in achieving comprehensive optimization of device performance. This study introduces a novel DE-FinFET featuring a stepped field plate to improve overall performance of device. Moreover, within an AI-assisted design framework, predictive modeling and multi-objective optimization of the device are accomplished using Kolmogorov–Arnold Networks (KAN) and the Nondominated Sorting Genetic Algorithm (NSGA-III). More importantly, the proposed framework enables efficient device design and performance evaluation, achieving an average prediction accuracy of 98.19% for electrical performance metrics while being over two million times faster than traditional Technology Computer-Aided-Design (TCAD) simulations. In addition, it effectively generates Pareto-optimal solutions, delivering an average improvement of 9.03% across key electrical performance metrics. The proposed novel device of DE-FinFET offers a new route toward tailoring electrical properties. Meanwhile, the methodology of AI-assisted design not only accelerates device design but also enables customizable solutions for multi-purpose applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"326-333"},"PeriodicalIF":2.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10943177","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Editorial for the J-EDS Special Issue for ESSERC 2024

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-21 DOI: 10.1109/JEDS.2025.3547035

Anne S. Verhulst

引用次数: 0