IEEE Journal of the Electron Devices Society最新文献

RESURF Ga2O3-on-SiC Field Effect Transistors for Enhanced Breakdown Voltage 用于提高击穿电压的复用Ga2O3-on-SiC场效应晶体管

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-14 DOI: 10.1109/JEDS.2025.3584977

Junting Chen;Xiaohan Zhang;Junlei Zhao;Jin Wei;Mengyuan Hua

{"title":"RESURF Ga2O3-on-SiC Field Effect Transistors for Enhanced Breakdown Voltage","authors":"Junting Chen;Xiaohan Zhang;Junlei Zhao;Jin Wei;Mengyuan Hua","doi":"10.1109/JEDS.2025.3584977","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3584977","url":null,"abstract":"Heterosubstrates have been extensively studied as a method to improve the heat dissipation of Ga2O3 devices. In this simulation work, we propose a novel role for p-type available heterosubstrates, as a component of a reduced surface field (RESURF) structure in Ga2O3 lateral field-effect transistors (FETs). The RESURF structure can eliminate the electric field crowding and contribute to higher breakdown voltage. Using SiC as an example, the designing strategy for doping concentration and dimensions of the p-type region is systematically studied using TCAD modeling. Meanwhile, the interface charges and Al2O3 interlayer that could exist in realistic devices are mimicked in the simulation. Additionally, the feasibility of the RESURF structure for high-frequency switching operation is supported by the simulation on charging/discharging time the p-SiC depletion region. This study demonstrates the great potential of utilizing the electrical properties of heat-dissipating heterosubstrates to achieve a uniform electric field distribution in Ga2O3 FETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"570-576"},"PeriodicalIF":2.0,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11080126","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cross-Temperature FeFETs Enabling Long- and Short-Term Memory for Reservoir Computing Network 油藏计算网络中实现长短期记忆的交叉温度效应

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-03 DOI: 10.1109/JEDS.2025.3585619

Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen

{"title":"Cross-Temperature FeFETs Enabling Long- and Short-Term Memory for Reservoir Computing Network","authors":"Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen","doi":"10.1109/JEDS.2025.3585619","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3585619","url":null,"abstract":"Hardware neural networks based on emerging nonvolatile memory are promising candidates to overcome the Von Neumann computing bottleneck. This study investigates the device characteristics and reliability of ferroelectric field-effect transistors (FeFETs) with a focus on their temperature-dependent performance. At 300 K, the FeFET demonstrates a 6.2 V memory window (MW) with 26.4% endurance degradation after 107 program/erase (P/E) cycles and 92.39% retention after 104 s. The accelerated charge trapping/detrapping dynamics enable superior short-term memory (STM) functionality. Remarkably, cryogenic operation at 77 K enhances the MW to 8 V while achieving exceptional stability with merely 0.4% degradation after 107 cycles and 99.02% retention at 104 seconds. The enhanced characteristics make it ideal for long-term memory (LTM) applications. Moreover, a reservoir computing (RC) network is proposed based on the cross-temperature FeFETs. By integrating the STM properties at 300 K and the LTM benefits at 77 K, the proposed RC network achieves a classification accuracy of 76.73% on the CIFAR-10 image recognition task. This surpasses the standalone results of 41.65% and 23.69% of 300 K and 77 K conditions, respectively. The findings highlight the potential to develop highly energy-efficient FeFET-based neuromorphic computing with varying temperature systems.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"582-586"},"PeriodicalIF":2.0,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11067954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimization of Guard Ring Structures for Superior Dark Current Reduction and Improved Quantum Efficiency in InGaAs/InP APDs InGaAs/InP apd中保护环结构的优化及暗电流减小和量子效率的提高

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-27 DOI: 10.1109/JEDS.2025.3583669

Zefang Xu;Yu Chang;Kai Qiao;Liyu Liu;Linmeng Xu;Mengyan Fang;Chang Su;Fei Yin;Jieying Wang;Tianye Liu;Ming Li;Dian Wang;Lizhi Sheng;Xing Wang

{"title":"Optimization of Guard Ring Structures for Superior Dark Current Reduction and Improved Quantum Efficiency in InGaAs/InP APDs","authors":"Zefang Xu;Yu Chang;Kai Qiao;Liyu Liu;Linmeng Xu;Mengyan Fang;Chang Su;Fei Yin;Jieying Wang;Tianye Liu;Ming Li;Dian Wang;Lizhi Sheng;Xing Wang","doi":"10.1109/JEDS.2025.3583669","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583669","url":null,"abstract":"Avalanche photodiodes (APDs) based on InGaAs/InP are pivotal for applications in low-light detection, yet their performance is often hindered by edge breakdown and high dark currents. This study systematically optimizes guard ring structures to address these challenges, focusing on attached guard rings (AGRs) and floating guard rings (FGRs) through a synergistic approach combining simulation-guided design, fabrication, and experimental validation. We analyze the impact of Zn diffusion depth, AGR/FGR geometries, and electric field distribution on device performance. Experimental results demonstrate that optimized AGR structures reduce dark currents by 70% and enhance quantum efficiency (QE) by 43%, while FGR structures achieve an order-of-magnitude reduction in dark current and a 90% QE improvement compared to non-guarded devices. The breakdown voltage increases by 2.5 V (AGR) and 4 V (FGR), leading to enhanced gain. These advancements highlight the critical role of guard ring optimization in effectively mitigating edge breakdown, offering a pathway to high-sensitivity InGaAs/InP APDs for photon detection technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"551-557"},"PeriodicalIF":2.0,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11053970","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unraveling the Origins of Fatigue in Hafnia Ferroelectric Capacitors 揭示铪铁电电容器疲劳的起源

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-27 DOI: 10.1109/JEDS.2025.3583931

Hyeon-Seo Do;Ik-Jyae Kim;Jiwoung Choi;Jang-Sik Lee

引用次数: 0

Electrical Tunability in 3-Gated Reconfigurable Transistor for Analog/RF Applications 模拟/射频应用中3门可重构晶体管的电可调性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-20 DOI: 10.1109/JEDS.2025.3581677

Chinmayi Adoni;Sandeep Semwal;Manish Gupta;Jean-Pierre Raskin;Abhinav Kranti

{"title":"Electrical Tunability in 3-Gated Reconfigurable Transistor for Analog/RF Applications","authors":"Chinmayi Adoni;Sandeep Semwal;Manish Gupta;Jean-Pierre Raskin;Abhinav Kranti","doi":"10.1109/JEDS.2025.3581677","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3581677","url":null,"abstract":"The potential of electrical tunability in a 3-gated (3G) Reconfigurable Field Effect Transistor (RFET) for analog/RF applications is investigated through four distinct configurations (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula>, R<inline-formula> <tex-math>${}_{text {1-IG-Ambi}}$ </tex-math></inline-formula>, R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>, and R<inline-formula> <tex-math>${}_{text {2-IG-HVT}}$ </tex-math></inline-formula>). The electrical connections through two program gates (PG) and one control gate (CG) in 3G-RFET supports the implementation of configurations suitable for low-VTH (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula> and R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>) and high-VTH (R<inline-formula> <tex-math>${}_{text {2-IG-HVT}}$ </tex-math></inline-formula>), phase follower/reversal (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula>), frequency doubler (R<inline-formula> <tex-math>${}_{text {1-IG-Ambi}}$ </tex-math></inline-formula>), high gain (R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>), lower parasitic capacitance (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula> and R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>), and higher linearity (R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>) applications. Results showcase electrical tunability as an opportunity to realize many analog/RF features–in–one nanoscale 3G-RFET.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"558-565"},"PeriodicalIF":2.0,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11045726","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Defects on the Low-Field Electron Mobility in GaN-on-Si HEMTs GaN-on-Si hemt中缺陷对低场电子迁移率的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-11 DOI: 10.1109/JEDS.2025.3577260

Ran Zhou;D. J. Gravesteijn;R. J. E. Hueting

{"title":"Impact of Defects on the Low-Field Electron Mobility in GaN-on-Si HEMTs","authors":"Ran Zhou;D. J. Gravesteijn;R. J. E. Hueting","doi":"10.1109/JEDS.2025.3577260","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3577260","url":null,"abstract":"In this work, we investigate the field and temperature dependence of the electron mobility in aluminum-gallium-nitride/gallium-nitride (AlGaN/GaN) high electron mobility transistors (HEMTs) realized on GaN-on-silicon (Si) substrates. For this purpose we employ an extraction method to eliminate parasitic and fringing effects. Our results show that especially at low fields the temperature dependence of the mobility, and consequently that of the specific on-resistance, is strongly affected by stress-induced charged dislocation scattering. For explaining the mobility behaviour at low fields, the subthreshold operation regime of the HEMTs has also been analyzed. An interface trap density at the AlGaN/GaN interface <inline-formula> <tex-math>$(N_{textrm {it}})$ </tex-math></inline-formula> of <inline-formula> <tex-math>$sim ~6.9times 10^{10}$ </tex-math></inline-formula> cm−2 has been extracted independent of the temperature which is close to the extracted dislocation density from mobility measurements. This suggests that the relatively high dislocation density in the GaN layer, which is a consequence of the still imperfect buffer layer in the GaN-on-Si substrate that is used to accommodate the strain difference, has an impact on <inline-formula> <tex-math>$N_{textrm {it}}$ </tex-math></inline-formula>, thus subthreshold swing, in addition to the mobility reduction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"516-523"},"PeriodicalIF":2.0,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11031174","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144472684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability of Gap-Type Thin Film Transistors Under Low Illumination for Imaging Sensing Applications 低照度下成像传感用间隙型薄膜晶体管的可靠性研究

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-11 DOI: 10.1109/JEDS.2025.3578547

Ya-Hsiang Tai;Chih-Chung Tu;Chi-Hao Lin;Chi-Fan Lu

{"title":"Reliability of Gap-Type Thin Film Transistors Under Low Illumination for Imaging Sensing Applications","authors":"Ya-Hsiang Tai;Chih-Chung Tu;Chi-Hao Lin;Chi-Fan Lu","doi":"10.1109/JEDS.2025.3578547","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3578547","url":null,"abstract":"In large-area image sensing applications, such as under-display fingerprint sensors, amorphous silicon (a-Si) gap-type thin-film transistors (TFTs) are favored due to their simple fabrication process and high sensing current. These applications typically involve device operation under low-light illumination conditions. Despite these advantages, the recovery behavior of performance parameters after exposure to stress factors, including bias stress and photo-stress, has not been comprehensively explored, particularly in relation to reliability recovery. This study systematically investigates the impact of fixed-bias and pulsed-stress operations under low-light conditions. The experimental findings are further analyzed using Technology Computer-Aided Design (TCAD) simulations to elucidate the underlying mechanisms. Results indicate that long-term bias stress induces significant variations in the photocurrent characteristics of the devices. However, the introduction of pulsed operations in sensing applications markedly enhances the operational lifetime of the devices, offering a promising pathway to improving their reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"524-531"},"PeriodicalIF":2.0,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11030751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Erratum to “Charge-Based Compact Modeling of OECTs for Neuromorphic Applications” “神经形态应用中基于电荷的oect紧凑建模”的勘误表

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-10 DOI: 10.1109/JEDS.2025.3572172

Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes

引用次数: 0

IEEE ELECTRON DEVICES SOCIETY 电子器件学会

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-05 DOI: 10.1109/JEDS.2025.3576507

引用次数: 0

Enabling Selective and Tunable Weight Updates in All-InGaZnO 3-Transistor 1-Capacitor Synaptic Circuits for On-Chip Training 在All-InGaZnO 3-晶体管1-电容突触电路中实现选择性和可调谐的权重更新，用于片上训练

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-05 DOI: 10.1109/JEDS.2025.3576795

Minseung Kang;Mingi Kim;Jaehyeon Kang;Jongun Won;Hyeong Jun Seo;Changhoon Joe;Youngchae Roh;Yeaji Park;Sangbum Kim

{"title":"Enabling Selective and Tunable Weight Updates in All-InGaZnO 3-Transistor 1-Capacitor Synaptic Circuits for On-Chip Training","authors":"Minseung Kang;Mingi Kim;Jaehyeon Kang;Jongun Won;Hyeong Jun Seo;Changhoon Joe;Youngchae Roh;Yeaji Park;Sangbum Kim","doi":"10.1109/JEDS.2025.3576795","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3576795","url":null,"abstract":"Capacitor-based analog synaptic circuit arrays proposed so far typically required more than three transistors per synapse to enable selective updates for parallel backpropagation updates. For the first time, an innovative update scheme that enables selective updating without requiring additional transistors is demonstrated. This approach is experimentally validated through an all-InGaZnO (IGZO) thin-film transistor (TFT) 3-transistor 1-capacitor (3T1C) synaptic circuit. IGZO TFTs are specifically chosen for their ability to extend retention times due to extremely low leakage currents and their simplified fabrication processes at low temperatures. Fundamental synaptic operations, including controllable weight updates, long data retention, and stable programming endurance, are confirmed experimentally. Additionally, optimizing operational voltage conditions improves weight update behavior, which enhances network training performance. System-level analysis using a neural network hardware simulator with a derived weight update model demonstrates high training accuracy on the MNIST handwritten digit dataset and achieves maximum accuracy over 98%. With the proposed selection method and tunable weight updates, 3T1C synaptic circuit is a promising candidate for scalable large-scale deep neural network accelerators based on analog compute-in-memory technology.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"510-515"},"PeriodicalIF":2.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11026025","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144367074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0