IEEE Journal of the Electron Devices Society最新文献

{"title":"Kr-Plasma Process for Conductance Control of MFSFET With FeND-HfO2 Gate Insulator","authors":"S. Ohmi, M. Tanuma, J.W. Shin","doi":"10.1109/jeds.2024.3462930","DOIUrl":"https://doi.org/10.1109/jeds.2024.3462930","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully Integrated GaN-on-Silicon Power-Rail ESD Clamp Circuit Without Transient Leakage Current During Normal Power-on Operation","authors":"Wei-Cheng Wang;Ming-Dou Ker","doi":"10.1109/JEDS.2024.3462590","DOIUrl":"10.1109/JEDS.2024.3462590","url":null,"abstract":"When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10681588","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Combining Intelligence With Rules for Device Modeling: Approximating the Behavior of AlGaN/GaN HEMTs Using a Hybrid Neural Network and Fuzzy Logic Inference System","authors":"Ahmad Khusro;Saddam Husain;Mohammad S. Hashmi","doi":"10.1109/JEDS.2024.3461169","DOIUrl":"10.1109/JEDS.2024.3461169","url":null,"abstract":"This paper uses the Adaptive Neuro-Fuzzy Inference System (ANFIS) to investigate and propose a new alternative behavioral modeling technique for microwave power transistors. Utilizing measured I-V characteristics, associated parameters like transconductance \u0000<inline-formula> <tex-math>$(g_{text {m}})$ </tex-math></inline-formula>\u0000 and output conductance \u0000<inline-formula> <tex-math>$(g_{text {ds}})$ </tex-math></inline-formula>\u0000, etc., S-parameters characteristics, and RF performance parameters such as unity current gain frequency \u0000<inline-formula> <tex-math>$(f_{text {T}})$ </tex-math></inline-formula>\u0000, maximum unilateral gain frequency \u0000<inline-formula> <tex-math>$(f_{max })$ </tex-math></inline-formula>\u0000, ANFIS-based behavioral models are developed for Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) and validated. The models have been developed using two distinct devices with dimensions of \u0000<inline-formula> <tex-math>$10times 200~mu m$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$10times 250~mu m$ </tex-math></inline-formula>\u0000 for multi-bias conditions and over a broad frequency range (0.5 to 43.5 GHz). Subsequently, the proposed model performance is validated on devices with geometries of \u0000<inline-formula> <tex-math>$10times 220~mu m$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$4times 100~mu m$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$2times 200~mu m$ </tex-math></inline-formula>\u0000 to examine the interpolation accuracy, extrapolation potential, and scalability. Here, ANFIS utilizes the subtractive clustering method to process the measurement characteristics by computing the clusters and opts for the best-performing model using error and number of fuzzy rules as criteria. The parameters involved in the fuzzy representation are trained using neural network algorithms, namely gradient-descent and least squares estimate. The proposed models are subsequently incorporated in a commercial circuit simulator (Keysight’s ADS) and the class-F power amplifier’s gain and stability characteristics are computed and studied.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10680392","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach","authors":"Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh","doi":"10.1109/jeds.2024.3459872","DOIUrl":"https://doi.org/10.1109/jeds.2024.3459872","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Parallel In-Memory Logic Array Based on Programmable Diodes","authors":"Jiabao Ye;Junyu Zhu;Jifang Cao;Haoxiong Bi;Yong Ding;Bing Chen","doi":"10.1109/JEDS.2024.3457021","DOIUrl":"10.1109/JEDS.2024.3457021","url":null,"abstract":"Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode—a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10674001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142198876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer-Scale Monolithic Integration of LEDs With p-GaN-Depletion MOSFETs on a GaN LED Epitaxial Layer","authors":"Boseong Son, Huijin Kim, Young-Woong Lee, Purusottam Reddy Bommireddy, Si-Hyun Park","doi":"10.1109/jeds.2024.3455256","DOIUrl":"https://doi.org/10.1109/jeds.2024.3455256","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Negative Activation Energy of Gate Reliability in Schottky-Gate p-GaN HEMTs: Combined Gate Leakage Current Modeling and Spectral Electroluminescence Investigation","authors":"Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini","doi":"10.1109/JEDS.2024.3454334","DOIUrl":"10.1109/JEDS.2024.3454334","url":null,"abstract":"For the first time, we use electrical characterization, spectrally-resolved electroluminescence measurements and degradation tests to explain the negative activation energy of gate reliability in power GaN HEMTs with p-GaN Schottky gate. First, the origin of gate leakage current was modeled. The results indicate that the gate leakage current originates from three different mechanisms: (i) thermionic emission of electrons from the uid-GaN layer across the AlGaN barrier, for gate voltages below threshold \u0000<inline-formula> <tex-math>$(V_{G} lt V_{TH})$ </tex-math></inline-formula>\u0000, (ii) thermionic emission of electrons from the channel to the p-GaN layer \u0000<inline-formula> <tex-math>$(V_{TH} lt V_{G} lt 4.5 V)$ </tex-math></inline-formula>\u0000 and (iii) trap-assisted-tunneling of holes at the Schottky metal for higher gate voltages. Then, the analysis of the reliability as function of gate bias demonstrated a negative activation energy (longer lifetime at high temperature). By analyzing the electroluminescence spectra under high positive bias, the improved time to failure at high temperatures was ascribed to the increased hole injection and recombination, that reduces the overall number of electrons that undergo avalanche multiplication, leading to the breakdown. Finally, the model was validated by comparing the electrical properties and conduction model of the devices pre- and post-stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10664574","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly Uniform Low Gray AMOLED Pixel Using Stable Circuit and Duty Ratio Modulation Driving","authors":"Chanjin Park;Hee-Ok Kim;Jong-Heon Yang;Jae-Eun Pi;Yong-Duck Kim;Chun-Won Byun;Kyeong-Soo Kang;Ji-Hwan Park;Minji Kim;Hyoungsik Nam;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3452753","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3452753","url":null,"abstract":"In this paper, a new pixel circuit for active matrix organic light-emitting diode (AMOLED) display that can achieve high uniformity in low gray levels and its driving method are proposed. The proposed circuit compensates for threshold voltage variation of thin-film-transistors (TFTs), with the structure that minimizes the loss of sensed threshold voltage. However, the high current error rate in extremely low gray level is unavoidable, as the driving TFT (DRT) operates in subthreshold region, where the current difference caused by the threshold voltage variation can be severe. To suppress high error rates in low gray levels, the operation region of DRT is restricted to the saturation region, by adopting duty ratio modulation (DRM) method. With the DRM method, low gray is expressed with high current value and short emission time. The viability of the proposed circuit and its operation are analyzed with HSPICE. Compared to the conventional driving method, DRM significantly reduces the current error rate in low gray area. The proposed circuit is fabricated within 220 \u0000<inline-formula> <tex-math>$mu {mathrm {m}} times 440 mu {mathrm {m}}$ </tex-math></inline-formula>\u0000. The measurement of the circuit also verified the capability of the proposed circuit and the DRM method.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142159891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Approach to Determine Noise Model Parameter for Submicron MOSFET from RF Noise Figure Measurement","authors":"Hanqi Gao;Jing Jin;Jianjun Zhou","doi":"10.1109/JEDS.2024.3453408","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3453408","url":null,"abstract":"An extraction method to obtain the noise model parameter \u0000<inline-formula> <tex-math>$T_{mathrm { d}}$ </tex-math></inline-formula>\u0000 in deep submicron MOSFETs directly from radio frequency (RF) scattering parameters and noise figure measurements is presented. A simplified noise equivalent circuit, along with closed-form solutions to calculate the RF noise figure of MOSFET is developed. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for \u0000<inline-formula> <tex-math>$16times 1times 2{{mu }rm m}$ </tex-math></inline-formula>\u0000 (number of gate fingers \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 unit gatewidth \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 cells) gatelength MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663413","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Power 190 GHz Frequency Doubler Based On GaAs Schottky Diode","authors":"Nan Wu;Zhi Jin;Jingtao Zhou;Haomiao Wei;Zhicheng Liu;Jianming Lin","doi":"10.1109/JEDS.2024.3453122","DOIUrl":"10.1109/JEDS.2024.3453122","url":null,"abstract":"The research on high power 190 GHz doubler based on the GaAs Schottky diodes is proposed in this paper. The frequency doubler comprises a improved diode configuration that increases the number of anodes by changing the diode arrangement to improve power handling capacity. Electromagnetic and thermal simulation is utilized to demonstrate that the doubler can carry more power. The input power is gradually pumping from 200 mW to 500 mW with an applied DC bias of −15 V. And the peak efficiency of the doubler is measured to be 17%, while the maximum output power is 85 mW at 190 GHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663496","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}