IEEE Journal of the Electron Devices Society最新文献

A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm²

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-13 DOI: 10.1109/JEDS.2025.3533920

Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu

{"title":"A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm²","authors":"Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2025.3533920","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3533920","url":null,"abstract":"In this letter, GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) are fabricated on Si substrates with an ultra-high breakdown voltage of over 3 kV using a 90-nm in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> layer as both the gate dielectric and surface passivation. The devices exhibit low off-state leakage current (on/off ratio of <inline-formula> <tex-math>$10{^{{9}}}$ </tex-math></inline-formula>), high forward gate breakdown voltage (>122 V), and state-of-the-art figure of merit (685 MW/cm2). Moreover, the reliability of the in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> dielectric is evaluated through the high-temperature gate bias test. The results are fitted with a Weibull distribution, estimating a 10-year estimation of 100 ppm. The maximum gate-source voltage of over 70 V is obtained. This letter presents a strategy for mass producing GaN-on-Si MISHEMTs with high breakdown voltage and reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"106-111"},"PeriodicalIF":2.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10886964","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Trap Analysis of Normally-Off Ga₂O₃ MOSFET Enabled by Charge Trapping Layer: Photon Stimulated Characterization and TDDB

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-07 DOI: 10.1109/JEDS.2025.3538769

Minghao He;Mujun Li;Chenkai Deng;Xiaohui Wang;Qing Wang;Hongyu Yu;Kah-Wee Ang

{"title":"Trap Analysis of Normally-Off Ga₂O₃ MOSFET Enabled by Charge Trapping Layer: Photon Stimulated Characterization and TDDB","authors":"Minghao He;Mujun Li;Chenkai Deng;Xiaohui Wang;Qing Wang;Hongyu Yu;Kah-Wee Ang","doi":"10.1109/JEDS.2025.3538769","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3538769","url":null,"abstract":"A charge trapping layer (CTL) technique is incorporated to achieve a normally-off Ga2O3 MOSFET. The gate dielectric was engineered using a stack composed of a blocking layer (16 nm <inline-formula> <tex-math>${mathrm { HfO}}_{mathrm { x}}$ </tex-math></inline-formula> / 2 nm Al2O3), a CTL (5.76 nm Al:HfO<inline-formula> <tex-math>${_{text {x}}}~1$ </tex-math></inline-formula>:5), and a tunneling barrier (2 nm Al2O3 / 2 nm <inline-formula> <tex-math>${mathrm { HfO}}_{mathrm { x}}$ </tex-math></inline-formula> / 2 nm Al2O3). The trap profile of the CTL layer and the interface of the gate dielectric and Ga2O3 channel are studied by photon-stimulated characterization, which yield highly uniform results, indicating the high quality and uniformity of the proposed method. Furthermore, we conducted a time-dependent dielectric breakdown (TDDB) test on devices both without a field plate (NOFP) and with a source-connected field plate (SFP) to investigate the dielectric failure mechanism and gain valuable insights for the design of CTL-based Ga2O3 MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"112-116"},"PeriodicalIF":2.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877719","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Call for Nominations for Editor-in-Chief

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3536136

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Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528210

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2024 Index IEEE Journal of the Electron Devices Society Vol. 12

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3536577

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Wide Band Gap Semiconductors for Automotive Applications

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528208

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Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528209

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Self-Assembled Multilayer Single-Walled Carbon Nanotube Thin Film Transistors and Doping Regulation

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-22 DOI: 10.1109/JEDS.2025.3532593

Xiangxiang Gao;Zhenhua Lin;Jincheng Zhang;Yue Hao;Jingjing Chang

{"title":"Self-Assembled Multilayer Single-Walled Carbon Nanotube Thin Film Transistors and Doping Regulation","authors":"Xiangxiang Gao;Zhenhua Lin;Jincheng Zhang;Yue Hao;Jingjing Chang","doi":"10.1109/JEDS.2025.3532593","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3532593","url":null,"abstract":"Semiconducting single-walled carbon nanotubes (SWCNTs) have stimulated tremendous research interest in high performance electronics thanks to their impressive mechanical and electronic properties. However, it is still challenging to prepare wafer-scale SWCNTs thin films and fine-tunable device performance. Here, layer-by-layer (LbL) assembly is presented as an effective approach to prepare multilayer SWCNT thin films by coordinating poly(diallyldimethylammonium chloride) (PDDA) with SWCNTs. The thickness of SWCNTs thin film is linearly dependent on the bilayer numbers. Thin film transistors (TFTs) fabricated from SWCNTs thin films showed prominent device performance with a mobility of <inline-formula> <tex-math>$rm 15.3 cm_{2} cdot V_{1}cdot s_{1}$ </tex-math></inline-formula>. Further the molecular dopants bis (trifluoromethane) sulfonimide (TFSI), with strong electro-withdrawing capability and protonating nature, was utilized to functionalize SWCNTs thin films, thereby regulating their electronic performances. The TFSI surface functionalization can remove excess electrons from SWCNT thin films, resulting in improved on-state current, increased carrier mobility and positively shifted threshold voltage. The molecular doping holds great promise for the future realization of large-area, low-power logic circuits and high-performance electronics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"93-97"},"PeriodicalIF":2.0,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10849582","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-20 DOI: 10.1109/JEDS.2025.3531432

Xuexiang Zhang;Qingkun Li;Lei Cao;Qingzhu Zhang;Renjie Jiang;Peng Wang;Jiaxin Yao;Huaxiang Yin

{"title":"Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering","authors":"Xuexiang Zhang;Qingkun Li;Lei Cao;Qingzhu Zhang;Renjie Jiang;Peng Wang;Jiaxin Yao;Huaxiang Yin","doi":"10.1109/JEDS.2025.3531432","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3531432","url":null,"abstract":"As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current (<inline-formula> <tex-math>$rm I_{mathrm {off}}$ </tex-math></inline-formula>) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"86-92"},"PeriodicalIF":2.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10845751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-13 DOI: 10.1109/JEDS.2025.3529079

Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka

{"title":"Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure","authors":"Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka","doi":"10.1109/JEDS.2025.3529079","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3529079","url":null,"abstract":"We examined the fabrication and the operation of GeSn/GeSiSn resonant tunneling diode (RTD) and demonstrated the observation of negative differential resistance (NDR) at a low temperature through the hole resonant tunneling. First, we revealed the possible designed contents of GeSiSn to Si and Sn of 40–60% and ∼10%, respectively to achieve the valence band offset over 0.3 eV with sustaining the biaxial strain value less than 1.0%, which is an important factor for the pseudomorphic growth of GeSn/GeSiSn heterostructure on Ge. Then, we successfully fabricated GeSn/GeSiSn RTD with a double barrier structure composed of ultra-thin GeSiSn barriers and GeSn well, which has the steep heterointerface. The current-density–voltage (J–V) characteristics at 10 K of the fabricated GeSn/GeSiSn RTD showed NDRs at applied voltages of approximately −1.5 and −1.8 V with peak to valley current ratio of 1.06 and 1.14, respectively, and peak current density of ∼3 and ∼5 kA/cm2, respectively. We also demonstrated that the observed NDR is reproducible. The quantum level and J–V simulations suggests that these two NDRs would originate from the hole resonant tunneling current through the first and second quantum levels formed in the GeSn well layer. Furthermore, we also discussed issues newly found in this study and future remarks of GeSn/GeSiSn heterostructures as RTD applications for the terahertz oscillator and the nonvolatile RAM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"79-85"},"PeriodicalIF":2.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839296","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0