IEEE Journal of the Electron Devices Society最新文献_第10页

Accurate Modeling of GaN HEMTs Oriented to Analysis of Kink Effects in S22 and h21: An Effective Machine Learning Approach 面向 S22 和 h21 扭结效应分析的 GaN HEMT 准确建模：一种有效的机器学习方法

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-12 DOI: 10.1109/JEDS.2024.3364809

Zegen Zhu;Gianni Bosi;Antonio Raffo;Giovanni Crupi;Jialin Cai

{"title":"Accurate Modeling of GaN HEMTs Oriented to Analysis of Kink Effects in S22 and h21: An Effective Machine Learning Approach","authors":"Zegen Zhu;Gianni Bosi;Antonio Raffo;Giovanni Crupi;Jialin Cai","doi":"10.1109/JEDS.2024.3364809","DOIUrl":"10.1109/JEDS.2024.3364809","url":null,"abstract":"In this work, for the first time, a machine learning behavioral modeling methodology based on gate recurrent unit (GRU) is developed and used to model and then analyze the kink effects (KEs) in the output reflection coefficient \u0000<inline-formula> <tex-math>$(S_{22})$ </tex-math></inline-formula>\u0000 and the short-circuit current gain \u0000<inline-formula> <tex-math>$(h_{21})$ </tex-math></inline-formula>\u0000 of an advanced microwave transistor. The device under test (DUT) is a 0.25-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC) substrate, which has a large gate periphery of 1.5 mm. The scattering (S-) parameters of the DUT are measured at a frequency up to 65 GHz and at an ambient temperature up to 200°C. The proposed model can accurately reproduce the KEs in \u0000<inline-formula> <tex-math>$S_{22}$ </tex-math></inline-formula>\u0000 and in \u0000<inline-formula> <tex-math>$h_{21}$ </tex-math></inline-formula>\u0000, enabling an effective analysis of their dependence on the operating conditions, bias point and ambient temperature. It is worth noticing that the proposed transistor model shows also good performance in both interpolation and extrapolation test.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10433010","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stability of GaN HEMT Device Under Static and Dynamic Gate Stress GaN HEMT 器件在静态和动态栅极应力下的稳定性

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-05 DOI: 10.1109/JEDS.2024.3362048

Linfei Gao;Ze Zhong;Qiyan Zhang;Xiaohua Li;Xinbo Xiong;Shaojun Chen;Longkou Chen;Huaibao Yan;Anle Zhang;Jiajun Han;Wenrong Zhuang;Feng Qiu;Hsien-Chin Chiu;Shuangwu Huang;Xinke Liu

{"title":"Stability of GaN HEMT Device Under Static and Dynamic Gate Stress","authors":"Linfei Gao;Ze Zhong;Qiyan Zhang;Xiaohua Li;Xinbo Xiong;Shaojun Chen;Longkou Chen;Huaibao Yan;Anle Zhang;Jiajun Han;Wenrong Zhuang;Feng Qiu;Hsien-Chin Chiu;Shuangwu Huang;Xinke Liu","doi":"10.1109/JEDS.2024.3362048","DOIUrl":"10.1109/JEDS.2024.3362048","url":null,"abstract":"In this work, we investigated the stability of a \u0000<inline-formula> <tex-math>${p}$ </tex-math></inline-formula>\u0000-GaN gate with high electron mobility transistors (HEMTs) including an internal integrated gate circuit. A circuit was designed to improve \u0000<inline-formula> <tex-math>${p}$ </tex-math></inline-formula>\u0000-GaN gate stability by using capacitance to release the hole into the \u0000<inline-formula> <tex-math>${p}$ </tex-math></inline-formula>\u0000-GaN layer to mitigate the threshold voltage shift. Through pulse I-V measurement and positive bias temperature instability (PBTI) test, the carrier transporting behavior in the gate region achieved dynamic equilibrium at 5 V gate bias. The positive gate shift \u0000<inline-formula> <tex-math>$(Delta V_{mathrm{ TH}})$ </tex-math></inline-formula>\u0000 of 0.4 V is observed with increasing voltage from 3 V to 8 V; \u0000<inline-formula> <tex-math>$Delta V_{mathrm{ TH}}$ </tex-math></inline-formula>\u0000 initially drops smoothly after release stresses by external capacitance discharge. Finally, integrated passive components and \u0000<inline-formula> <tex-math>${p}$ </tex-math></inline-formula>\u0000-GaN gate HEMT circuit are recommended to mitigate the \u0000<inline-formula> <tex-math>$V_{mathrm{ TH}}$ </tex-math></inline-formula>\u0000 instability for E-mode HEMT.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10422723","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Electrical Property and Thermal Stability in Enhancement-Mode InxAl1–xN/AlN/GaN MOS-HEMTs Fabricated by Using NiOx Gate and Fluorine Treatment 利用氧化镍栅极和氟处理技术制作的增强型 InxAl1-xN/AlN/GaN MOS-HEMT 的电气特性和热稳定性研究

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-02-05 DOI: 10.1109/JEDS.2024.3360244

Jian Qin;Jingxiong Chen;Wenxuan Xiao;Hong Wang

{"title":"Investigation of Electrical Property and Thermal Stability in Enhancement-Mode InxAl1–xN/AlN/GaN MOS-HEMTs Fabricated by Using NiOx Gate and Fluorine Treatment","authors":"Jian Qin;Jingxiong Chen;Wenxuan Xiao;Hong Wang","doi":"10.1109/JEDS.2024.3360244","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3360244","url":null,"abstract":"In this study, we report a novel approach for achieving high-performance enhancement mode (E-mode) InAlN/GaN MOS HEMTs based on the fluorine treatment and a p-type NiOx gate (F-NiO HEMT). The NiO film was deposited at different substrate temperatures using reactive sputtering in a varied mixture of O2 and Ar. We show that the threshold voltage \u0000<inline-formula> <tex-math>$({V}_{TH}$ </tex-math></inline-formula>\u0000) is effectively modulated by comprehensively optimizing fluorine ion implantation and NiO sputtering conditions without requiring gate recess etching. The influence of different NiO deposition conditions on electrical properties and the critical interface of NiOx/InAlN have been investigated in detail. The proposed E-mode F-NiO HEMT exhibits superior on-state characteristics, including more positive \u0000<inline-formula> <tex-math>${V}_{TH}$ </tex-math></inline-formula>\u0000, enhanced gate voltage swing, larger transconductance \u0000<inline-formula> <tex-math>${g}_{m}$ </tex-math></inline-formula>\u0000 and also superior gate control over the channel. The dual C-V and pulsed mode measurements confirm the excellent NiOx/AlInN interface and effective suppression of current collapse. We propose a model to explain the contrasting temperature-dependent coefficients of \u0000<inline-formula> <tex-math>${V}_{TH}$ </tex-math></inline-formula>\u0000 shifts observed in pure fluorine ion-implanted and NiO-based devices. The underlying mechanisms at elevated temperatures are also analyzed.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10421783","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139739008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Improved Method for InP HEMT Noise-Parameter Determination Based on 50-Ω Noise Measurements 基于 50-Ω 噪声测量的 InP HEMT 噪声参数确定改进方法

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-31 DOI: 10.1109/JEDS.2024.3360461

Yuanting Lyu;Zhichun Li;Ao Zhang;Jianjun Gao

引用次数: 0

Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations 使用所有 "室温 "离子注入法制造的 1.2kV 4H-SiC MOSFET 静态性能调查

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-30 DOI: 10.1109/JEDS.2024.3359974

Stephen A. Mancini;Seung Yup Jang;Zeyu Chen;Dongyoung Kim;Alex Bialy;Balaji Raghotamacher;Michael Dudley;Nadeemullah Mahadik;Robert Stahlbush;Mowafak Al-Jassim;Woongje Sung

引用次数: 0

A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design 用于低温 CMOS 设计的基于物理电荷的阈值电压分析模型

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-29 DOI: 10.1109/jeds.2024.3359664

Hao Su, Yiyuan Cai, Shenghua Zhou, Guangchong Hu, Yu He, Yunfeng Xie, Yuhuan Lin, Chunhui Li, Tianqi Zhao, Jun Lan, Wenhui Wang, Wenxin Li, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, Kai Chen

引用次数: 0

Investigation of Photosensitive Polyimide With Low Coefficient of Thermal Expansion and Excellent Adhesion Strength for Advanced Packaging Applications 研究用于先进封装应用的热膨胀系数低、粘合强度高的光敏聚酰亚胺

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-26 DOI: 10.1109/JEDS.2024.3358830

Yuan-Chiu Huang;Han-Wen Hu;Yun-Hsi Liu;Hui-Ching Hsieh;Kuan-Neng Chen

引用次数: 0

Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes 单光子雪崩二极管的晶圆级表征和监控平台

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-26 DOI: 10.1109/JEDS.2024.3359088

Samuel Parent;Frédéric Vachon;Valérie Gauthier;Steve Lamoureux;Alexandre Paquette;Jacob Deschamps;Tommy Rossignol;Nicolas Roy;Philippe Arsenault;Henri Dautet;Serge A. Charlebois;Jean-François Pratte

{"title":"Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes","authors":"Samuel Parent;Frédéric Vachon;Valérie Gauthier;Steve Lamoureux;Alexandre Paquette;Jacob Deschamps;Tommy Rossignol;Nicolas Roy;Philippe Arsenault;Henri Dautet;Serge A. Charlebois;Jean-François Pratte","doi":"10.1109/JEDS.2024.3359088","DOIUrl":"10.1109/JEDS.2024.3359088","url":null,"abstract":"When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10414786","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Balanced Performance Merit On Wind and Solar Energy Contact With Clean Environment Enrichment 风能和太阳能与清洁环境的平衡功绩

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-24 DOI: 10.1109/jeds.2024.3358087

Dr. Priyan Malarvizhi Kumar, Dr. M. M. Kamruzzaman, Badria Sulaiman Alfurhood, Bakri Hossain, Harikumar Nagarajan, Surendar Rama Sitaraman

引用次数: 0

Design and Thermal Analysis of 2.5D and 3-D Integrated System of a CMOS Image Sensor and a Sparsity-Aware Accelerator for Autonomous Driving 用于自动驾驶的 CMOS 图像传感器和稀疏感知加速器的 2.5D 和 3D 集成系统的设计与热分析

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-01-17 DOI: 10.1109/JEDS.2024.3354621

Janak Sharda;Madison Manley;Ankit Kaul;Wantong Li;Muhannad Bakir;Shimeng Yu

{"title":"Design and Thermal Analysis of 2.5D and 3-D Integrated System of a CMOS Image Sensor and a Sparsity-Aware Accelerator for Autonomous Driving","authors":"Janak Sharda;Madison Manley;Ankit Kaul;Wantong Li;Muhannad Bakir;Shimeng Yu","doi":"10.1109/JEDS.2024.3354621","DOIUrl":"10.1109/JEDS.2024.3354621","url":null,"abstract":"For the autonomous driving application, data movement has increased rapidly between a CMOS Image sensor (CIS) and the processor due to increase in image resolution. Advanced packaging techniques like 2.5D/3D integration have been proposed to reduce the data movement energy between memory and processor. In this work, we explore the use of such techniques to integrate a CIS and a backend accelerator on a silicon interposer. The data movement energy from CIS to the accelerator is thus reduced by \u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000 compared to using the conventional MIPI links. We perform thermal simulations to study the impact of the thermal coupling of CIS and accelerator and ensure a peak temperature increase of less than \u0000<inline-formula> <tex-math>$5~^{circ }$ </tex-math></inline-formula>\u0000C. We also vary the distance between the CIS and the processor to study the trade-offs between energy savings and peak temperature. Next, we assume the 3D stacked CIS and accelerator to reduce the data movement further and obtain an energy efficiency of 45.81 TOPS/W. Now we observe a heat dissipation challenge with an increase in the peak temperature of more than \u0000<inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>\u0000C. Hence, we scale down the operational frequency and study the trade-off between performance degradation and reduction in peak temperature, while maintaining the accurate multi-object tracking on the BDD100k dataset for autonomous driving.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10403647","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139952886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0