Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed

Abstract

A novel Asymmetrical FET (AsyFET) is proposed to enhance the retention of gain cell memory and is experimentally demonstrated based on standard 300mm logic foundry platform. In AsyFET, the asymmetrical S/D doping and S/D gate spacer are designed to suppress leakage current. The modulated Schottky direct tunneling current and band-to-band tunneling current are designed to write “1” and “0” respectively without write disturb. The AsyFET-based 2T0C DRAM with significantly enhanced retention and fast access speed is also proposed and experimentally demonstrated on the same wafer. Without area penalty or new materials, the fabricated Si AsyFET can obtain ultralow off-state current of $\sim 10{^{-}17 }$ A/ $\mu $ m, leading to the long retention above second-level in 55nm technology node across the 300mm wafer. The on-state currents of AsyFET at forward and reverse bias are $\sim 10{^{-}6 }$ A/ $\mu $ m, enabling write speed of below 5ns with negligible temperature dependence. The experimental results show the great potential of proposed AsyFET 2T0C DRAM design for low-power, high-density, and high-speed on-chip memory.