Trap Analysis of Normally-Off Ga₂O₃ MOSFET Enabled by Charge Trapping Layer: Photon Stimulated Characterization and TDDB

Abstract

A charge trapping layer (CTL) technique is incorporated to achieve a normally-off Ga2O3 MOSFET. The gate dielectric was engineered using a stack composed of a blocking layer (16 nm ${\mathrm { HfO}}_{\mathrm { x}}$ / 2 nm Al2O3), a CTL (5.76 nm Al:HfO ${_{\text {x}}}~1$ :5), and a tunneling barrier (2 nm Al2O3 / 2 nm ${\mathrm { HfO}}_{\mathrm { x}}$ / 2 nm Al2O3). The trap profile of the CTL layer and the interface of the gate dielectric and Ga2O3 channel are studied by photon-stimulated characterization, which yield highly uniform results, indicating the high quality and uniformity of the proposed method. Furthermore, we conducted a time-dependent dielectric breakdown (TDDB) test on devices both without a field plate (NOFP) and with a source-connected field plate (SFP) to investigate the dielectric failure mechanism and gain valuable insights for the design of CTL-based Ga2O3 MOSFETs.