IEEE Journal of the Electron Devices Society最新文献_第2页

Simulation Study on the Scalability of Channel-All-Around Reconfigurable Field-Effect Transistors With Gate-Controlled Polarity 栅极控制通道可重构场效应晶体管的可扩展性仿真研究

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-28 DOI: 10.1109/JEDS.2026.3659128

Ran Huo;Shijun Ou;Zhehao Wu;Han Zhang;Bowen Lv;Yvyang Shao;Zichao Ma;Min Zhang;Mansun Chan;Changjian Zhou

{"title":"Simulation Study on the Scalability of Channel-All-Around Reconfigurable Field-Effect Transistors With Gate-Controlled Polarity","authors":"Ran Huo;Shijun Ou;Zhehao Wu;Han Zhang;Bowen Lv;Yvyang Shao;Zichao Ma;Min Zhang;Mansun Chan;Changjian Zhou","doi":"10.1109/JEDS.2026.3659128","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3659128","url":null,"abstract":"Conventional complementary metal oxide semiconductor (CMOS) devices rely heavily on doping, which increasingly limits scalability due to process constraints and performance degradations at advanced technology nodes. To overcome the drawbacks associated with doping, reconfigurable field-effect transistors (RFETs) that employ ferroelectric gate dielectrics with non-volatile programmability have emerged as a promising alternative for gate-controlled polarity modulation. Nevertheless, most reported RFETs adopt planar device geometries, raising concerns regarding their scalability at deeply scaled nodes. This work proposes a channel-all-around (CAA) RFETs architecture featuring gate-tunable polarity, based on an undoped <inline-formula> <tex-math>${mathrm { WSe}}_{2}$ </tex-math></inline-formula> channel and an AlScN gate dielectric. Using calibrated TCAD simulations, we show that vertically stackable CAA structures, combined with intrinsically ambipolar WSe2, have significantly enhanced the scalability of RFETs for logic applications down to N0.5 technology node. Furthermore, the extracted device characteristics are implemented in a Verilog-A model for circuit-level simulations. The CAA-RFET-based complementary inverters exhibit robust noise margins, high voltage gains, and stable operation voltages at supply voltages down to 0.2 V. The reconfigurable CMOS logic gates with topologies identical to conventional CMOS designs, confirm the extreme scalability, and circuit-level viability of 2D CAA-RFETs for ultra-compact and energy-efficient programmable logic.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"93-101"},"PeriodicalIF":2.4,"publicationDate":"2026-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11367430","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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2025 Index IEEE Journal of the Electron Devices Society Vol. 13 电子器件学会杂志第13卷

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IEEE Journal of the Electron Devices Society Pub Date : 2026-01-28 DOI: 10.1109/JEDS.2026.3659206

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Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory 3-D NAND闪存中优化虚拟字线电压实现的低功耗堆栈级编程

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-28 DOI: 10.1109/JEDS.2026.3659350

Kyungmin Lee;Gunwook Yoon;Seung Jae Baik;Myounggon Kang

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Microchannel Cooling for Performance Enhancement of GaN-on-Si HEMT With a Low Rj-a of 13.5 K/W 微通道冷却提高GaN-on-Si HEMT的性能，低r -a为13.5 K/W

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-28 DOI: 10.1109/JEDS.2026.3658238

Jiajun Zhou;Xin Feng;Weihang Zhang;Kui Dang;Yachao Zhang;Zeyang Ren;Yanjing He;Xianhe Liu;Hong Zhou;Zhihong Liu;Yue Hao;Jincheng Zhang

{"title":"Microchannel Cooling for Performance Enhancement of GaN-on-Si HEMT With a Low Rj-a of 13.5 K/W","authors":"Jiajun Zhou;Xin Feng;Weihang Zhang;Kui Dang;Yachao Zhang;Zeyang Ren;Yanjing He;Xianhe Liu;Hong Zhou;Zhihong Liu;Yue Hao;Jincheng Zhang","doi":"10.1109/JEDS.2026.3658238","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3658238","url":null,"abstract":"Gallium nitride (GaN) is a high-performance wide bandgap semiconductor material with unique physical and chemical properties such as higher breakdown electric field, higher electron density, superior electron mobility and saturation velocity. These properties endow GaN with unparalleled advantages in high-frequency and high-power applications. However, a primary challenge faced by the industrialized GaN HEMT is thermal management, particularly in handling higher power densities, which leads to a serious degradation in electrical performance and long-term reliability. In this study, electrothermal analysis for GaN HEMT is conducted based on two thermal resistance models for natural air cooling and microchannel cooling, proving a minimum 40% reduction in Rj-a using microchannel cooling and an optimal coolant flow rate to guide the actual experiment. Furthermore, the experimental result shows that microchannel cooling technology significantly enhances the thermal convection capacity, resulting in a 35.2% increase in the saturation current. Moreover, the Rj-a can be reduced to 13.5 K/W with 65% improvement at a cooling flow rate of 460 mL/min, and the surface heat flux density reaches 2200 W/cm2, which is 106% higher than that of natural air cooling.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"85-92"},"PeriodicalIF":2.4,"publicationDate":"2026-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11364121","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146176024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Guest Editorial Special Issue on 22nd International Workshop on Junction Technologies 第22届连接技术国际研讨会特刊

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IEEE Journal of the Electron Devices Society Pub Date : 2026-01-22 DOI: 10.1109/JEDS.2025.3650320

Tetsuo Narita

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Golden List of Reviewers for 2025 2025年评审金名单

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IEEE Journal of the Electron Devices Society Pub Date : 2026-01-21 DOI: 10.1109/JEDS.2026.3651876

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Monolithic Comparators on a Novel Platform of GaN-Based D/E-Mode HEMTs by LPCVD SiNx Passivation Compatible to Gate Dielectrics 与栅极介质兼容的LPCVD SiNx钝化gan基D/ e模hemt新平台上的单片比较器

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-19 DOI: 10.1109/JEDS.2026.3655330

Xinyu Sun;Hongwei Gao;Fangqing Li;Haoran Qie;Xin Chen;Haodong Wang;Yaozong Zhong;Xiaolu Guo;Xinchen Ge;Zhihong Feng;Qian Sun;Hui Yang

{"title":"Monolithic Comparators on a Novel Platform of GaN-Based D/E-Mode HEMTs by LPCVD SiNx Passivation Compatible to Gate Dielectrics","authors":"Xinyu Sun;Hongwei Gao;Fangqing Li;Haoran Qie;Xin Chen;Haodong Wang;Yaozong Zhong;Xiaolu Guo;Xinchen Ge;Zhihong Feng;Qian Sun;Hui Yang","doi":"10.1109/JEDS.2026.3655330","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3655330","url":null,"abstract":"This paper demonstrates an integrated comparator based on a novel platform of GaN-based high electron mobility transistors (HEMTs) with low pressure chemical vapor deposition (LPCVD) SiNx as both gate dielectric and passivation layer. Solving the compatibility issue in device fabrication, both high-performance D-mode and E-mode GaN HEMTs have been realized and then loaded for circuits simulation. With careful determination of each device’s performance, the designed comparator has been constructed, and its comparison range goes from 1 to 3.5 V at VDD <inline-formula> <tex-math>${=}5$ </tex-math></inline-formula> V. Moreover, the comparator achieved a rise time of 754 ns at a driving frequency of 100 kHz, and maintained stable operation even at a high temperature of <inline-formula> <tex-math>$200~{^{text {o}}}$ </tex-math></inline-formula>C. The comparator based on the new platform of p-GaN gated HEMTs with LPCVD SiNx passivation provides a new solution for GaN-based power ICs and holds great potential in wide applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"79-84"},"PeriodicalIF":2.4,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11357512","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Repetitive Gate-HBM-ESD-Induced Vth Degradation for RF GaN HEMT With Matching Networks 具有匹配网络的射频GaN HEMT的重复栅极- hbm - esd诱导的Vth衰减

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-15 DOI: 10.1109/JEDS.2026.3654157

Ran Ye;Hao Luo;Suyuan Wang;Zhiqiang Hu;Jiaojing Bian;Qiao Kang;Sheng Li;Siyang Liu;Weifeng Sun

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Investigation of PBTS-Induced Degradation Mechanisms in SA TG Coplanar IGZO TFTs Using Low-Frequency Noise Analysis 基于低频噪声分析的pbts诱导SA - TG共面IGZO tft降解机制研究

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-13 DOI: 10.1109/JEDS.2026.3653818

Hyeon-Woo Lee;Su-Hyeon Lee;Dong-Ho Lee;Chae-Eun Oh;Dong-Hwi Son;Chang-Hyeon Kim;Chan-Yong Jeong;Jaeman Jang;Byung-Du Ahn;Jong-Uk Bae;Sang-Hun Song;Hyuck-In Kwon

{"title":"Investigation of PBTS-Induced Degradation Mechanisms in SA TG Coplanar IGZO TFTs Using Low-Frequency Noise Analysis","authors":"Hyeon-Woo Lee;Su-Hyeon Lee;Dong-Ho Lee;Chae-Eun Oh;Dong-Hwi Son;Chang-Hyeon Kim;Chan-Yong Jeong;Jaeman Jang;Byung-Du Ahn;Jong-Uk Bae;Sang-Hun Song;Hyuck-In Kwon","doi":"10.1109/JEDS.2026.3653818","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653818","url":null,"abstract":"This study investigates the degradation mechanism of self-aligned top-gate (SA TG) coplanar IGZO thin-film transistors (TFTs) under positive bias temperature stress (PBTS) using low-frequency noise (LFN) analysis. Electrical measurements revealed a positive shift in threshold voltage, increased subthreshold swing, decreased field-effect mobility, and enhanced hysteresis after PBTS. The enhanced unified LFN model, accounting for both channel trap states and gate dielectric traps, successfully explained the observed noise characteristics of fabricated SA TG coplanar IGZO TFTs before and after PBTS. From the extracted trap parameters from LFN analysis, an increase in near-interface trap density and subgap density of states near the conduction band edge was confirmed after PBTS, correlating well with the observed electrical degradation. These results demonstrate that LFN analysis based on the enhanced unified LFN model is an effective diagnostic tool for examining the electrical stress-induced degradation in IGZO TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"36-40"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347528","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Enhancing Ultraviolet Responsivity of GaN p-i-n Photodetectors Through Full Depletion Thin-Layer Doping-Induced Carrier Transport Modulation 通过全耗尽薄层掺杂诱导载流子传输调制增强GaN p-i-n光电探测器的紫外响应性

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-13 DOI: 10.1109/JEDS.2026.3653860

Shishun Yang;Yaxuan Liu;Huiyi Zhang;Hanlin Li;Jun Wang

{"title":"Enhancing Ultraviolet Responsivity of GaN p-i-n Photodetectors Through Full Depletion Thin-Layer Doping-Induced Carrier Transport Modulation","authors":"Shishun Yang;Yaxuan Liu;Huiyi Zhang;Hanlin Li;Jun Wang","doi":"10.1109/JEDS.2026.3653860","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653860","url":null,"abstract":"High-performance GaN-based ultraviolet (UV) photodetectors (PDs) are essential for applications in harsh-environment sensing, space-based UV monitoring, and high-speed optical communications. However, conventional GaN-based p-i-n homojunction UV photodetectors face limitations in responsivity due to significant UV absorption in the p-GaN layer. To address this issue, we propose a novel full depletion (FD) thin-layer structure incorporating a strategically placed 1-nm n-type interlayer at the p–i interface with optimized doping to enhance carrier separation and collection. Results reveal a 27.3% increase in peak responsivity, reaching 0.163 A/W at 360 nm, compared to 0.128 A/W in conventional devices. In addition, the new-structured photodetector exhibits a specific detectivity (D*) of <inline-formula> <tex-math>$2.88times 10{^{{13}}}$ </tex-math></inline-formula> Jones, and a low response time of approximately 37 ns. The results of experiments and simulations are highly consistent, verifying the accuracy of the proposed model. Notably, the proposed design maintains excellent electrical performance, with dark current levels comparable to those of traditional architectures, thereby ensuring device stability. The FD-thin doped layer strategy offers a straightforward yet effective route to significantly improve the responsivity of GaN-based UV photodetectors without introducing fabrication complexity or the need for heterojunction integration. This architecture presents a promising pathway toward high-efficiency UV photodetection systems for next-generation applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"49-57"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347526","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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