IEEE Journal of the Electron Devices Society最新文献_第2页

Advanced Microfluidic Biofuel Cells Using Gold and Silver Leaf on Paper and PDMS Substrates: Toward Implantable Energy Solution

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-04 DOI: 10.1109/JEDS.2025.3547869

S. Vanmathi;Sanket Goel

{"title":"Advanced Microfluidic Biofuel Cells Using Gold and Silver Leaf on Paper and PDMS Substrates: Toward Implantable Energy Solution","authors":"S. Vanmathi;Sanket Goel","doi":"10.1109/JEDS.2025.3547869","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547869","url":null,"abstract":"An exploration of new and simplified electrode materials such as gold leaf (GL), and silver leaf (SL) based approaches to enhance the efficiency and scalability of microfluidic biofuel cell renewable energy sources has generated significant interest. Our research aims to utilize the unique properties of these materials to create advanced biofuel cells, with a specific focus on implantable devices. By employing nanoporous gold and patterned silver leaf, are designing flexible, efficient, and scalable biofuel cells that have the potential to revolutionize energy solutions in medical and wearable technologies. Microfluidic biofuel cells with nanostructured gold and silver leaf devices harvest ultra-low power energy, making them more practical for real-world applications. The gold and silver leaf enzymatic biofuel cell (LEBFC) operates using glucose as fuel, with glucose oxidase functioning at the anode and laccase at the cathode, both coating the GL and SL bioelectrodes. These leaf microfluidic devices, fabricated using polydimethylsiloxane (PDMS) and filter paper, demonstrated a peak open circuit voltage of 197 mV and 448 mV, along with a maximum power density of <inline-formula> <tex-math>$28.7 mu mathrm{~W} / mathrm{cm}^2$ </tex-math></inline-formula> and <inline-formula> <tex-math>$93.6 mu mathrm{~W} / mathrm{cm}^2$ </tex-math></inline-formula>, respectively. Such flexible devices are lightweight, non-toxic, edible, and biodegradable, designed for optimal load connection to ensure stable performance while reducing weight. Please replace with this sentence. It opens new opportunities for sustainable power generation and offers promising applications in wearable, implantable, and portable microelectronic devices, where reliable, low-power energy sources are inexpensive.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"173-181"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909661","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Stability of Gate Driver Circuits Based on 4H-SiC MOSFETs at 300°C for High-Power Applications

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-03 DOI: 10.1109/JEDS.2025.3546959

Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki

{"title":"Thermal Stability of Gate Driver Circuits Based on 4H-SiC MOSFETs at 300°C for High-Power Applications","authors":"Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki","doi":"10.1109/JEDS.2025.3546959","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3546959","url":null,"abstract":"The operation and reliability of gate driver circuits based on 4H-SiC MOSFETs at temperatures up to 300°C were reported. Due to the advantages of 4H-SiC MOSFETs, the driver circuit can overcome limitations in complicated circuit design and power dissipation associated with SiC BJTbased technology. Additionally, the stability of implanted 4H-SiC resistors can address the reliability issues of SiC CMOS-based driver circuits, which are caused by the instability in the threshold voltage of P-channel SiC MOSFETs. In this study, the switching characteristics of the gate driver circuit were improved when the ambient temperature increased. The decrease of threshold voltage and increase of carrier mobility of the 4H-SiC MOSFETs may account for the improvement in switching characteristics of the gate driver circuit. The output signal of the gate driver circuit still showed proper characteristics after 600 min of continuous operation at 300°C in an air ambient. These results indicate that the gate driver circuit based on 4H-SiC MOSFET technology is promising to apply for high power applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"161-167"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10908627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Analysis of Rare-Earth Doped Oxide Thin-Film Transistors Using Neural Network Method

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-03 DOI: 10.1109/JEDS.2025.3547646

Zengyi Peng;Xianglan Huang;Yuanyi Shen;Weijing Wu;Min Li;Miao Xu;Lei Wang;Zhenghui Gu;Zhuliang Yu;Junbiao Peng

{"title":"Performance Analysis of Rare-Earth Doped Oxide Thin-Film Transistors Using Neural Network Method","authors":"Zengyi Peng;Xianglan Huang;Yuanyi Shen;Weijing Wu;Min Li;Miao Xu;Lei Wang;Zhenghui Gu;Zhuliang Yu;Junbiao Peng","doi":"10.1109/JEDS.2025.3547646","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547646","url":null,"abstract":"The work analyzes the key impact factors on the performances of rare-earth element doped oxide thin-film transistors (TFTs), which are potentially used for high performance displays, by comparatively using a Bayesian Neural Network (BNN) method and Artificial Neural Network (ANN) method based on published and self-experimental data which was exhaustively collected. Both BNN and ANN methods can effectively identify the primary impact factors among rare-earth element type, doping concentration, thin film thickness, channel length and width, which are key factors to determine the TFTs performances. Comparisons between the BNN and ANN methods, the BNN approach offers more reliable and robust predictions on the dataset. Accordingly, the efficient neural network models tailored to the data features were accurately established. A key outcome from the BNN models is the relative importance ranking of the influence factors and relationship between the carrier mobility and element type, concentration as well. To the TFT mobility, rare-earth element concentration is the most critical factor, suggesting lower concentration exhibited higher mobility, followed by the rare-earth element type. To the sub-threshold swing performance of TFTs, the rare-earth element type is the most significant influence factor, suggesting higher valence rare-earth is superior to lower valence one, followed by the element concentration. The results are basically consistent with experimental tendency. These insights could effectively guide the design of oxide semiconductor materials and TFT device structure, to achieve high-performance (high mobility and high stability) oxide TFT devices for displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"263-269"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909085","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-27 DOI: 10.1109/JEDS.2025.3546314

Sandeep Semwal;Pin Su

引用次数: 0

Nanomole Process: Enabling Localized Metallic Back-Gates for Enhanced Cryogenic Front-to-Back Coupling in FDSOI Quantum Dots

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-25 DOI: 10.1109/JEDS.2025.3545661

Fabio Bersano;Niccolò Martinolli;Ilan Bouquet;Michele Ghini;Eloi Collette;Liza Žaper;Floris Braakman;Martino Poggio;Mathieu Luisier;Adrian Mihai Ionescu

{"title":"Nanomole Process: Enabling Localized Metallic Back-Gates for Enhanced Cryogenic Front-to-Back Coupling in FDSOI Quantum Dots","authors":"Fabio Bersano;Niccolò Martinolli;Ilan Bouquet;Michele Ghini;Eloi Collette;Liza Žaper;Floris Braakman;Martino Poggio;Mathieu Luisier;Adrian Mihai Ionescu","doi":"10.1109/JEDS.2025.3545661","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3545661","url":null,"abstract":"This paper introduces a novel integration method of localized metallic back-gates into fully-depleted silicon-on-insulator (FDSOI) multi-gate FETs, enabling robust front-to-back electrostatic coupling from room temperature to cryogenic conditions, without the need for substrate implantation. The fabrication process, termed the Nanomole process, utilizes nanometric vapor-phase etching of the buried oxide or silicon substrate with vapor-HF and XeF2 gases. This is followed by atomic layer deposition (ALD) of a dielectric material and Pt, with precise patterning achieved through inductively coupled plasma etching. Detailed analysis of the process demonstrates controllable etch rates based on device geometry, providing calibrated guidelines for scalable manufacturing. Symmetric mid-k dual-gating is reported in devices featuring a Si-film thickness of 24 nm, with a top and bottom gate oxide equivalent thickness (EOT) of 6.5 nm. Electrical characterization of multi-gate FDSOI SETs, operated as FETs, confirms effective threshold voltage tuning through dual-gate operation, with consistent performance from room temperature to millikelvin regimes. Additionally, quantum mechanical simulations based on the effective mass approximation at 4 K offer insights into the electrostatic behavior of dual-gated SOI quantum dot devices in both planar and nanowire geometries. This scalable and versatile technological solution opens new possibilities for advanced quantum devices, such as charge and spin qubits, by enabling in situ control over volume inversion, electron valley splitting, and spin-orbit interaction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"210-218"},"PeriodicalIF":2.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10902357","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Power a-IGZO TFT Emission Driver With Shoot-Through Current-Free QB Control Block

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-24 DOI: 10.1109/JEDS.2025.3544840

Won-Been Jeong;Sang-Hoon Kim;Seung-Woo Lee

引用次数: 0

Characterization and Modeling of MOSFET Series Resistance Down to 4 K

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-21 DOI: 10.1109/JEDS.2025.3544738

Yuhuan Lin;Zhizhao Ma;Shilong Li;Tianyue Wen;Yuxuan Zhou;Hao Su;Shenghua Zhou;Longyang Lin;Yida Li;Kai Chen

引用次数: 0

Design of an Integrated MEMS Magnetic Gradiometer Rejecting Vibrations and Stray Fields

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-19 DOI: 10.1109/JEDS.2025.3543662

Enrico Gasparin;Arno Hoogerwerf;Dara Bayat;Guido Spinola Durante;Yves Petremand;Maurizio Tormen;Michel Despont;Gaël Close

{"title":"Design of an Integrated MEMS Magnetic Gradiometer Rejecting Vibrations and Stray Fields","authors":"Enrico Gasparin;Arno Hoogerwerf;Dara Bayat;Guido Spinola Durante;Yves Petremand;Maurizio Tormen;Michel Despont;Gaël Close","doi":"10.1109/JEDS.2025.3543662","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543662","url":null,"abstract":"Magnetic sensors are often used near current-carrying wires or electrical motors generating significant magnetic interference. To mitigate the effects of these stray fields, the traditional design approach relies on a differential sensing scheme: multiple magnetometers are spaced apart, and the field differences are measured. Despite being rejected, stray fields still constrain the design space. Extra linear range and matched channels are required to accommodate their peak amplitude without saturation or residual common-mode leakage. On the contrary, single-point MEMS gradiometers rely on the force acting on a magnet, which is directly proportional to the magnetic field gradient. The stray field is intrinsically rejected by the magnetic transducing mechanism, even before entering the measurement chain. The range of the measurement chain can then be largely optimized for the gradient, independently of the stray field amplitude. This paper discusses the design of a single-point MEMS gradiometer. By design, it rejects magnetic stray fields and mechanical disturbances like vibrations and gravity. It is the first single-point MEMS gradiometer capable of operating unshielded and in various orientations. The prototype achieves a noise density of 4 nT/mm/<inline-formula> <tex-math>$sqrt {mathrm { Hz}}$ </tex-math></inline-formula> within a measurement range of <inline-formula> <tex-math>${pm } 300~{mu }$ </tex-math></inline-formula>T/mm. The paper demonstrates the sensor’s effectiveness in a bus-bar current sensing application. Design limitations and future design prospects are also outlined.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"228-236"},"PeriodicalIF":2.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892099","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-18 DOI: 10.1109/JEDS.2025.3542951

Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li

{"title":"A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays","authors":"Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li","doi":"10.1109/JEDS.2025.3542951","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542951","url":null,"abstract":"A highly robust integrated gate driver based on organic thin-film transistors (OTFTs) is proposed that effectively addresses the output degradation caused by depletion-mode operation, instability and variation. The series-connected two-transistor structures and the inverters generate positive gateto- source voltages for internal nodes, which eliminate the leakage current and voltage ripples in depletion-mode operation and extend the support threshold voltage (<inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula>) range. The simulation waveforms of the 538th stage have no degradation, considering the <inline-formula> <tex-math>$Delta V_{TH}$ </tex-math></inline-formula> range from 1.18 to -0.53 V for single-gate (SG) OTFT and that from 2.13 to -8.07 V for dual-gate (DG) OTFT. The fabricated gate drivers generate stable scan signals with almost negligible voltage ripples for SG- and DG-OTFT with <inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula> of +7.9 and +1.8 V, respectively. In a 5.8-inch AMOLED panel (resolution: 538×302), the circuit can operate at a frame rate range from 1 to 45 Hz, driven by clocks with a frequency of 12.5 kHz and a swing from 0 to -15 V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"128-133"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891473","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Self-Aligned Staggered Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors With Ultra-Low Contact Resistance for High-Speed Circuits Application

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-18 DOI: 10.1109/JEDS.2025.3543212

Chuanke Chen;Xinlv Duan;Congyan Lu;Xichen Chuai;Wanming Wu;Chunyu Zhang;Chen Gu;Guanhua Yang;Nianduan Lu;Di Geng;Ling Li

引用次数: 0