基于VTH补偿技术的多比特IGZO 2T0C DRAM

IF 2 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu
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引用次数: 0

摘要

在这项工作中,我们提出并实验证明了用于阵列级多比特存储的新型双栅(DG)铟镓锌氧化物(IGZO)双晶体管零电容(2T0C)动态随机存取存储器(DRAM)。与传统的2T0C DRAM不同,新型DG位单元的数据写入策略是从存储节点(SN)到位线的放电过程,在不牺牲位单元布局的情况下实现单元内阈值电压(VTH)补偿。从读晶体管顶栅极产生的VTH调制使$\Delta $ VSN显著增强,其创纪录的比率($\Delta $ VSN/ $\Delta $ VDATA)为1.46,从而提高了多比特存储的空间。此外,优化后的晶体管具有正VTH和高导通电流,可实现长保持时间(>1500 s)和超快写入速度(< 10 ns)。在VTH补偿和$\Delta $ VSN增强的协同作用下,实现了25个单元间的无重叠3位存储操作,标准差降低了一阶。本研究为实现IGZO 2T0C DRAM在大规模阵列中的多比特存储应用奠定了关键基础。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications
In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable $\Delta $ VSN boosting, with a record-high ratio ( $\Delta $ VSN/ $\Delta $ VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and $\Delta $ VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.
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来源期刊
IEEE Journal of the Electron Devices Society
IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology
CiteScore
5.20
自引率
4.30%
发文量
124
审稿时长
9 weeks
期刊介绍: The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.
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