IEEE Journal of the Electron Devices Society最新文献_第3页

Enhancement of the Transient Current Behavior of MIS Tunnel Diodes With Ultra-Edge-Thickened (UET) Oxide under the Consideration of Tunnel Oxide Areas 考虑隧道氧化区的情况下，超边缘增厚（UET）氧化物增强MIS隧道二极管瞬态电流行为

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-14 DOI: 10.1109/JEDS.2025.3588814

Jun-Yi Lin;Sung-Wei Huang;Jenn-Gwo Hwu

{"title":"Enhancement of the Transient Current Behavior of MIS Tunnel Diodes With Ultra-Edge-Thickened (UET) Oxide under the Consideration of Tunnel Oxide Areas","authors":"Jun-Yi Lin;Sung-Wei Huang;Jenn-Gwo Hwu","doi":"10.1109/JEDS.2025.3588814","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588814","url":null,"abstract":"In this research, the steady-state and transient behavior of the p-type metal-insulator-semiconductor (MIS) tunnel-diodes (TD) with ultra-edge-thickened (UET) oxide was studied, utilizing experimental results and TCAD simulations. The investigation explores how the gate voltage (VG) influences the gate current (IG). Additionally, the impact of the thin oxide area under the gate (Athin) on IG is examined. When VG < VFB, which is in forward bias, IG is directly proportional to Athin, resulting in a larger |IG| for the planar devices with only thin oxide. Conversely, for V<inline-formula> <tex-math>${}_{text {G}} gt $ </tex-math></inline-formula> 0 V, the UET devices exhibit a higher IG compared to the planar device due to more electrons supplied from the region outside the gate. The UET device, compared to the planar device, shows an enhancement of over one hundred times larger magnitude of transient current. Also, the UET devices featuring the larger Athin display a greater magnitude of transient current. However, the enhancement of transient current becomes saturated when the portions of thin and thick oxide are almost equal in area. The magnitudes of the transient currents of the UET devices are sampled at 60 ms after switching VG from write to 0 V. Endurance characteristic is also measured, revealing minimal changes after 1000 write and read cycles. To elucidate the mechanism behind the steady-state and transient current behavior, simulations are employed for both the steady-state and transient situations.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"607-614"},"PeriodicalIF":2.4,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11079924","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A p-GaN HEMT Voltage Reference With High Line Sensitivity and Power Supply Rejection Ratio 具有高线路灵敏度和电源抑制比的p-GaN HEMT基准电压

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-11 DOI: 10.1109/JEDS.2025.3588210

Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue

{"title":"A p-GaN HEMT Voltage Reference With High Line Sensitivity and Power Supply Rejection Ratio","authors":"Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue","doi":"10.1109/JEDS.2025.3588210","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588210","url":null,"abstract":"A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to <inline-formula> <tex-math>$250~{^{circ }}$ </tex-math></inline-formula>C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"630-637"},"PeriodicalIF":2.4,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078414","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and Modeling of Intrinsic Capacitance in Enhancement Mode GaN HEMT 增强模式GaN HEMT本征电容的分析与建模

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-11 DOI: 10.1109/JEDS.2025.3588180

Taeyoung Cho;Jesun Park;Sungyeop Jung;Myounggon Kang

{"title":"Analysis and Modeling of Intrinsic Capacitance in Enhancement Mode GaN HEMT","authors":"Taeyoung Cho;Jesun Park;Sungyeop Jung;Myounggon Kang","doi":"10.1109/JEDS.2025.3588180","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588180","url":null,"abstract":"This paper analyzes the intrinsic capacitance of enhancement-mode (e-mode) Gallium Nitridebased High Electron Mobility Transistor (GaN HEMTs). The intrinsic capacitance was measured using <inline-formula> <tex-math>$C_{i s s}$ </tex-math></inline-formula> (input capacitance), <inline-formula> <tex-math>$C_{o s s}$ </tex-math></inline-formula> (output capacitance), and <inline-formula> <tex-math>$C_{r s s}$ </tex-math></inline-formula> (reverse transfer capacitance). The <inline-formula> <tex-math>$C_{o s s}$ </tex-math></inline-formula> was also analyzed. Based on depletion-mode (d-mode) measurement data from the MIT virtual source GaN HEMT (MVSG) compact model, a measurement circuit for <inline-formula> <tex-math>$C_{i s s}, C_{o s s}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$C_{r s s}$ </tex-math></inline-formula> was constructed and calibrated for reliability. Subsequently, the circuit, initially configured for d-mode GaN HEMT intrinsic capacitance measurements, was optimized for e-mode GaN HEMT, upon which intrinsic capacitance was measured. The influence on the graph was analyzed by varying parameters in the measured capacitance data, leading to the modeling of intrinsic capacitance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"638-641"},"PeriodicalIF":2.4,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078449","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cross-Temperature FeFETs Enabling Long- and Short-Term Memory for Reservoir Computing Network 油藏计算网络中实现长短期记忆的交叉温度效应

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-03 DOI: 10.1109/JEDS.2025.3585619

Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen

{"title":"Cross-Temperature FeFETs Enabling Long- and Short-Term Memory for Reservoir Computing Network","authors":"Bo Chen;Yifan Wu;Yuwei Qu;Anlin Liu;Yuzhe Hu;Pengpeng Sang;Jixuan Wu;Xuepeng Zhan;Jiezhi Chen","doi":"10.1109/JEDS.2025.3585619","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3585619","url":null,"abstract":"Hardware neural networks based on emerging nonvolatile memory are promising candidates to overcome the Von Neumann computing bottleneck. This study investigates the device characteristics and reliability of ferroelectric field-effect transistors (FeFETs) with a focus on their temperature-dependent performance. At 300 K, the FeFET demonstrates a 6.2 V memory window (MW) with 26.4% endurance degradation after 107 program/erase (P/E) cycles and 92.39% retention after 104 s. The accelerated charge trapping/detrapping dynamics enable superior short-term memory (STM) functionality. Remarkably, cryogenic operation at 77 K enhances the MW to 8 V while achieving exceptional stability with merely 0.4% degradation after 107 cycles and 99.02% retention at 104 seconds. The enhanced characteristics make it ideal for long-term memory (LTM) applications. Moreover, a reservoir computing (RC) network is proposed based on the cross-temperature FeFETs. By integrating the STM properties at 300 K and the LTM benefits at 77 K, the proposed RC network achieves a classification accuracy of 76.73% on the CIFAR-10 image recognition task. This surpasses the standalone results of 41.65% and 23.69% of 300 K and 77 K conditions, respectively. The findings highlight the potential to develop highly energy-efficient FeFET-based neuromorphic computing with varying temperature systems.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"582-586"},"PeriodicalIF":2.0,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11067954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144671149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel Gate Fabrication Process Enhancing High-Frequency Operation in AlGaN/GaN HEMTs for Ka-Band Applications 新型栅极制造工艺增强了ka波段应用中AlGaN/GaN hemt的高频工作

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-07-01 DOI: 10.1109/JEDS.2025.3584809

Neng-Da Li;Yueh-Chin Lin;Kai-Wen Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang

{"title":"Novel Gate Fabrication Process Enhancing High-Frequency Operation in AlGaN/GaN HEMTs for Ka-Band Applications","authors":"Neng-Da Li;Yueh-Chin Lin;Kai-Wen Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang","doi":"10.1109/JEDS.2025.3584809","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3584809","url":null,"abstract":"In this study, AlGaN/GaN high-electron-mobility-transistor (HEMTs) with a small gate length were fabricated using a stepper. Additionally, a novel gate fabrication process was conducted to shrink the gate head, thus reducing the parasitic capacitance of the device to achieve high-power amplifier performance. The device performance in the research demonstrated a steady-state current density (Idss) of 975 mA/mm and a maximum transconductance (gm) of 369 mS/mm at a 20 V bias. Moreover, the cut-off frequency (fT) reached 50.6 GHz, and the maximum oscillation frequency (fmax) achieved 161 GHz as measured by S-parameter measurement. In the load-pull system, the frequency operation is under 28 GHz. For the <inline-formula> <tex-math>$2times 50~mu $ </tex-math></inline-formula>m device at a drain bias of 20 V, it exhibits a maximum output power density (Pout) of 2.83 W/mm with a maximum 24.97% power-added efficiency (PAE). Additionally, for the <inline-formula> <tex-math>$8times 50~mu $ </tex-math></inline-formula>m device at a drain bias of 32V, it achieves a <inline-formula> <tex-math>$mathrm { P_{out}}$ </tex-math></inline-formula> of 1.27 W (3.18 W/mm). This work demonstrates that the novel gate fabrication process of shrinking gate head by using <inline-formula> <tex-math>$mathrm { SiN_{x}}$ </tex-math></inline-formula> shield achieves high-frequency and high-output power characteristics for Ka-band application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"593-598"},"PeriodicalIF":2.4,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11062583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimization of Guard Ring Structures for Superior Dark Current Reduction and Improved Quantum Efficiency in InGaAs/InP APDs InGaAs/InP apd中保护环结构的优化及暗电流减小和量子效率的提高

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-27 DOI: 10.1109/JEDS.2025.3583669

Zefang Xu;Yu Chang;Kai Qiao;Liyu Liu;Linmeng Xu;Mengyan Fang;Chang Su;Fei Yin;Jieying Wang;Tianye Liu;Ming Li;Dian Wang;Lizhi Sheng;Xing Wang

{"title":"Optimization of Guard Ring Structures for Superior Dark Current Reduction and Improved Quantum Efficiency in InGaAs/InP APDs","authors":"Zefang Xu;Yu Chang;Kai Qiao;Liyu Liu;Linmeng Xu;Mengyan Fang;Chang Su;Fei Yin;Jieying Wang;Tianye Liu;Ming Li;Dian Wang;Lizhi Sheng;Xing Wang","doi":"10.1109/JEDS.2025.3583669","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583669","url":null,"abstract":"Avalanche photodiodes (APDs) based on InGaAs/InP are pivotal for applications in low-light detection, yet their performance is often hindered by edge breakdown and high dark currents. This study systematically optimizes guard ring structures to address these challenges, focusing on attached guard rings (AGRs) and floating guard rings (FGRs) through a synergistic approach combining simulation-guided design, fabrication, and experimental validation. We analyze the impact of Zn diffusion depth, AGR/FGR geometries, and electric field distribution on device performance. Experimental results demonstrate that optimized AGR structures reduce dark currents by 70% and enhance quantum efficiency (QE) by 43%, while FGR structures achieve an order-of-magnitude reduction in dark current and a 90% QE improvement compared to non-guarded devices. The breakdown voltage increases by 2.5 V (AGR) and 4 V (FGR), leading to enhanced gain. These advancements highlight the critical role of guard ring optimization in effectively mitigating edge breakdown, offering a pathway to high-sensitivity InGaAs/InP APDs for photon detection technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"551-557"},"PeriodicalIF":2.0,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11053970","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unraveling the Origins of Fatigue in Hafnia Ferroelectric Capacitors 揭示铪铁电电容器疲劳的起源

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-27 DOI: 10.1109/JEDS.2025.3583931

Hyeon-Seo Do;Ik-Jyae Kim;Jiwoung Choi;Jang-Sik Lee

引用次数: 0

Evaluation of p-GaN-gate All-GaN Cascode HEMT on SiC Substrate: DC Characteristics and Switching Performance SiC衬底上p- gan栅极全gan级联HEMT的评价：直流特性和开关性能

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-24 DOI: 10.1109/JEDS.2025.3582342

Dian-Ying Wu;Chih-Yung Hsieh;Yi-Xian Huang;Yu-Chen Liu;Wen-Ching Hsu;Ci-Ze Li;Jia-Zhe Liu;Cheng-Yeu Wu;Meng-Chyi Wu

{"title":"Evaluation of p-GaN-gate All-GaN Cascode HEMT on SiC Substrate: DC Characteristics and Switching Performance","authors":"Dian-Ying Wu;Chih-Yung Hsieh;Yi-Xian Huang;Yu-Chen Liu;Wen-Ching Hsu;Ci-Ze Li;Jia-Zhe Liu;Cheng-Yeu Wu;Meng-Chyi Wu","doi":"10.1109/JEDS.2025.3582342","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3582342","url":null,"abstract":"This article compares p-GaN-gate all-GaN cascode devices with standalone E-mode HEMTs on SiC substrates, with a focus on double pulse testing (DPT), a critical method for evaluating switching performance under realistic operating conditions. The all-GaN cascode, featuring a gate width of 85 mm, demonstrates a current rating of 15.6 A, an on-resistance of 7.7 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-cm2, a breakdown voltage of 970 V, and turn-on/off times of 71/52 ns, respectively. Additionally, it exhibits switching energy losses of 17/<inline-formula> <tex-math>$8.2~mu $ </tex-math></inline-formula>J at <inline-formula> <tex-math>$V_{DS} ,, {=} ,, 400$ </tex-math></inline-formula> V and <inline-formula> <tex-math>$I_{DS} ,, {=} ,, 1$ </tex-math></inline-formula> A. Its dynamic RDS,on is measured at <inline-formula> <tex-math>$0.7~Omega $ </tex-math></inline-formula> at <inline-formula> <tex-math>$V_{DS} ,, {=} ,, 300$ </tex-math></inline-formula> V and <inline-formula> <tex-math>$I_{DS} ,, {=} ,, 1$ </tex-math></inline-formula> A. The experimental results indicate a significant improvement compared to the standalone E-mode HEMT. This highlights the advantages of the all-GaN cascode in reducing dynamic resistance and enhancing switching efficiency, making it an excellent choice for high-performance applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"642-648"},"PeriodicalIF":2.4,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11049654","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Tunability in 3-Gated Reconfigurable Transistor for Analog/RF Applications 模拟/射频应用中3门可重构晶体管的电可调性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-20 DOI: 10.1109/JEDS.2025.3581677

Chinmayi Adoni;Sandeep Semwal;Manish Gupta;Jean-Pierre Raskin;Abhinav Kranti

{"title":"Electrical Tunability in 3-Gated Reconfigurable Transistor for Analog/RF Applications","authors":"Chinmayi Adoni;Sandeep Semwal;Manish Gupta;Jean-Pierre Raskin;Abhinav Kranti","doi":"10.1109/JEDS.2025.3581677","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3581677","url":null,"abstract":"The potential of electrical tunability in a 3-gated (3G) Reconfigurable Field Effect Transistor (RFET) for analog/RF applications is investigated through four distinct configurations (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula>, R<inline-formula> <tex-math>${}_{text {1-IG-Ambi}}$ </tex-math></inline-formula>, R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>, and R<inline-formula> <tex-math>${}_{text {2-IG-HVT}}$ </tex-math></inline-formula>). The electrical connections through two program gates (PG) and one control gate (CG) in 3G-RFET supports the implementation of configurations suitable for low-VTH (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula> and R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>) and high-VTH (R<inline-formula> <tex-math>${}_{text {2-IG-HVT}}$ </tex-math></inline-formula>), phase follower/reversal (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula>), frequency doubler (R<inline-formula> <tex-math>${}_{text {1-IG-Ambi}}$ </tex-math></inline-formula>), high gain (R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>), lower parasitic capacitance (R<inline-formula> <tex-math>${}_{text {2-IG-LVT}}$ </tex-math></inline-formula> and R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>), and higher linearity (R<inline-formula> <tex-math>${}_{text {3-IG-LVT}}$ </tex-math></inline-formula>) applications. Results showcase electrical tunability as an opportunity to realize many analog/RF features–in–one nanoscale 3G-RFET.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"558-565"},"PeriodicalIF":2.0,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11045726","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144598037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Defects on the Low-Field Electron Mobility in GaN-on-Si HEMTs GaN-on-Si hemt中缺陷对低场电子迁移率的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-11 DOI: 10.1109/JEDS.2025.3577260

Ran Zhou;D. J. Gravesteijn;R. J. E. Hueting

{"title":"Impact of Defects on the Low-Field Electron Mobility in GaN-on-Si HEMTs","authors":"Ran Zhou;D. J. Gravesteijn;R. J. E. Hueting","doi":"10.1109/JEDS.2025.3577260","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3577260","url":null,"abstract":"In this work, we investigate the field and temperature dependence of the electron mobility in aluminum-gallium-nitride/gallium-nitride (AlGaN/GaN) high electron mobility transistors (HEMTs) realized on GaN-on-silicon (Si) substrates. For this purpose we employ an extraction method to eliminate parasitic and fringing effects. Our results show that especially at low fields the temperature dependence of the mobility, and consequently that of the specific on-resistance, is strongly affected by stress-induced charged dislocation scattering. For explaining the mobility behaviour at low fields, the subthreshold operation regime of the HEMTs has also been analyzed. An interface trap density at the AlGaN/GaN interface <inline-formula> <tex-math>$(N_{textrm {it}})$ </tex-math></inline-formula> of <inline-formula> <tex-math>$sim ~6.9times 10^{10}$ </tex-math></inline-formula> cm−2 has been extracted independent of the temperature which is close to the extracted dislocation density from mobility measurements. This suggests that the relatively high dislocation density in the GaN layer, which is a consequence of the still imperfect buffer layer in the GaN-on-Si substrate that is used to accommodate the strain difference, has an impact on <inline-formula> <tex-math>$N_{textrm {it}}$ </tex-math></inline-formula>, thus subthreshold swing, in addition to the mobility reduction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"516-523"},"PeriodicalIF":2.0,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11031174","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144472684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0