IEEE Journal of the Electron Devices Society最新文献_第3页

Research on Degradation of P-FinFET Under Mixed NBTI and HCD Stress NBTI和HCD混合应力下P-FinFET的降解研究

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-13 DOI: 10.1109/JEDS.2026.3653934

Yanghao Wang;Hang Xu;Peng Liao;Jianbin Guo;Qingqing Sun;David Wei Zhang

{"title":"Research on Degradation of P-FinFET Under Mixed NBTI and HCD Stress","authors":"Yanghao Wang;Hang Xu;Peng Liao;Jianbin Guo;Qingqing Sun;David Wei Zhang","doi":"10.1109/JEDS.2026.3653934","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653934","url":null,"abstract":"In this paper, the stress degradation of P-channel Fin Field-Effect Transistor (FinFET) under AC mixed NBTI and HCD stress is studied and compared with the effects of individual NBTI and HCD. In the scope of this study, degradation caused by interface traps becomes more and more dominant with the increase of individual NBTI stress. The more significant degradation observed under individual HCD stress, in comparison to individual NBTI stress at the same voltage, may primarily be attributed to an increase in interfacial traps. The AC mixed stress experiment demonstrates that the interruption of NBTI stress persistence leads to a significant reduction in the defect components within the oxide layer affected by NBTI. Even when NBTI accounts for 85% of the total degradation, the overall extent of degradation remains considerably lower than that observed with single NBTI. Consequently, in AC scenarios, interface traps emerge as the primary contributors to degradation. This finding may hold substantial implications for circuit designers. In practical AC applications, it may reduce the design margin allocated to degradation, thereby avoiding overdesign.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"70-78"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Geometric and Area Scaling Effects on Ferroelectric Properties of Al₀.₈Sc₀.₂N-Based Capacitive Memory Al₀₈Sc₀铁电性能的几何和面积缩放效应基于2n的电容存储器

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-04-20 DOI: 10.1109/JEDS.2026.3685619

Yoojin Lim;Hyeong Jun Joo;Sisung Yoon;Geonwook Yoo

{"title":"Geometric and Area Scaling Effects on Ferroelectric Properties of Al₀.₈Sc₀.₂N-Based Capacitive Memory","authors":"Yoojin Lim;Hyeong Jun Joo;Sisung Yoon;Geonwook Yoo","doi":"10.1109/JEDS.2026.3685619","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3685619","url":null,"abstract":"In this letter, we investigate the geometric and area dependence of ferroelectric behavior in Al0.8Sc0.2N-based metal-ferroelectric-metal capacitors. Circular and square top electrodes with areas ranging from 707 to 2,<inline-formula> <tex-math>$500~mu $ </tex-math></inline-formula>m2 are employed to examine the influence of electrode geometry on polarization switching, dielectric response, and reliability. As the electrode area decreases, the apparent remnant polarization and measured dielectric constant increases from 80 to <inline-formula> <tex-math>$97~mu $ </tex-math></inline-formula>C/cm2 and 17.1 to 19.7. This scaling trend is associated with the periphery-to-area ratio rather than intrinsic material changes. Smaller electrodes exhibit higher peak switching current densities (up to 48.7 A/cm2), indicating enhanced switching near the electrode edges. The coercive field (EC) shows shape-dependent trends: square electrodes exhibit higher <inline-formula> <tex-math>$rm E_{C}$ </tex-math></inline-formula> at smaller sizes due to corner-induced non-uniformity, whereas circular electrodes show increased <inline-formula> <tex-math>$rm E_{C}$ </tex-math></inline-formula> at larger areas. Retention and endurance measurements demonstrate stable operation across all geometries, with a wake-up effect observed during cycling. Finite-element simulations indicate that the observed scaling behavior originates from localized electric-field enhancement near the electrode perimeter. These results emphasize the role of electrode geometry on the apparent scaling behavior of Al0.8Sc0.2N ferroelectric capacitors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"242-249"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11488507","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2xVDD-Tolerant ESD Clamp With Dual Detection and Ultra-Low Leakage 2xdd耐静电钳，双检测，超低漏

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-17 DOI: 10.1109/JEDS.2026.3674432

Kuan-Ying Chen;Shih-Hsin Wu;Po-Xiao Chen;Chun-Yu Lin

{"title":"2xVDD-Tolerant ESD Clamp With Dual Detection and Ultra-Low Leakage","authors":"Kuan-Ying Chen;Shih-Hsin Wu;Po-Xiao Chen;Chun-Yu Lin","doi":"10.1109/JEDS.2026.3674432","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3674432","url":null,"abstract":"Although conventional power-rail electrostatic discharge (ESD) clamp circuits are essential for ESD protection, they are prone to false triggering during fast power-on events. This phenomenon can lead to excessive current consumption and potential reliability concerns. Furthermore, leakage current exacerbates these issues by increasing static power dissipation and compromising long-term stability. To address these challenges, this study proposes a power-rail ESD clamp circuit that is tolerant to 2xVDD. This circuit incorporates a dual detection mechanism, integrating time detection and voltage detection to prevent false triggering during fast power-on events. Additionally, N-well and deep N-well isolation techniques are employed to effectively suppress parasitic NPN structures, thereby reducing leakage current and enhancing ESD robustness. The proposed circuit is implemented using the TSMC 180 nm CMOS process. Measurement results indicate that at room temperature, the leakage current is maintained at the level of nanoampere, and the circuit achieves a human-body-model (HBM) ESD robustness exceeding 8 kV. Even under 2xVDD operation, the design maintains ultra-low leakage current and exhibits excellent ESD protection capabilities, thereby improving energy efficiency and long-term reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"205-212"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11440071","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of Atomic Layer Etching on n-GaN MOS Capacitors 原子层蚀刻对n-GaN MOS电容器的影响

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-06-03 DOI: 10.1109/JEDS.2026.3700059

Sesha Gopal Selvakumar;Tobias Claus;Dong Wang

{"title":"Effect of Atomic Layer Etching on n-GaN MOS Capacitors","authors":"Sesha Gopal Selvakumar;Tobias Claus;Dong Wang","doi":"10.1109/JEDS.2026.3700059","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3700059","url":null,"abstract":"Gallium nitride (GaN) with its high breakdown voltage and low specific on resistance is suitable for high voltage power electronic applications. Common dry etching processes such as reactive ion etching with an inductively coupled plasma (ICP-RIE), however, damage the surface and affect the electrical performance of the fabricated devices. This work aims to investigate the restorative effect of Atomic Layer Etching (ALE) to improve the surface of GaN post dry etching. To this end, Metal-Oxide-Semiconductor capacitors (MOSCAPs) were fabricated on n-doped GaN-on-Si (111) substrates with on wafer splits to study ALE and compare it with ICP-RIE on various rubrics. The sample surfaces were characterized using Atomic Force Microscopy (AFM) and Photoluminescence (PL) measurements while the MOSCAPs were characterized via Capacitance-Voltage (CV) measurements. ALE shows a clear improvement in surface roughness, PL peak intensity and flatband voltage displacement in CV curves when performed on GaN after dry etching. ALE performed on pristine GaN deteriorated the surface, implying that ALE induces damage onto the surface. The ion energy of the sputtered ions in ALE played a key role in the recovery induced onto the surface post dry etching, with lower values causing lower damage, which is preferrable for better end device performance. The number of ALE cycles played no significant role in improving the surface quality. Additionally, a correlation was found between AFM, PL and CV measurements.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"383-388"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11550106","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unveiling Time-Dependent Dynamics in MFMIS FeFETs 揭示MFMIS效应场的时变动力学

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-21 DOI: 10.1109/JEDS.2026.3695545

Simin Chen;Taewon Jin;Xinkai Sun;Gijun Ju;Zewei Wang;Jaehoon Han;Younghyun Kim

{"title":"Unveiling Time-Dependent Dynamics in MFMIS FeFETs","authors":"Simin Chen;Taewon Jin;Xinkai Sun;Gijun Ju;Zewei Wang;Jaehoon Han;Younghyun Kim","doi":"10.1109/JEDS.2026.3695545","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3695545","url":null,"abstract":"Metal–ferroelectric–metal–insulator–semiconductor (MFMIS) ferroelectric field-effect transistors (FeFETs) using an amorphous indium–tin–zinc-oxide (a-ITZO) channel and Hf<inline-formula> <tex-math>${}_{mathbf {0.5}}$ </tex-math></inline-formula>Zr<inline-formula> <tex-math>${}_{mathbf {0.5}}$ </tex-math></inline-formula>O<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula> (HZO) ferroelectric layer are fabricated. By engineering the area ratio (AR = A<inline-formula> <tex-math>${}_{mathbf {I}}$ </tex-math></inline-formula>/A<inline-formula> <tex-math>${}_{mathbf {F}}$ </tex-math></inline-formula>) between the MIS transistor region and the MFM ferroelectric-capacitor region, the memory window (MW) can be continuously tuned while maintaining robust erase operation. To probe time-dependent behavior, single-sweep readouts are performed after program/erase pulses with a controlled delay time (T<inline-formula> <tex-math>${}_{mathbf {delay}}$ </tex-math></inline-formula>). We found that, as Tdelay increases, the threshold voltage (V<inline-formula> <tex-math>${}_{mathbf {th}}$ </tex-math></inline-formula>) shift of the program becomes larger than that of the erase under pulsed conditions, producing a progressive reduction—and at low AR, a possible inversion—of the MW. This asymmetric delay dependence has not been reported previously for oxide-semiconductor MFMIS FeFETs. Guided by the experimental trends, we propose a band-diagram-based mechanism that explicitly incorporates oxygen-vacancy-related traps at the HZO/floating-gate interfaces. The model attributes the observed evolution to the interplay among ferroelectric polarization relaxation, charge trapping/de-trapping in the floating gate. These findings establish AR engineering and delay-aware operation as effective levers to optimize MW, retention, and erase behavior in AOS-based MFMIS FeFETs, paving the way for compensation-free display drivers and embedded non-volatile memory.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"332-338"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11533180","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of Back-Gate Bias-Induced Interfaces on the Zero-Temperature-Coefficient in Fully Depleted SOI Transistors 全耗尽SOI晶体管中后门偏置接口对零温度系数的影响

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-07-28 DOI: 10.1109/JEDS.2026.3717628

Dae-Young Jeon;Yeonsu Kim;Mikaël Cassé;Sergio Nicoletti;Gyu-Tae Kim

引用次数: 0

Ge-on-Si Photodetector With Broadband Spectral Response and High Gain 宽带光谱响应和高增益锗硅光电探测器

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-16 DOI: 10.1109/JEDS.2026.3674330

Zhou Zhou;Chao Gao;Zequn Zheng;Xin Jin;Xiaolin Liu;Yihong Qi;Kai Wang

{"title":"Ge-on-Si Photodetector With Broadband Spectral Response and High Gain","authors":"Zhou Zhou;Chao Gao;Zequn Zheng;Xin Jin;Xiaolin Liu;Yihong Qi;Kai Wang","doi":"10.1109/JEDS.2026.3674330","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3674330","url":null,"abstract":"We propose a photodetector, referred to as the germanium photodiode–body-biased MOSFET (GePD-MOS), which integrates a Ge-on-Si photodiode with a body-biased MOSFET to achieve high gain and broadband short-wavelength infrared (SWIR) detection. In this architecture, the photo-induced body effect acts in conjunction with gate control to modulate the channel current, enabling gain-tunable and high-responsivity operation. Technology Computer-Aided Design (TCAD) simulations were conducted with calibrated material parameters accounting for threading dislocation effects, and the device structure was optimized to enhance optoelectronic performance. The results demonstrate high responsivity and wide spectral coverage extending from the UV to the SWIR region. A proof-of-concept prototype, experimentally implemented by wire-bonding a commercial Ge photodiode to a MOSFET substrate, confirms the photo-induced body effect in agreement with the simulated trend. A peak responsivity of <inline-formula> <tex-math>$sim 10{^{{4}}}$ </tex-math></inline-formula> A/W at 1550 nm and ~3 A/W at 245 nm was observed. These findings indicate that the GePD-MOS design offers an effective solution for broadband, high-sensitivity detection, with potential CMOS compatibility and applications in imaging, multispectral sensing, and integrated photonics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"686-693"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11434874","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ESD Protection With Sub-3Ω Dynamic Resistance for Neuromodulation System-on-Chip ESD保护与Sub-3Ω动态电阻神经调节片上系统

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-02-10 DOI: 10.1109/JEDS.2026.3663915

Tanay Das;Naef Ahmad;Laxmeesha Somappa;Sandip Lashkare

{"title":"ESD Protection With Sub-3Ω Dynamic Resistance for Neuromodulation System-on-Chip","authors":"Tanay Das;Naef Ahmad;Laxmeesha Somappa;Sandip Lashkare","doi":"10.1109/JEDS.2026.3663915","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3663915","url":null,"abstract":"Implantable neurostimulators are critical for treating neurological disorders and require compact CMOS systems with long-term reliability. Electrostatic discharge (ESD) can damage thin oxide layers in the CMOS and can cause significant damage to systems. Conventional ESD protection circuits, such as clamp-based schemes with implicit or explicit diodes, are practical but require considerable area and complexity. Conversely, simpler protection architectures are more suitable for high-voltage neural interfaces, for which area and robustness are the key requirements. The major challenge is to achieve efficient ESD protection while ensuring operational safety and low layout area. This paper presents a compact back-to-back diode–based ESD protection design for neurostimulators in 65 nm CMOS technology, primarily targeting HBM-level ESD protection. The circuit has also been tested for CDM-level robustness; however, the main focus of this work remains on achieving reliable HBM performance. The proposed back-to-back diode design reduces clamping voltage by ~53% and dynamic resistance by ~89% when compared with implicit clamps while meeting the normal voltage operation range. In addition, the proposed design reduces dynamic resistance by more than 92% compared to the typical foundry design. As a result, ESD protection can be decoupled from stimulator drivers, allowing for more modular and area-efficient H-bridge designs. This simplifies the layout, eliminates the need for clamping transistors, and provides robust bidirectional ESD protection. Our work proposes a scalable ESD strategy appropriate for next-generation implantable SoC-based biomedical devices by addressing electrical and physical constraints.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"702-709"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11391546","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148749112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact Modeling of a Charge-Accumulation-Based Dual-Gate Feedback Field-Effect Transistor for Circuit-Level Analysis 基于电荷积累的双栅反馈场效应晶体管电路级分析的紧凑建模

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-09-03 DOI: 10.1109/JEDS.2026.3730701

Jaewon Lee;Min-Woo Kwon

{"title":"Compact Modeling of a Charge-Accumulation-Based Dual-Gate Feedback Field-Effect Transistor for Circuit-Level Analysis","authors":"Jaewon Lee;Min-Woo Kwon","doi":"10.1109/JEDS.2026.3730701","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3730701","url":null,"abstract":"In this work, we develop a SPICE-compatible compact model for a fabricated dual-gate positive feedback field-effect transistor (FBFET) based on measured device characteristics. The model parameters are quantitatively extracted to reproduce the DC transfer characteristics, temperature-dependent switching behavior, and transient responses of the device. The proposed framework captures the charge injection–accumulation–positive feedback mechanism responsible for abrupt switching and the characteristic delay associated with charge accumulation in the floating body. Temperature-dependent variations in threshold voltage and drain current are incorporated using experimentally calibrated scaling parameters. In addition, an ONO-based charge-trapping module is incorporated using TCAD-extracted memory-window characteristics as an exploratory extension toward charge-trap memory and processing-in-memory applications. Finally, the circuit-level applicability of the proposed model is validated by comparing the measured and SPICE-simulated responses of a fabricated FBFET-based hybrid inverter. The model successfully reproduces the inverter operation and the drain-voltage-dependent pull-down limitation of the FBFET, demonstrating its practical applicability to circuit-level analysis.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"808-819"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11677113","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unified Physical Understanding of Current-Filament Stability in IGBTs Based on a 1-D Space-Charge-Region Framework 基于一维空间-电荷-区域框架的igbt中电流-灯丝稳定性的统一物理理解

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-10-05 DOI: 10.1109/JEDS.2026.3740486

Taichi Fukuda;Ryohei Gejo;Yusuke Kobayashi

{"title":"Unified Physical Understanding of Current-Filament Stability in IGBTs Based on a 1-D Space-Charge-Region Framework","authors":"Taichi Fukuda;Ryohei Gejo;Yusuke Kobayashi","doi":"10.1109/JEDS.2026.3740486","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3740486","url":null,"abstract":"We analyze the space-charge-region (SCR) physics governing current-filament stability in IGBTs using a one-dimensional model based on Gauss’s law and carrier continuity equations. We show that both clamped inductive switching (CIS) and unclamped inductive switching (UIS), despite traditionally being analyzed separately, are governed by the same SCR differential equations with different boundary conditions. This establishes a unified physical framework that explains the vertical electric-field formation in IGBT switching transients. Using this unified SCR model, we analyze the electrical conditions governing current-filament persistence and extinction. The critical current density <inline-formula> <tex-math>$j_{mathrm {crit}}$ </tex-math></inline-formula>, derived from the SCR voltage–current characteristics, is introduced as an isothermal electrical criterion under prescribed temperature and boundary conditions. In particular, a positive finite <inline-formula> <tex-math>$j_{mathrm {crit}}$ </tex-math></inline-formula> exists for high collector injection efficiency, whereas in SSCM no positive finite <inline-formula> <tex-math>$j_{mathrm {crit}}$ </tex-math></inline-formula> appears. This distinction indicates a stronger local tendency toward filament persistence in SSCM as the collector current approaches zero. These results establish a physics-based electrical criterion for filament stability and clarify the key factors governing IGBT robustness during high-current transient operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"887-897"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11720376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149188570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0