IEEE Journal of the Electron Devices Society最新文献_第3页

Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform for Reliable Cryogenic IC Design

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-17 DOI: 10.1109/JEDS.2025.3542589

Zhidong Tang;Zewei Wang;Yumeng Yuan;Chang He;Xin Luo;Ao Guo;Renhe Chen;Yongqi Hu;Longfei Yang;Chengwei Cao;Lin Lin Liu;Liujiang Yu;Ganbing Shang;Yongfeng Cao;Shoumian Chen;Yuhang Zhao;Shaojian Hu;Xufeng Kou

引用次数: 0

Harmonic Enhancement of Terahertz GaN Planar Gunn Oscillators With Multiple Gates

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-17 DOI: 10.1109/JEDS.2025.3543017

Ying Wang;Shuai Hui;Yu-Xin Fu;Yuan-Zhu Xia;He Guan

{"title":"Harmonic Enhancement of Terahertz GaN Planar Gunn Oscillators With Multiple Gates","authors":"Ying Wang;Shuai Hui;Yu-Xin Fu;Yuan-Zhu Xia;He Guan","doi":"10.1109/JEDS.2025.3543017","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543017","url":null,"abstract":"In this paper, we propose a novel design of GaN-based planar Gunn oscillator as terahertz signal source. The oscillator has multiple gates and each gate can be individually biased. By controlling gate bias voltage and distance to the barrier layer, the output oscillating current can be formed in such a way that the higher harmonics are more powerful than the fundamental one. This is because multiple Gunn domains created under the gates in the channel are synchronized. Compared to the conventional single-domain diode, this multi-gate configuration not only increases the frequency and output power but also provides superior harmonic control, leading to higher efficiency and more stable operation at terahertz frequencies. We will review the design details and analysis on domain forming conditions using a physics-based numerical model. The optimal parameters for high power, high DC-RF conversion efficiency and high frequency will be given. Specifically, in dual-gate device, when it works in the dual-domain mode, the second harmonic is enhanced, reaching a frequency of 310.5 GHz with 7.6 mW of power and 11.2% efficiency. The tri-gate device operating in tri-domain mode further enhances the third harmonic to 417.0 GHz, with 9.57 mW of power and 9.23% efficiency. The multi-gate structure allows for more efficient harmonic generation, greater frequency tunability, and better power management, all of which are crucial for advanced terahertz application such as mixing, frequency multiplexing, and signal amplification.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"145-153"},"PeriodicalIF":2.0,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling of van der Waals-Based Photovoltaic Devices 基于范德华的光伏设备建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-14 DOI: 10.1109/JEDS.2025.3542168

Ángel A. Díaz-Burgos;Enrique G. Marin;Francisco Pasadas;Francisco G. Ruiz;Andrés Godoy

引用次数: 0

A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm²

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-13 DOI: 10.1109/JEDS.2025.3533920

Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu

{"title":"A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm²","authors":"Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2025.3533920","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3533920","url":null,"abstract":"In this letter, GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) are fabricated on Si substrates with an ultra-high breakdown voltage of over 3 kV using a 90-nm in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> layer as both the gate dielectric and surface passivation. The devices exhibit low off-state leakage current (on/off ratio of <inline-formula> <tex-math>$10{^{{9}}}$ </tex-math></inline-formula>), high forward gate breakdown voltage (>122 V), and state-of-the-art figure of merit (685 MW/cm2). Moreover, the reliability of the in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> dielectric is evaluated through the high-temperature gate bias test. The results are fitted with a Weibull distribution, estimating a 10-year estimation of 100 ppm. The maximum gate-source voltage of over 70 V is obtained. This letter presents a strategy for mass producing GaN-on-Si MISHEMTs with high breakdown voltage and reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"106-111"},"PeriodicalIF":2.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10886964","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Understanding the Slow Erase Operation in IGZO-Channel FeFETs: The Role of Positive Charge Generation Kinetics

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-12 DOI: 10.1109/JEDS.2025.3541418

Zhuo Chen;Nicolò Ronchi;Roman Izmailov;Hongwei Tang;Mihaela Ioana Popovici;Harold Dekkers;Alexandru Pavel;Geert Van den Bosch;Maarten Rosmeulen;Valeri V. Afanas’Ev;Jan Van Houdt

{"title":"Understanding the Slow Erase Operation in IGZO-Channel FeFETs: The Role of Positive Charge Generation Kinetics","authors":"Zhuo Chen;Nicolò Ronchi;Roman Izmailov;Hongwei Tang;Mihaela Ioana Popovici;Harold Dekkers;Alexandru Pavel;Geert Van den Bosch;Maarten Rosmeulen;Valeri V. Afanas’Ev;Jan Van Houdt","doi":"10.1109/JEDS.2025.3541418","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3541418","url":null,"abstract":"This work systematically investigates the programming and erasing dynamics of IGZO-channel back-gated FeFETs, uncovering that erase operation is significantly slower than programming. PUND measurements in ferroelectric capacitors with IGZO top electrodes reveal that the ferroelectric switching kinetics under negative bias are limited by the generation of positive charges. Two underlying physical mechanisms are identified: (1) IGZO-bandgap donor states, which can get positively charged by emitting electrons to Conduction Band and reversibly neutralized during programming, help ferroelectric switching and limits the switching kinetics; and (2) hydrogen doping into IGZO, which proceeds at a much slower rate and is irreversible, thus incapable of supporting ferroelectric switching. This work emphasizes the importance to deepen the understanding of erasing kinetics to enable low-latency, and high-endurance applications of oxide-semiconductor-channel FeFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"245-251"},"PeriodicalIF":2.0,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10883345","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-11 DOI: 10.1109/JEDS.2025.3540581

Kaifeng Wang;Pengfei Hao;Fangxing Zhang;Lining Zhang;Qianqian Huang;Ru Huang

{"title":"Logic-Compatible Asymmetrical FET for Gain Cell eDRAM With Long Retention and Fast Access Speed","authors":"Kaifeng Wang;Pengfei Hao;Fangxing Zhang;Lining Zhang;Qianqian Huang;Ru Huang","doi":"10.1109/JEDS.2025.3540581","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3540581","url":null,"abstract":"A novel Asymmetrical FET (AsyFET) is proposed to enhance the retention of gain cell memory and is experimentally demonstrated based on standard 300mm logic foundry platform. In AsyFET, the asymmetrical S/D doping and S/D gate spacer are designed to suppress leakage current. The modulated Schottky direct tunneling current and band-to-band tunneling current are designed to write “1” and “0” respectively without write disturb. The AsyFET-based 2T0C DRAM with significantly enhanced retention and fast access speed is also proposed and experimentally demonstrated on the same wafer. Without area penalty or new materials, the fabricated Si AsyFET can obtain ultralow off-state current of <inline-formula> <tex-math>$sim 10{^{-}17 }$ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, leading to the long retention above second-level in 55nm technology node across the 300mm wafer. The on-state currents of AsyFET at forward and reverse bias are <inline-formula> <tex-math>$sim 10{^{-}6 }$ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, enabling write speed of below 5ns with negligible temperature dependence. The experimental results show the great potential of proposed AsyFET 2T0C DRAM design for low-power, high-density, and high-speed on-chip memory.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"237-244"},"PeriodicalIF":2.0,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10879406","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Trap Analysis of Normally-Off Ga₂O₃ MOSFET Enabled by Charge Trapping Layer: Photon Stimulated Characterization and TDDB

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-07 DOI: 10.1109/JEDS.2025.3538769

Minghao He;Mujun Li;Chenkai Deng;Xiaohui Wang;Qing Wang;Hongyu Yu;Kah-Wee Ang

{"title":"Trap Analysis of Normally-Off Ga₂O₃ MOSFET Enabled by Charge Trapping Layer: Photon Stimulated Characterization and TDDB","authors":"Minghao He;Mujun Li;Chenkai Deng;Xiaohui Wang;Qing Wang;Hongyu Yu;Kah-Wee Ang","doi":"10.1109/JEDS.2025.3538769","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3538769","url":null,"abstract":"A charge trapping layer (CTL) technique is incorporated to achieve a normally-off Ga2O3 MOSFET. The gate dielectric was engineered using a stack composed of a blocking layer (16 nm <inline-formula> <tex-math>${mathrm { HfO}}_{mathrm { x}}$ </tex-math></inline-formula> / 2 nm Al2O3), a CTL (5.76 nm Al:HfO<inline-formula> <tex-math>${_{text {x}}}~1$ </tex-math></inline-formula>:5), and a tunneling barrier (2 nm Al2O3 / 2 nm <inline-formula> <tex-math>${mathrm { HfO}}_{mathrm { x}}$ </tex-math></inline-formula> / 2 nm Al2O3). The trap profile of the CTL layer and the interface of the gate dielectric and Ga2O3 channel are studied by photon-stimulated characterization, which yield highly uniform results, indicating the high quality and uniformity of the proposed method. Furthermore, we conducted a time-dependent dielectric breakdown (TDDB) test on devices both without a field plate (NOFP) and with a source-connected field plate (SFP) to investigate the dielectric failure mechanism and gain valuable insights for the design of CTL-based Ga2O3 MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"112-116"},"PeriodicalIF":2.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877719","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical and 850 nm Optical Characterization of Back-Gate Controlled 22 nm FDSOI PIN-Diodes Without Front-Gate

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-31 DOI: 10.1109/JEDS.2025.3537290

Jelle H. T. Bakker;Marcin Ł. Motycki;Raymond J. E. Hueting;Anne-Johan Annema;Mark S. Oude Alink

{"title":"Electrical and 850 nm Optical Characterization of Back-Gate Controlled 22 nm FDSOI PIN-Diodes Without Front-Gate","authors":"Jelle H. T. Bakker;Marcin Ł. Motycki;Raymond J. E. Hueting;Anne-Johan Annema;Mark S. Oude Alink","doi":"10.1109/JEDS.2025.3537290","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3537290","url":null,"abstract":"We present electrical and optical <inline-formula> <tex-math>$(lambda =rm {850~nm })$ </tex-math></inline-formula> measurement results of back-gate controlled SOI PIN-diodes without a front-gate, with an intrinsic Si film thickness of only <inline-formula> <tex-math>${sim }rm 6nm $ </tex-math></inline-formula>. These ultrathin-body PIN-diodes were fabricated as exploratory devices in a commercially available Fully-Depleted Silicon-On-Insulator (FDSOI) technology, without requiring additional process steps. We show that electrostatic back-gate tuning significantly affects the electrical characteristics and optical responsivity <inline-formula> <tex-math>$({{R_{mathrm { o}}}{}})$ </tex-math></inline-formula>. This leads to a novel method to extract the optimal back-gate bias for maximum <inline-formula> <tex-math>${R_{mathrm { o}}}{}$ </tex-math></inline-formula> from electrical measurements. The maximal measured <inline-formula> <tex-math>${R_{mathrm { o}}}{}$ </tex-math></inline-formula> at 0V bias across the diode and with optimal back-gate bias equals <inline-formula> <tex-math>$62{mu }$ </tex-math></inline-formula>A /W, with a -3dB bandwidth of 5.9GHz, and a -6dB bandwidth of 15GHz. These PIN-diodes potentially open the way to new (THz) circuits, sensors, novel/complementary process control monitoring structures, and optical applications. They also enable interaction between the hybrid (bulk) and SOI devices, which is a unique feature of FDSOI technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"190-199"},"PeriodicalIF":2.0,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10859268","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Call for Nominations for Editor-in-Chief

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3536136

引用次数: 0

Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528210

引用次数: 0