IEEE Journal of the Electron Devices Society最新文献_第3页

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach 使用神经紧凑建模方法分析应变对 3 纳米以下栅极全方位 CMOS 逻辑电路性能的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-13 DOI: 10.1109/JEDS.2024.3459872

Ji Hwan Lee;Kihwan Kim;Kyungjin Rim;Soogine Chong;Hyunbo Cho;Saeroonter Oh

{"title":"Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach","authors":"Ji Hwan Lee;Kihwan Kim;Kyungjin Rim;Soogine Chong;Hyunbo Cho;Saeroonter Oh","doi":"10.1109/JEDS.2024.3459872","DOIUrl":"10.1109/JEDS.2024.3459872","url":null,"abstract":"Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10680295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Parallel In-Memory Logic Array Based on Programmable Diodes 基于可编程二极管的新型并行内存逻辑阵列

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-10 DOI: 10.1109/JEDS.2024.3457021

Jiabao Ye;Junyu Zhu;Jifang Cao;Haoxiong Bi;Yong Ding;Bing Chen

{"title":"A Novel Parallel In-Memory Logic Array Based on Programmable Diodes","authors":"Jiabao Ye;Junyu Zhu;Jifang Cao;Haoxiong Bi;Yong Ding;Bing Chen","doi":"10.1109/JEDS.2024.3457021","DOIUrl":"10.1109/JEDS.2024.3457021","url":null,"abstract":"Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode—a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10674001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142198876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wafer-Scale Monolithic Integration of LEDs with p-GaN-Depletion MOSFETs on a GaN LED Epitaxial Layer 晶圆级单片集成 LED 与 GaN LED 外延层上的 p-GaN 损耗 MOSFET

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-06 DOI: 10.1109/JEDS.2024.3455256

Boseong Son;Huijin Kim;Young-Woong Lee;Purusottam Reddy Bommireddy;Si-Hyun Park

引用次数: 0

Negative Activation Energy of Gate Reliability in Schottky-Gate p-GaN HEMTs: Combined Gate Leakage Current Modeling and Spectral Electroluminescence Investigation 肖特基栅p-GaN HEMT中栅极可靠性的负活化能：栅极漏电流建模与光谱电致发光调查相结合

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-04 DOI: 10.1109/JEDS.2024.3454334

Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini

{"title":"Negative Activation Energy of Gate Reliability in Schottky-Gate p-GaN HEMTs: Combined Gate Leakage Current Modeling and Spectral Electroluminescence Investigation","authors":"Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini","doi":"10.1109/JEDS.2024.3454334","DOIUrl":"10.1109/JEDS.2024.3454334","url":null,"abstract":"For the first time, we use electrical characterization, spectrally-resolved electroluminescence measurements and degradation tests to explain the negative activation energy of gate reliability in power GaN HEMTs with p-GaN Schottky gate. First, the origin of gate leakage current was modeled. The results indicate that the gate leakage current originates from three different mechanisms: (i) thermionic emission of electrons from the uid-GaN layer across the AlGaN barrier, for gate voltages below threshold \u0000<inline-formula> <tex-math>$(V_{G} lt V_{TH})$ </tex-math></inline-formula>\u0000, (ii) thermionic emission of electrons from the channel to the p-GaN layer \u0000<inline-formula> <tex-math>$(V_{TH} lt V_{G} lt 4.5 V)$ </tex-math></inline-formula>\u0000 and (iii) trap-assisted-tunneling of holes at the Schottky metal for higher gate voltages. Then, the analysis of the reliability as function of gate bias demonstrated a negative activation energy (longer lifetime at high temperature). By analyzing the electroluminescence spectra under high positive bias, the improved time to failure at high temperatures was ascribed to the increased hole injection and recombination, that reduces the overall number of electrons that undergo avalanche multiplication, leading to the breakdown. Finally, the model was validated by comparing the electrical properties and conduction model of the devices pre- and post-stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10664574","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly Uniform Low Gray AMOLED Pixel Using Stable Circuit and Duty Ratio Modulation Driving 利用稳定电路和占空比调制驱动高度均匀的低灰度 AMOLED 像素

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-02 DOI: 10.1109/JEDS.2024.3452753

Chanjin Park;Hee-Ok Kim;Jong-Heon Yang;Jae-Eun Pi;Yong-Duck Kim;Chun-Won Byun;Kyeong-Soo Kang;Ji-Hwan Park;Minji Kim;Hyoungsik Nam;Soo-Yeon Lee

{"title":"Highly Uniform Low Gray AMOLED Pixel Using Stable Circuit and Duty Ratio Modulation Driving","authors":"Chanjin Park;Hee-Ok Kim;Jong-Heon Yang;Jae-Eun Pi;Yong-Duck Kim;Chun-Won Byun;Kyeong-Soo Kang;Ji-Hwan Park;Minji Kim;Hyoungsik Nam;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3452753","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3452753","url":null,"abstract":"In this paper, a new pixel circuit for active matrix organic light-emitting diode (AMOLED) display that can achieve high uniformity in low gray levels and its driving method are proposed. The proposed circuit compensates for threshold voltage variation of thin-film-transistors (TFTs), with the structure that minimizes the loss of sensed threshold voltage. However, the high current error rate in extremely low gray level is unavoidable, as the driving TFT (DRT) operates in subthreshold region, where the current difference caused by the threshold voltage variation can be severe. To suppress high error rates in low gray levels, the operation region of DRT is restricted to the saturation region, by adopting duty ratio modulation (DRM) method. With the DRM method, low gray is expressed with high current value and short emission time. The viability of the proposed circuit and its operation are analyzed with HSPICE. Compared to the conventional driving method, DRM significantly reduces the current error rate in low gray area. The proposed circuit is fabricated within 220 \u0000<inline-formula> <tex-math>$mu {mathrm {m}} times 440 mu {mathrm {m}}$ </tex-math></inline-formula>\u0000. The measurement of the circuit also verified the capability of the proposed circuit and the DRM method.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142159891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Approach to Determine Noise Model Parameter for Submicron MOSFET from RF Noise Figure Measurement 从射频噪声系数测量中确定亚微米 MOSFET 噪声模型参数的方法

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-02 DOI: 10.1109/JEDS.2024.3453408

Hanqi Gao;Jing Jin;Jianjun Zhou

引用次数: 0

High Power 190 GHz Frequency Doubler Based On GaAs Schottky Diode 基于砷化镓肖特基二极管的 190 GHz 高功率倍频器基座

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-02 DOI: 10.1109/JEDS.2024.3453122

Nan Wu;Zhi Jin;Jingtao Zhou;Haomiao Wei;Zhicheng Liu;Jianming Lin

引用次数: 0

Impact of the Scaling of LGS and LG on the On-State Breakdown Voltage of InAlN/GaN HFETs With Localized Fin Under the Gate Electrode 栅电极下有局部鳍片的 InAlN/GaN HFET 的 LGS 和 LG 缩放对通态击穿电压的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-08-26 DOI: 10.1109/JEDS.2024.3449798

Yatexu Patel;Pouya Valizadeh

引用次数: 0

Discrete-Trap Effects on 3-D NAND Variability – Part I: Threshold Voltage 离散阱对 3-D NAND 变异性的影响 - 第一部分：阈值电压

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-08-21 DOI: 10.1109/JEDS.2024.3447149

Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli

引用次数: 0

Temperature-Dependent Electrical Characteristics and Low-Frequency Noise Analysis of AlGaN/GaN HEMTs AlGaN/GaN HEMT 随温度变化的电气特性和低频噪声分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-08-21 DOI: 10.1109/JEDS.2024.3447022

Qiang Chen;Y. Q. Chen;Chang Liu;Zhiyuan He;Yuan Chen;K. W. Geng;Y. J. He;W. Y. Chen

{"title":"Temperature-Dependent Electrical Characteristics and Low-Frequency Noise Analysis of AlGaN/GaN HEMTs","authors":"Qiang Chen;Y. Q. Chen;Chang Liu;Zhiyuan He;Yuan Chen;K. W. Geng;Y. J. He;W. Y. Chen","doi":"10.1109/JEDS.2024.3447022","DOIUrl":"10.1109/JEDS.2024.3447022","url":null,"abstract":"In this paper, we investigate the electrical characteristics of AlGaN/GaN HEMTs at the lowest temperature of 20 K. The measurement results indicate that the output current of the device decreases significantly with increasing temperature at temperature ranging from 40 K to 260 K, and the saturation drain current decreases by 19%. The gate leakage current rises slightly when the temperature increases. However, both the transfer and C-V characteristics indicate that the threshold voltage shift slightly in a negative direction as the temperature rises. In order to determine the physical mechanism of electrical characteristics change, the low-frequency noise (LFN) characteristics at different temperatures were measured and the density of traps was extracted. Finally, we consider that there are two competing mechanisms affecting the electrical characteristics of devices. The trap density reduction caused by temperature rise leads to threshold voltage’s negative shift, while the drop of 2DEG mobility is the main reason for the decrease of output current.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643171","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0