{"title":"High Output Power and Efficiency 300-GHz Band InP-Based MOS-HEMT Power Amplifiers With Composite-Channel and Double-Side Doping","authors":"Yusuke Kumazaki;Shiro Ozaki;Naoya Okamoto;Naoki Hara;Yasuhiro Nakasha;Masaru Sato;Toshihiro Ohki","doi":"10.1109/JEDS.2024.3483305","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3483305","url":null,"abstract":"This paper demonstrated high-output-power and high-efficiency power amplifier (PA) monolithic microwave-integrated circuit (MMIC) at 300-GHz band (252–296 GHz) with the use of InPbased metal–oxide–semiconductor high-electron-mobility transistors (HEMTs) with composite-channel (CC) and double-side-doping (DD) techniques. The CC-DD structure obtained high output current and low channel resistance due to the improved carrier density and mobility. W-band load-pull measurement revealed the drastically improved output power density of CC-DD structure compared with that of singlechannel DD structure. The 2-stage cascaded, 4-way, and 16-way PA-MMICs were designed based on stacked common-gate transistors with current reuse topology. The cascaded PA-MMIC exhibited a poweradded efficiency (PAE) of 7.8%, and the 16-way PA-MMIC exhibited an output power of 16.9 dBm. These values are the highest among all the values reported for the 300-GHz band PA-MMICs. The 4-way PA-MMIC achieved a high output power of 13.6–14.6 dBm and high PAE of 4.8%–6.3% simultaneously at the entire 300-GHz band.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"965-973"},"PeriodicalIF":2.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10722855","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Capacitively Coupled Near-Threshold Biasing: Low-Power Design Based on Metal Oxide TFTs for IoT Applications","authors":"Yixin Fu;Zhixuan Wang;Shuai Yuan;Shengdong Zhang;Yudi Zhao;Junchen Dong;Kai Zhao","doi":"10.1109/JEDS.2024.3480269","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3480269","url":null,"abstract":"Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"956-964"},"PeriodicalIF":2.0,"publicationDate":"2024-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10716537","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Subthreshold Kink Effect in Gate-All-Around MOSFETs Based on Void Embedded Silicon on Insulator Technology","authors":"Yuxin Liu;Qiang Liu;Jin Chen;Zhiqiang Mu;Xing Wei;Wenjie Yu","doi":"10.1109/JEDS.2024.3478750","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3478750","url":null,"abstract":"The kink effect of gate-all-around (GAA) MOSFET has been experimentally validated by our GAA devices fabricated on a void embedded silicon-on-insulator (VESOI) substrate. In this VESOI GAA device, a consistent and favorable decrease in subthreshold swing (SS) is observed as \u0000<inline-formula> <tex-math>$V_{mathrm { d}}$ </tex-math></inline-formula>\u0000 increases, which has rarely been reported in devices with other gate structures. In particular, the SS of the device reaches the minimum ~0.1mV/dec with no discernable hysteresis window at \u0000<inline-formula> <tex-math>$V_{mathrm { d}} {=} 4.5$ </tex-math></inline-formula>\u0000V under ambient condition. Further device simulation strongly confirms the unique role of the GAA controllability over the hysteresis-free kink process. These findings contribute to a better understanding of kink behaviors within GAA device for potential application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"941-947"},"PeriodicalIF":2.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10714381","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs","authors":"Zhanhang Chen;Haoliang Shan;Ziyi Ding;Xia Wu;Xiaolin Cen;Xiaoyu Ma;Wanling Deng;Junkai Huang","doi":"10.1109/JEDS.2024.3477928","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3477928","url":null,"abstract":"A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"948-955"},"PeriodicalIF":2.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10713252","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Magaly Ramírez-Como;Monica M. Valdez-Mata;Angel Sacramento;José L. Casas-Espínola;Luis Reséndiz;Lluis F. Marsal
{"title":"Utilization of Graphite Nanoparticles as a Hybrid Hole Transport Layer in Non-Fullerene Organic Solar Cells","authors":"Magaly Ramírez-Como;Monica M. Valdez-Mata;Angel Sacramento;José L. Casas-Espínola;Luis Reséndiz;Lluis F. Marsal","doi":"10.1109/JEDS.2024.3475513","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3475513","url":null,"abstract":"This study investigates the impact of incorporating graphite nanoparticles (GNPs) into poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) as hybrid hole transport layer (HTL) in non-fullerene organic solar cells (NF-OSCs) based on PBDB-T-2F:BTP-4CL. The concentration of GNPs in the PEDOT:PSS layer was varied to investigate their impact on the overall device behavior. The PCE initially increased with the GNPs concentration up to 5% v/v, reaching a maximum enhancement of 6.43%, which was attributed to the increased JSC. Current-voltage measurements and Mott-Schottky analysis through capacitance-voltage characteristics were conducted to evaluate the behavior of the charge recombination and built-in potential due to the concentration variation of the GNPs into PEDOT:PSS. This study illustrates the potential of GNPs to improve OSC performance through enhanced light absorption, reduced recombination losses, and improved charge carrier transport, indicating promising prospects for GNPs on interface layers in OSCs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1044-1050"},"PeriodicalIF":2.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10706788","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HEMT Noise Modeling for D Band Low Noise Amplifier Design","authors":"Ao Zhang;Jianjun Gao","doi":"10.1109/JEDS.2024.3475289","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3475289","url":null,"abstract":"An improved EEHEMT nonlinear model with noise model has been developed in this paper. Empirical formulas of bias dependent noise model parameters are given. A four-stage 120–160 GHz monolithic low-noise amplifier (LNA) fabricated with the 70nm InAlAs/InGaAs/InP HEMT technology. The simulated results of S-parameters and noise figure show the good agreement with measured data to verify the accuracy of the proposed model.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"928-933"},"PeriodicalIF":2.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10706073","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Physics-Based Compact DC Model for AOS TFTs Considering Effects of Active Layer Thickness Variation","authors":"Minxi Cai;Wei Zhong;Bei Liu;Piaorong Xu;Jing Cao","doi":"10.1109/JEDS.2024.3474291","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3474291","url":null,"abstract":"A DC model is proposed for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) applicable to various active layer thicknesses. With the back surface potential and its coupling with the front surface potential being considered, an explicit potential solution is developed. Then, the analytical drain current and physical definition of threshold voltage are derived based on a non-chargesheet expression of free charge density. It is verified that in the previous models for AOS TFTs, typically ignoring the back surface potential and the active layer thickness effects could result in obvious deviations in the values of parameters during the characterization of DC performance, especially for scaled devices with low channel thicknesses. By comparing with numerical calculations and experimental data, this model is validated to be more suitable for AOS TFTs with decreased dimensions, which could give more realistic distributions of the density of states in the channel during parameter extraction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"919-927"},"PeriodicalIF":2.0,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10705102","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142442958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Prediction of Random Telegraph Noise-Induced Threshold Voltage Shift and Its Scaling Dependency Using Machine Learning","authors":"Eunseok Oh;Hyungcheol Shin","doi":"10.1109/JEDS.2024.3471999","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3471999","url":null,"abstract":"Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift in 3D NAND flash memory. Artificial neural network (ANN)-based machine learning (ML) is used for this prediction. With 2000 samples, ANN is trained and tested to predict the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift of random cells with high reliability. Furthermore, ANN is applied to predict the tendency of RTN-induced \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift in scaled 3D NAND. Compared to prior works which has required far more measurements or simulations, the predictions are shown to shorten the time spent to obtain the distribution. Based on these predictions, the dependency of the decay constant on cell variation is investigated, which is a most critical parameter in analyzing the RTN distribution. This indicates that it is possible to apply ANN-based ML to predict various characteristics of 3D NAND flash memory in a much shorter time and to develop numerical models of related parameters.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"934-940"},"PeriodicalIF":2.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim
{"title":"A Process-Aware Analytical Gate Resistance Model for Nanosheet Field-Effect Transistors","authors":"Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim","doi":"10.1109/JEDS.2024.3469917","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3469917","url":null,"abstract":"In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"898-904"},"PeriodicalIF":2.0,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10699326","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142408862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computationally Efficient Band Structure-Based Approach for Accurately Determining Electrostatics and Source-to-Drain Tunneling Current in UTB MOSFETs","authors":"Nalin Vilochan Mishra;Aditya Sankar Medury","doi":"10.1109/JEDS.2024.3469398","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3469398","url":null,"abstract":"The ability of Ultra-Thin-Body (UTB) MOS devices to enable channel length scaling can only be realistically assessed by accurately taking key physical effects such as Quantum Confinement effects (QCEs) and Short channel effects (SCEs) into account. QCEs can accurately be considered only through a full band structure-based approach, which tends to be computationally inefficient, particularly at higher channel thicknesses, and is further exacerbated when required to be used to calculate 2-D channel electrostatics. Therefore, in this work, we propose a methodology to efficiently simulate the channel electrostatics of a UTB Double Gate MOSFET by solving the 1-D band structure with the 2-D Poisson’s equation self consistently, determined by using the \u0000<inline-formula> <tex-math>$sp^{3}d^{5}s^{*}$ </tex-math></inline-formula>\u0000 semi-empirical tight-binding approach only over those k-points that are likely to have a significant effect on the electrostatics. By showing that determining the 1-D Band structure at the source-channel junction is adequate to accurately determine the 2-D channel electrostatics, we show that this approach remains computationally tractable even at higher channel lengths. By following this approach, we obtain the 2-D profile of important device parameters such as electron density and channel potential, which, in turn, enables the determination of the thermionic current density and source-to-drain tunneling current density for a wide range of device parameters using Tsu-Esaki and WKB formalism respectively. Furthermore, the effect of phonon scattering, which is likely to manifest at longer channel lengths, is also incorporated in the drain current calculation, thus making this approach widely applicable.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"881-888"},"PeriodicalIF":2.0,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10697110","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142383489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}