IEEE Journal of the Electron Devices Society最新文献_第3页

Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors 应变工程二维 MoTe2 相变晶闸管的性能和可扩展性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-31 DOI: 10.1109/JEDS.2025.3556316

Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu

{"title":"Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors","authors":"Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu","doi":"10.1109/JEDS.2025.3556316","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556316","url":null,"abstract":"This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math>$leq 0.5$ </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math>$geq 10{^{{5}}}$ </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math>$leq 0.6mu $ </tex-math></inline-formula>m and A<inline-formula> <tex-math>$leq 0.3mu $ </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math>$leq 1.2mu $ </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math>$leq 65{^{text {o}}}$ </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"343-349"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945750","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts 具有源/漏金属触点的ML型和BL型MoS2 GAA NS场效应管的电特性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-29 DOI: 10.1109/JEDS.2025.3575015

Yueh-Ju Chan;Min-Hui Chuang;Yiming Li

{"title":"Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts","authors":"Yueh-Ju Chan;Min-Hui Chuang;Yiming Li","doi":"10.1109/JEDS.2025.3575015","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3575015","url":null,"abstract":"This paper reports source/drain (S/D) contact issues in monolayer and bilayer (BL) <inline-formula> <tex-math>$mathrm {MoS_{2}}$ </tex-math></inline-formula> devices through density-functional-theory (DFT) calculation and device simulation. We begin by analyzing material properties and van der Waals gaps at metal contacts of <inline-formula> <tex-math>$mathrm {MoS_{2}}$ </tex-math></inline-formula> using DFT calculation. These results are then used for device simulation, aligning closely with experimental data. For the first time, the model is extended to 3D gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) simulation, enabling contact resistance <inline-formula> <tex-math>$(R_{C})$ </tex-math></inline-formula> estimation. This work addresses key challenges by reducing computational demands compared to non-equilibrium Green function method and accurately calibrating devices with various metal contacts and gate lengths. Simulations with C-type S/D contacts achieve an <inline-formula> <tex-math>$R_{C}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$89.6~Omega $ </tex-math></inline-formula>-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m in 7-channel GAA BL <inline-formula> <tex-math>$mathrm {MoS_{2}}$ </tex-math></inline-formula> NS FETs, offering an interesting study for 2D material-based devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"485-493"},"PeriodicalIF":2.0,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017515","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144264230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Gamma Ray Irradiation on the Blocking Characteristics of Edge Termination on 4H-SiC and a Novel Anti-Ionizing Radiation Technology 伽玛射线辐照对4H-SiC封边特性的影响及一种新型抗电离辐射技术

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-28 DOI: 10.1109/JEDS.2025.3574497

Chuan-Han Chen;Bing-Yue Tsui;Der-Sheng Chao

引用次数: 0

AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications 多用途阶梯场极板漏极扩展FinFET的ai辅助设计

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-27 DOI: 10.1109/JEDS.2025.3555327

Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu

{"title":"AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications","authors":"Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu","doi":"10.1109/JEDS.2025.3555327","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3555327","url":null,"abstract":"Fin Field-Effect-Transistor (FinFET) has become fundamental components in advanced integrated circuit, while the drain-extended FinFET (DE-FinFET) features a lightly doped drain extension region to improve the device’s breakdown voltage. However, both structural refinement and the optimal integration of various parameters remain limited in achieving comprehensive optimization of device performance. This study introduces a novel DE-FinFET featuring a stepped field plate to improve overall performance of device. Moreover, within an AI-assisted design framework, predictive modeling and multi-objective optimization of the device are accomplished using Kolmogorov–Arnold Networks (KAN) and the Nondominated Sorting Genetic Algorithm (NSGA-III). More importantly, the proposed framework enables efficient device design and performance evaluation, achieving an average prediction accuracy of 98.19% for electrical performance metrics while being over two million times faster than traditional Technology Computer-Aided-Design (TCAD) simulations. In addition, it effectively generates Pareto-optimal solutions, delivering an average improvement of 9.03% across key electrical performance metrics. The proposed novel device of DE-FinFET offers a new route toward tailoring electrical properties. Meanwhile, the methodology of AI-assisted design not only accelerates device design but also enables customizable solutions for multi-purpose applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"326-333"},"PeriodicalIF":2.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10943177","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Non-Linear Partial Differential Equation Solver Based on Analog Memristor Crossbar Arrays 基于模拟忆阻交叉栅阵列的非线性偏微分方程求解器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-26 DOI: 10.1109/JEDS.2025.3573409

Jiabao Ye;Bing Chen;Nuo Xu;Jiantao Zhou;Rongjun Mu;Chao Du;Wei D. Lu

引用次数: 0

Editorial for the J-EDS Special Issue for ESSERC 2024 ESSERC 2024 J-EDS特刊社论

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-21 DOI: 10.1109/JEDS.2025.3547035

Anne S. Verhulst

引用次数: 0

Dynamic Response of Low-Voltage Thin Film Phototransistors Based on DNTT Organic Semiconductor 基于DNTT有机半导体的低压薄膜光电晶体管的动态响应

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-21 DOI: 10.1109/JEDS.2025.3553583

Antonio Vettoliere;Fabio Chiarella;Vincenzo Izzo;Marcello Campajola;Paolo Scotto Di Vettimo;Patrizia Minutolo;Alberto Aloisio;Ettore Sarnelli

{"title":"Dynamic Response of Low-Voltage Thin Film Phototransistors Based on DNTT Organic Semiconductor","authors":"Antonio Vettoliere;Fabio Chiarella;Vincenzo Izzo;Marcello Campajola;Paolo Scotto Di Vettimo;Patrizia Minutolo;Alberto Aloisio;Ettore Sarnelli","doi":"10.1109/JEDS.2025.3553583","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3553583","url":null,"abstract":"We analyzed the dynamic response to the light of organic field-effect transistors in bottom-gate/top-contact configuration. We fabricated Al/Al2O3/SAM/DNTT/Au phototransistors by evaporating thin film layers through shadow masks on flexible PEN (polyethylene naphthalate) substrates. The structure is composed of Al layer as the gate electrode, and Au used both for Source and Drain electrodes. DNTT (Dinaphtho[2,3-b:<inline-formula> <tex-math>$2^{prime }$ </tex-math></inline-formula>,<inline-formula> <tex-math>$3^{prime }$ </tex-math></inline-formula>-f]thieno[3,2-b]thiophene) is the active organic semiconductor layer and Al2O3 is the dielectric material, chosen for the high value of the dielectric constant. SAM (self-assembled monolayer) was used to improve adhesion and interface properties between Al2O3 and DNTT. The transistors, sensitive to blue light, were biased at low-voltage (Vgs and <inline-formula> <tex-math>$mathrm { V_{ds}}$ </tex-math></inline-formula> from 0 to 3.5 V). Devices showed low <inline-formula> <tex-math>$mathrm { I_{gs}}$ </tex-math></inline-formula> leakage currents, of the order of <inline-formula> <tex-math>$5x10^{-10}$ </tex-math></inline-formula> A, and a clear electro-optical response to the light. The maximum responsivity value was about 0.21 A/W in the static regime, while the lowest irradiance producing a measurable response in dynamic regime was <inline-formula> <tex-math>$13~mu $ </tex-math></inline-formula>W/cm2. Fast time components of the rise time of the light response for the analyzed phototransistors, of the order of few hundreds of ms, turned out to be among the fastest reported in literature for Al/AlOx/DNTT/Au organic phototransistor. These preliminary results are encouraging for developing organic phototransistors for visible light communication.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"317-325"},"PeriodicalIF":2.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10937183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power LTPO Scan Driver Circuit Using DC Power Supplied Buffer 一种使用直流电源缓冲器的低功耗LTPO扫描驱动电路

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-19 DOI: 10.1109/JEDS.2025.3571171

SangWoon Lee;JungSuk Oh;HyeongMin Kim;YiKyoung You;Nack-Hyeon Keum;HeeJu Moon;SangHun Kim;KeeChan Park;Hwarim Im

{"title":"A Low-Power LTPO Scan Driver Circuit Using DC Power Supplied Buffer","authors":"SangWoon Lee;JungSuk Oh;HyeongMin Kim;YiKyoung You;Nack-Hyeon Keum;HeeJu Moon;SangHun Kim;KeeChan Park;Hwarim Im","doi":"10.1109/JEDS.2025.3571171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3571171","url":null,"abstract":"This paper proposes a novel low-temperature polycrystalline silicon and oxide (LTPO) scan driver circuit integrating p-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and n-channel metal-oxide (MOx) TFTs. The proposed circuit employs a complementary metal-oxide-semiconductor inverter as an output buffer, allowing low-level voltage to be delivered from a DC power supply to the output node without relying on clock-supplied bootstrapping, which is typically required in most scan driver circuits to drive the output buffer. This design significantly lowers dynamic power consumption by up to 74% by reducing the power consumption due to charging/discharging the parasitic capacitance of the buffer TFT by the clock signals compared with the conventional LTPO scan driver circuits utilizing the clock-supplied bootstrapping method. Additionally, the proposed circuit reduces the positive bias applied to MOx TFTs to alleviate stress conditions effectively. Therefore, the proposed circuit can improve long-term reliability by mitigating the threshold voltage shifts of MOx TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"494-500"},"PeriodicalIF":2.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11006837","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Field-Effect Passivation of GaN-Based Blue Micro-Light-Emitting Diodes gan基蓝色微发光二极管的场效应钝化

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-18 DOI: 10.1109/JEDS.2025.3552171

Woo Jin Baek;Joon Pyo Kim;Song Hyeon Kuk;Juhyuk Park;Hyun Soo Kim;Dae-Myeong Geum;Sang Hyeon Kim

引用次数: 0

Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability 双层InGaSnO和氮掺杂InSnO薄膜晶体管的设计与优化，以提高迁移率和可靠性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-18 DOI: 10.1109/JEDS.2025.3552454

Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan

{"title":"Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability","authors":"Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2025.3552454","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552454","url":null,"abstract":"In this study, high-performance indium gallium tin oxide (IGTO) and nitrogen (N) doped indium tin oxide (ITO) hetero structured bilayer thin-film transistors (TFTs) are prepared by incorporating an N-doped ITO intercalation layer in single-layer IGTO TFTs. The performance of the IGTO/ITO:N bilayer TFTs is significantly improved compared with single-layer IGTO TFTs, with specific indicators including a field-effect mobility of 32.6 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, a subthreshold swing of 201 mV/dec, a threshold voltage shifts of 0.21 V and −0.45 V under ±10 V gate-bias stress. The results show that the performance enhancement is due to the rational design of the bilayer structure, in which the ITO layer functions as a charge-accumulation layer, providing additional electrons. Meanwhile, N doping effectively reduces the oxygen vacancies, thereby decreasing the interfacial trap density, and ultimately enhancing the performance of single-layer IGTO TFTs. Through X-ray photoelectron spectroscopy and low-frequency noise analyses, we further confirmed the positive effects of N doping and bilayer structure on reducing the defective states and enhancing the stability of TFTs. Overall, the strategy presented here is effective for preparing high performance oxide TFTs for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"290-296"},"PeriodicalIF":2.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0