Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin
{"title":"Cryogenic InP HEMTs With Enhanced fmax and Reduced On-Resistance Using Double Recess","authors":"Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin","doi":"10.1109/JEDS.2025.3557432","DOIUrl":null,"url":null,"abstract":"Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device’s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device’s RON is <inline-formula> <tex-math>$410~\\Omega \\cdot \\mu $ </tex-math></inline-formula>m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device’s maximum oscillation frequency(<inline-formula> <tex-math>$f_{\\max }$ </tex-math></inline-formula>) by reducing the parasitic capacitance. At 7 K, the device’s <inline-formula> <tex-math>$f_{\\max }$ </tex-math></inline-formula> reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the <inline-formula> <tex-math>$\\rm Si_{3}N_{4}$ </tex-math></inline-formula> passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device’s cryogenic performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"366-372"},"PeriodicalIF":2.0000,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10948522","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10948522/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device’s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device’s RON is $410~\Omega \cdot \mu $ m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device’s maximum oscillation frequency($f_{\max }$ ) by reducing the parasitic capacitance. At 7 K, the device’s $f_{\max }$ reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the $\rm Si_{3}N_{4}$ passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device’s cryogenic performance.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.