IEEE Journal of the Electron Devices Society最新文献_第4页

Investigation of the DC Performance and Linearity of InAlN/GaN HFETs via Studying the Impact of the Scaling of LGS and LG on the Source Access Resistance 通过研究 LGS 和 LG 的缩放对源接入电阻的影响考察 InAlN/GaN HFET 的直流性能和线性度

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-07-15 DOI: 10.1109/JEDS.2024.3428969

Yatexu Patel;Pouya Valizadeh

{"title":"Investigation of the DC Performance and Linearity of InAlN/GaN HFETs via Studying the Impact of the Scaling of LGS and LG on the Source Access Resistance","authors":"Yatexu Patel;Pouya Valizadeh","doi":"10.1109/JEDS.2024.3428969","DOIUrl":"10.1109/JEDS.2024.3428969","url":null,"abstract":"In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the output characterises and gate-transconductance (Gm) linearity of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. Evidence for both device types suggests that the downscaling of LGS and LG augments the electron velocity in the source-access region, as a result of which the higher carrier density under the gated-channel improves the maximum drain-current density but not necessarily the \u0000<inline-formula> <tex-math>$G_{m}$ </tex-math></inline-formula>\u0000 linearity of the device. It is shown that the devices having a planar and longer source access region are exhibiting relatively improved gate-transconductance linearity. This is suggested to be due to their almost constant source access resistance (Rs). In addition, the downscaling of the LG is observed to have a positive influence on device linearity. This observation could be due to the larger exposure to the drain-induced barrier lowering (DIBL) and the resulting rush of the carriers from the source access region to the gated-channel, leading to the suppression of the increasing \u0000<inline-formula> <tex-math>$R_{s}$ </tex-math></inline-formula>\u0000 at higher drain currents.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10599155","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141718883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Bridging the Data Gap in Photovoltaics with Synthetic Data Generation 通过合成数据生成弥补光伏领域的数据差距

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-07-11 DOI: 10.1109/JEDS.2024.3425989

引用次数: 0

Study of Highly Stable Nitrogen-Doped a-InGaSnO Thin-Film Transistors 高稳定氮掺杂 a-InGaSnO 薄膜晶体管的研究

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-07-05 DOI: 10.1109/JEDS.2024.3424545

Wenyang Zhang;Li Lu;Chenfei Li;Weijie Jiang;Wenzhao Wang;Xingqiang Liu;Ablat Abliz;Da Wan

{"title":"Study of Highly Stable Nitrogen-Doped a-InGaSnO Thin-Film Transistors","authors":"Wenyang Zhang;Li Lu;Chenfei Li;Weijie Jiang;Wenzhao Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2024.3424545","DOIUrl":"10.1109/JEDS.2024.3424545","url":null,"abstract":"Herein, highly stable nitrogen (N) doped amorphous indium gallium tin oxide (a-IGTO) thinfilm transistors (TFTs) are prepared and the effects of N-doping are investigated. Compared with undoped a-IGTO TFTs, a-IGTO TFTs with 6 min N plasma treatment exhibit superior bias stress stability and a threshold voltages (\u0000<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>\u0000) closer to 0 V with almost no decline in mobility. In particular, the positive/negative bias stress threshold shift of N-doped a-IGTO TFTs is substantially reduced in both dark and light environment. The X-ray photoelectron spectroscopy analysis (XPS) and low frequency noise (LFN) are employed to study the mechanism of N-doping in a-IGTO TFTs. The XPS results indicate that appropriate amount of N-doping could enhance the bias stress stability and control the \u0000<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>\u0000 efficiently by passivating the defects such as oxygen vacancy in a-IGTO films. The LFN results illustrate that the average interfacial trap density could be reduced by N-doping. Overall, the strategy presented here is effective for preparing a-IGTO TFTs with enhanced stability for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10587190","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141572389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Directly Fabricated Flexible Photodetector Based on TiO₂-Doped Carbon Nanosheets Film 基于掺杂 TiO2 的碳纳米片薄膜的直接制备柔性光电探测器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-07-02 DOI: 10.1109/JEDS.2024.3422292

Yunlong Zhang;Xiaolin Li;Zhipeng Cao;Qiang Wu;Gong Chen;Bo Wen;Dongfeng Diao;Xi Zhang

{"title":"Directly Fabricated Flexible Photodetector Based on TiO₂-Doped Carbon Nanosheets Film","authors":"Yunlong Zhang;Xiaolin Li;Zhipeng Cao;Qiang Wu;Gong Chen;Bo Wen;Dongfeng Diao;Xi Zhang","doi":"10.1109/JEDS.2024.3422292","DOIUrl":"10.1109/JEDS.2024.3422292","url":null,"abstract":"Flexible photodetector is crucial for the intelligent industrial applications. However, the optical-sensitive materials are usually grown in a high temperature and then transferred onto the flexible substrate. This paper reported a directly fabricated flexible photodetector based on TiO2-doped Graphene Nanosheets Embedded Carbon (GNEC)film. An Electron Cyclotron Resonance (ECR) system was employed to in-situ deposit TiO2-doped GNEC film on a polyimide substrate, which were subsequently sensitized with N719 dye to fabricate the TiO2@GNEC photodetector. The GNEC film contains vertically aligned Graphene Nanosheets (GNs), which exhibit high-density edge states. The edge states suppress the recombination rate of photo-generated electron-hole pairs, thereby significantly enhancing the photo-responsive performance. The photodetector demonstrates a high photo responsivity of 0.82 mA/W and a response time of 1.93 seconds. Due to the in-situ manufacturing capabilities of the ECR system, which avoids defects from secondary material transfers, the photodetector array exhibits excellent consistency and achieves clear recognition of light patterns in both flat and bent states.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10580991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Piezotronic N+ -ITO/P-NiO/N-ZnO Heterojunction Thin-Film Diode as a Flexible Energy Scavenger 作为柔性能量清除器的压电 N+-ITO/P-NiO/N-ZnO 异质结薄膜二极管

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-07-01 DOI: 10.1109/JEDS.2024.3421612

Shuxin Lin;Emad Iranmanesh;Lin Zhao;Weiwei Li;Haris Doumanidis;Hang Zhou;Kai Wang

{"title":"Piezotronic N+ -ITO/P-NiO/N-ZnO Heterojunction Thin-Film Diode as a Flexible Energy Scavenger","authors":"Shuxin Lin;Emad Iranmanesh;Lin Zhao;Weiwei Li;Haris Doumanidis;Hang Zhou;Kai Wang","doi":"10.1109/JEDS.2024.3421612","DOIUrl":"10.1109/JEDS.2024.3421612","url":null,"abstract":"This paper reports on an all-oxide thin film piezotronic P-N heterojunction diode incorporating vertically-stacked structure of N+-ITO/P-type nickel oxide/N-type zinc oxide as a flexible energy scavenger and its diode characteristics on signal regulation which simplifies an essential element for harvesting which is signal rectification circuitry. An energy band diagram, theoretical modeling and equivalent small-signal circuit elaborate its working principle and device physics. Signal amplification due to introduction of in-series capacitances related to junction formation has also been addressed. A preliminary experimental study demonstrates applicability of such a flexible energy scavenger in various gratis non-stop thrusts originating from human body motions such as: simple tapping (as in typing) and walking actions for generating \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 W-range power. Moreover, focusing on a simple power management system along with analysis of voltage waveforms in response to both resistive and capacitive loads unveils that the device is capable of quickly charging a capacitor and discharging it slowly allowing for possible energy storage. The estimation on generated power by a pixelated array that is obtainable due to ease of large-area fabrication processes and a single-pixel strip-based device exabits its feasibility as an energy source to power up some IoT nodes.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A New 13T4C LTPO MicroLED Pixel Circuit Producing Highly Stable Driving Current by Minimizing Effect of Parasitic Capacitors and Stabilizing Capacitor Nodes 一种新型 13T4C LTPO MicroLED 像素电路，通过最小化寄生电容和稳定电容节点的影响产生高度稳定的驱动电流

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-24 DOI: 10.1109/JEDS.2024.3417994

Ji-Hwan Park;Kyeong-Soo Kang;Chanjin Park;Soo-Yeon Lee

{"title":"A New 13T4C LTPO MicroLED Pixel Circuit Producing Highly Stable Driving Current by Minimizing Effect of Parasitic Capacitors and Stabilizing Capacitor Nodes","authors":"Ji-Hwan Park;Kyeong-Soo Kang;Chanjin Park;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3417994","DOIUrl":"10.1109/JEDS.2024.3417994","url":null,"abstract":"In this paper, we proposed a new low-temperature polycrystalline oxide (LTPO) thin-film transistor (TFT) pixel circuit for micro light-emitting diode (μ LED) displays that produces a highly stable and uniform driving current. The proposed pixel circuit suppresses the current level change along with the sweep signal due to the parasitic capacitances and compensates for the TFT's threshold voltage (VTH) variation-induced current error, including even falling shape. In addition, the proposed circuit produces a constant current regardless of the data voltage. As a result, a relative current error rate of less than 2% was achieved across all gray levels under the ±0.5 V VTH fluctuation. The proposed circuit was verified using HSPICE with a low-temperature polycrystalline silicon (LTPS) TFT and amorphous indium-galliumzinc- oxide (a-IGZO) TFT model based on the measured data. The simulation analysis confirmed that the optimal sweep signal input position and pulse width modulation (PWM) and constant current generation (CCG) parts connecting method were key design points for stable and uniform performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141608753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time 通过即时上下文切换和延长功率门控时间实现低功耗神经网络处理的 3-D 存储器系统

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-24 DOI: 10.1109/JEDS.2024.3418036

Kouhei Toyotaka;Yuto Yakubo;Kazuma Furutani;Haruki Katagiri;Masashi Fujita;Yoshinori Ando;Toru Nakura;Shunpei Yamazaki

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Effective Reduction of Hydrogen Diffusion and Reliability Degradation in Peripheral Transistor of Peripheral-Under-Cell (PUC) NAND Flash Memory 有效减少外设单元下 (PUC) NAND 闪存外设晶体管中的氢扩散和可靠性退化

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-24 DOI: 10.1109/JEDS.2024.3418212

Eunyoung Park;Hyun-Yong Yu

{"title":"Effective Reduction of Hydrogen Diffusion and Reliability Degradation in Peripheral Transistor of Peripheral-Under-Cell (PUC) NAND Flash Memory","authors":"Eunyoung Park;Hyun-Yong Yu","doi":"10.1109/JEDS.2024.3418212","DOIUrl":"10.1109/JEDS.2024.3418212","url":null,"abstract":"Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that excess hydrogen is injected into the peripheral transistor, resulting in degradation of reliability. Therefore, we propose the hydrogen diffusion model in PUC to investigate the degradation of peripheral transistor by excess hydrogen using Sentaurus 3D technology Computer-Aided Design (TCAD) and suggest an optimal process to improve reliability. As a result, by applying the bonding process and adjusting the cell alloy process sequence, the amount of excess hydrogen injection is reduced by 87% and the NBTI lifetime showed about 8.3 times greater result and TDDB breakdown time improved more than 9.1 times compared to the PUC structure made through a sequential process. Additionally, this process effectively alleviates excess hydrogen injection in the NAND cell with an increased number of WL. These results could provide critical insight for designing a PUC that ensures the reliability of peripheral transistor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568956","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation 大规模训练神经紧凑模型，实现准确、适应性强的 MOSFET 仿真

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-20 DOI: 10.1109/JEDS.2024.3417521

Chanwoo Park;Seungjun Lee;Junghwan Park;Kyungjin Rim;Jihun Park;Seonggook Cho;Jongwook Jeon;Hyunbo Cho

{"title":"Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation","authors":"Chanwoo Park;Seungjun Lee;Junghwan Park;Kyungjin Rim;Jihun Park;Seonggook Cho;Jongwook Jeon;Hyunbo Cho","doi":"10.1109/JEDS.2024.3417521","DOIUrl":"10.1109/JEDS.2024.3417521","url":null,"abstract":"We address the challenges associated with traditional analytical models, such as BSIM, in semiconductor device modeling. These models often face limitations in accurately representing the complex behaviors of miniaturized devices. As an alternative, Neural Compact Models (NCMs) offer improved modeling capabilities, but their effectiveness is constrained by a reliance on extensive datasets for accurate performance. In real-world scenarios, where measurements for device modeling are often limited, this dependence becomes a significant hindrance. In response, this work presents a large-scale pre-training approach for NCMs. By utilizing extensive datasets across various technology nodes, our method enables NCMs to develop a more detailed understanding of device behavior, thereby enhancing the accuracy and adaptability of MOSFET device simulations, particularly when data availability is limited. Our study illustrates the potential benefits of large-scale pre-training in enhancing the capabilities of NCMs, offering a practical solution to one of the key challenges in current device modeling practices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566861","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection 在铁电 FinFET 跨栅上高效实现马哈拉诺比斯距离以检测离群点

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-19 DOI: 10.1109/JEDS.2024.3416441

Musaib Rafiq;Yogesh Singh Chauhan;Shubham Sahay

{"title":"Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection","authors":"Musaib Rafiq;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/JEDS.2024.3416441","DOIUrl":"10.1109/JEDS.2024.3416441","url":null,"abstract":"The developments in the nascent field of artificial-intelligence-of-things (AIoT) relies heavily on the availability of high-quality multi-dimensional data. A huge amount of data is being collected in this era of big data, predominantly for AI/ML algorithms and emerging applications. Considering such voluminous quantities, the collected data may contain a substantial number of outliers which must be detected before utilizing them for data mining or computations. Therefore, outlier detection techniques such as Mahalanobis distance computation have gained significant popularity recently. Mahalanobis distance, the multivariate equivalent of the Euclidean distance, is used to detect the outliers in the correlated data accurately and finds widespread application in fault identification, data clustering, singleclass classification, information security, data mining, etc. However, traditional CMOS-based approaches to compute Mahalanobis distance are bulky and consume a huge amount of energy. Therefore, there is an urgent need for a compact and energy-efficient implementation of an outlier detection technique which may be deployed on AIoT primitives, including wireless sensor nodes for in-situ outlier detection and generation of high-quality data. To this end, in this paper, for the first time, we have proposed an efficient Ferroelectric FinFET-based implementation for detecting outliers in correlated multivariate data using Mahalanobis distance. The proposed implementation utilizes two crossbar arrays of ferroelectric FinFETs to calculate the Mahalanobis distance and detect outliers in the popular Wisconsin breast cancer dataset using a novel inverter-based threshold circuit. Our implementation exhibits an accuracy of 94.1% which is comparable to the software implementations while consuming a significantly low energy (27.2 pJ).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10563982","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0