IEEE Journal of the Electron Devices Society最新文献_第4页

Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability 双层InGaSnO和氮掺杂InSnO薄膜晶体管的设计与优化，以提高迁移率和可靠性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-18 DOI: 10.1109/JEDS.2025.3552454

Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan

{"title":"Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability","authors":"Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2025.3552454","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552454","url":null,"abstract":"In this study, high-performance indium gallium tin oxide (IGTO) and nitrogen (N) doped indium tin oxide (ITO) hetero structured bilayer thin-film transistors (TFTs) are prepared by incorporating an N-doped ITO intercalation layer in single-layer IGTO TFTs. The performance of the IGTO/ITO:N bilayer TFTs is significantly improved compared with single-layer IGTO TFTs, with specific indicators including a field-effect mobility of 32.6 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, a subthreshold swing of 201 mV/dec, a threshold voltage shifts of 0.21 V and −0.45 V under ±10 V gate-bias stress. The results show that the performance enhancement is due to the rational design of the bilayer structure, in which the ITO layer functions as a charge-accumulation layer, providing additional electrons. Meanwhile, N doping effectively reduces the oxygen vacancies, thereby decreasing the interfacial trap density, and ultimately enhancing the performance of single-layer IGTO TFTs. Through X-ray photoelectron spectroscopy and low-frequency noise analyses, we further confirmed the positive effects of N doping and bilayer structure on reducing the defective states and enhancing the stability of TFTs. Overall, the strategy presented here is effective for preparing high performance oxide TFTs for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"290-296"},"PeriodicalIF":2.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of the Schottky Barrier Height on the Carrier Velocity Overshoot Behaviors in SOI nMOSFETs With Metal Source/Drain 肖特基势垒高度对金属源漏型SOI nmosfet载流子速度超调行为的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-15 DOI: 10.1109/JEDS.2025.3569242

Rui Su;Yan Jing;Xinyi Zhang;Yi Jiang;Dawei Gao;Walter Schwarzenbach;Bich-Yen Nguyen;Junkang Li;John Robertson;Rui Zhang

引用次数: 0

High Power Added Efficiency Enhancement-Mode Γ-Gate RF HEMT With High/Low p-GaN Doping Profile 高功率附加效率增强模式Γ-Gate高/低p-GaN掺杂的RF HEMT

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-14 DOI: 10.1109/JEDS.2025.3551313

Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin

{"title":"High Power Added Efficiency Enhancement-Mode Γ-Gate RF HEMT With High/Low p-GaN Doping Profile","authors":"Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin","doi":"10.1109/JEDS.2025.3551313","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3551313","url":null,"abstract":"<inline-formula> <tex-math>$0.5~mu $ </tex-math></inline-formula>m enhancement-mode (E-mode) p-GaN <inline-formula> <tex-math>$Gamma $ </tex-math></inline-formula>-gate RF HEMT with engineered Mg doping profile in p-GaN layer was studied for high power amplifier application. With high/low Mg doping profile design in p-GaN, the traditional Ti/p-GaN Schottky gate behavior can be transformed to ohmic-gate after 550°C 3 minutes post-gate annealing. The ohmic-gate design of p-GaN HEMT can minimize poole-frenkel (PF) emission thus the flicker noise and current collapse (C.C) can be improved. A better gate-to-channel modulation ability is also obtained due to precipitous C-VG curve of low Mg (<inline-formula> <tex-math>$1times 10{^{{19}}}$ </tex-math></inline-formula>cm-3) doping concentration p-GaN layer. The fabricated device achieves a threshold voltage (VTH) of +1.1 V, and shows a low on-resistance (RON) of <inline-formula> <tex-math>$1.8~Omega cdot $ </tex-math></inline-formula>mm and an off-state breakdown voltage of 206 V. With the engineered Mg doping profile design, a 70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"285-289"},"PeriodicalIF":2.0,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10926554","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimize Gate-All-Around Devices Using Wide Neural Network-Enhanced Bayesian Optimization 基于广义神经网络增强贝叶斯优化的全门器件优化

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-13 DOI: 10.1109/JEDS.2025.3569528

Jiaye Shen;Zhiqiang Li;Zhenjie Yao

{"title":"Optimize Gate-All-Around Devices Using Wide Neural Network-Enhanced Bayesian Optimization","authors":"Jiaye Shen;Zhiqiang Li;Zhenjie Yao","doi":"10.1109/JEDS.2025.3569528","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3569528","url":null,"abstract":"Device design processes based on manual design experience require numerous experiments and simulations. As transistors continue to shrink, complex physical effects, such as quantum effects intensify, making the design process increasingly costly, whether based on experiments or technology computer-assisted design (TCAD) simulations. To reduce the experimental and simulation resources consumed during the design process, we propose a device optimization framework based on neural network-enhanced Bayesian Optimization (BO). We target two Figures of Merit (FoMs) of Nanowire field-effect transistor (NWFET) devices as optimization objectives: subthreshold swing (SS) and on-state current (Ion). By improving the neural network to better fit the nonlinear mapping between the objective functions and input parameters, we effectively optimize device parameters while reducing the number of TCAD simulations. Experimental results show that compared to Bayesian optimization frameworks based on Gaussian Process (GP), Random Forest (RF) and Deep Networks for Global Optimization (DNGO), our neural network-based Bayesian optimization framework reduced the number of iterations by 19.3%, 42.7% and 60.3%, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"456-463"},"PeriodicalIF":2.0,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11003089","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology 14nm FinFET技术锁相环电路老化分析及退化预测

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-11 DOI: 10.1109/JEDS.2025.3549754

Meng Li;Xin Xu;Xianghui Li;Yunpeng Li;Yiqun Shi;Qingqing Sun;Hao Zhu

{"title":"Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology","authors":"Meng Li;Xin Xu;Xianghui Li;Yunpeng Li;Yiqun Shi;Qingqing Sun;Hao Zhu","doi":"10.1109/JEDS.2025.3549754","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549754","url":null,"abstract":"This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"270-277"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918946","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hot Carrier Degradation in Si n-MOSFETs at Cryogenic Temperatures 低温下Si - n- mosfet的热载流子降解

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-11 DOI: 10.1109/JEDS.2025.3550268

Shunsuke Shitakata;Hiroshi Oka;Kimihiko Kato;Takumi Inaba;Shota Iizuka;Hidehiro Asai;Takahiro Mori

引用次数: 0

Enhancement of Near-Infrared Sensitivity in Silicon-Based Image Sensors to Oblique Chief Rays via Quasi-Surface Plasmon Resonance 准表面等离子体共振增强硅基图像传感器对斜主射线的近红外灵敏度

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-10 DOI: 10.1109/JEDS.2025.3549721

Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono

{"title":"Enhancement of Near-Infrared Sensitivity in Silicon-Based Image Sensors to Oblique Chief Rays via Quasi-Surface Plasmon Resonance","authors":"Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono","doi":"10.1109/JEDS.2025.3549721","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549721","url":null,"abstract":"A silicon-based image sensor is proposed, incorporating plasmonic diffraction gratings tailored to chief ray angles (CRAs), to enhance near-infrared (NIR) sensitivity improvement over a broad range of incident angles. Under quasi-surface plasmon resonance (quasi-SPR) conditions, the metal grating efficiently diffracted incident light into the silicon absorption layer. The period and width of the metal grating were adjusted at each pixel position according to CRAs, thereby improving the NIR sensitivity at sensor edges. The plasmonically diffracted light with angled chief ray was confined within the pixel photodiode. The photon confinement resulted in a significant improvement in absorption of approximately 37% or more, within an incident angle range of 30 degrees at a NIR wavelength of 940 nm and a silicon thickness of 3 μm. The improvement in NIR absorption over a broad incident angle range enhances the sensitivity of the entire sensor chip, representing a significant advancement for NIR cameras.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"278-284"},"PeriodicalIF":2.0,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918731","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs 了解Si - n- finet在交流正偏置温度不稳定应力下产生陷阱的频率依赖性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-09 DOI: 10.1109/JEDS.2025.3567049

Yunfei Shi;Hao Chang;Hong Yang;Qiangzhu Zhang;Qianqian Liu;Bo Tang;Longda Zhou;Zhigang Ji;Junjie Li;Xiaobin He;Junfeng Li;Huaxiang Yin;Xiaolei Wang;Jun Luo;Wenwu Wang

{"title":"Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs","authors":"Yunfei Shi;Hao Chang;Hong Yang;Qiangzhu Zhang;Qianqian Liu;Bo Tang;Longda Zhou;Zhigang Ji;Junjie Li;Xiaobin He;Junfeng Li;Huaxiang Yin;Xiaolei Wang;Jun Luo;Wenwu Wang","doi":"10.1109/JEDS.2025.3567049","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3567049","url":null,"abstract":"In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and the discharging-based multi-pulse energy profiling (DMP) technique. The experimental results show that both interface trap generation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NIT) and bulk trap generation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NOT) of n-FinFET under AC PBTI stress are almost independent of the AC frequency. However, further analysis shows that <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NOT consists of shallow traps near EC of Si and deep traps near Ev of Si. Moreover, about 22% of deep traps decrease with shallow traps increasing under 1.4V overdrive voltage (Vov) at 125°C with AC bias frequency increasing from 10 Hz to 1 MHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"450-455"},"PeriodicalIF":2.0,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10994476","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Characteristics Enhancement of Drain-Extended FinFETs for System on Chip Applications With Dual High-k Field Plates 双高k场极板用于片上系统应用的漏极扩展finfet的热特性增强

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-06 DOI: 10.1109/JEDS.2025.3548595

Yeonsil Yang;Jongmin Lee;Jang Hyun Kim

{"title":"Thermal Characteristics Enhancement of Drain-Extended FinFETs for System on Chip Applications With Dual High-k Field Plates","authors":"Yeonsil Yang;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2025.3548595","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548595","url":null,"abstract":"In this paper, we analyze the electrical and thermal characteristics through Drain-Extended Fin Field-effect Transistor (DeFinFET) using separated high-k field plates. In this article, we first compare the structure using silicon dioxide (SiO2) as the field plate near the drain with that using aluminum oxide (Al2O3). The maximum lattice temperature (<inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula>) in the hafnium oxide (HfO2)/SiO2 structure is 391.953 K under the same current condition, whereas <inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula> is reduced to 360.941 K in the HfO2/Al2O3 structure, indicating improved thermal management. Similarly, the thermal resistance <inline-formula> <tex-math>$(R_th)$ </tex-math></inline-formula> is reduced by 8.73% in the Al2O3 based structure, indicating improved thermal characteristics. Heat flux analysis results show that 60.1% of the generated heat is dissipated through the extended drain region, which identifies the heat dissipation path of the device. And when the length of the Al2O3 field plate in the HfO2/Al2O3 structure was changed to 20 nm, 40 nm, 60 nm, and 80 nm, the <inline-formula> <tex-math>$R_{mathrm{th}}$ </tex-math></inline-formula> of the 80 nm configuration was found to achieve the best thermal performance with a thermal resistance of 217.091 μm · K/mW. In addition, in this structure, the drain current reduction rate due to SHE was the lowest at 12.1%, and excellent breakdown voltage <inline-formula> <tex-math>$(V_{mathrm{BD}})$ </tex-math></inline-formula> was derived because the electric field was not concentrated at the field plate junction near the drain. Consequently, the proposed device has potential application to high voltage (HV) System on Chip (SoC).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"182-188"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915199","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection 半导体制造环境中基于ESD事件检测芯片的ESD实时监测与控制

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-06 DOI: 10.1109/JEDS.2025.3548886

Chang-Jiun Lai;Ming-Dou Ker

{"title":"Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection","authors":"Chang-Jiun Lai;Ming-Dou Ker","doi":"10.1109/JEDS.2025.3548886","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548886","url":null,"abstract":"Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"252-262"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0