IEEE Journal of the Electron Devices Society最新文献_第4页

Reliability of Gap-Type Thin Film Transistors Under Low Illumination for Imaging Sensing Applications 低照度下成像传感用间隙型薄膜晶体管的可靠性研究

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-11 DOI: 10.1109/JEDS.2025.3578547

Ya-Hsiang Tai;Chih-Chung Tu;Chi-Hao Lin;Chi-Fan Lu

{"title":"Reliability of Gap-Type Thin Film Transistors Under Low Illumination for Imaging Sensing Applications","authors":"Ya-Hsiang Tai;Chih-Chung Tu;Chi-Hao Lin;Chi-Fan Lu","doi":"10.1109/JEDS.2025.3578547","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3578547","url":null,"abstract":"In large-area image sensing applications, such as under-display fingerprint sensors, amorphous silicon (a-Si) gap-type thin-film transistors (TFTs) are favored due to their simple fabrication process and high sensing current. These applications typically involve device operation under low-light illumination conditions. Despite these advantages, the recovery behavior of performance parameters after exposure to stress factors, including bias stress and photo-stress, has not been comprehensively explored, particularly in relation to reliability recovery. This study systematically investigates the impact of fixed-bias and pulsed-stress operations under low-light conditions. The experimental findings are further analyzed using Technology Computer-Aided Design (TCAD) simulations to elucidate the underlying mechanisms. Results indicate that long-term bias stress induces significant variations in the photocurrent characteristics of the devices. However, the introduction of pulsed operations in sensing applications markedly enhances the operational lifetime of the devices, offering a promising pathway to improving their reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"524-531"},"PeriodicalIF":2.0,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11030751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Erratum to “Charge-Based Compact Modeling of OECTs for Neuromorphic Applications” “神经形态应用中基于电荷的oect紧凑建模”的勘误表

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-10 DOI: 10.1109/JEDS.2025.3572172

Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes

引用次数: 0

IEEE ELECTRON DEVICES SOCIETY 电子器件学会

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-05 DOI: 10.1109/JEDS.2025.3576507

引用次数: 0

Enabling Selective and Tunable Weight Updates in All-InGaZnO 3-Transistor 1-Capacitor Synaptic Circuits for On-Chip Training 在All-InGaZnO 3-晶体管1-电容突触电路中实现选择性和可调谐的权重更新，用于片上训练

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-05 DOI: 10.1109/JEDS.2025.3576795

Minseung Kang;Mingi Kim;Jaehyeon Kang;Jongun Won;Hyeong Jun Seo;Changhoon Joe;Youngchae Roh;Yeaji Park;Sangbum Kim

{"title":"Enabling Selective and Tunable Weight Updates in All-InGaZnO 3-Transistor 1-Capacitor Synaptic Circuits for On-Chip Training","authors":"Minseung Kang;Mingi Kim;Jaehyeon Kang;Jongun Won;Hyeong Jun Seo;Changhoon Joe;Youngchae Roh;Yeaji Park;Sangbum Kim","doi":"10.1109/JEDS.2025.3576795","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3576795","url":null,"abstract":"Capacitor-based analog synaptic circuit arrays proposed so far typically required more than three transistors per synapse to enable selective updates for parallel backpropagation updates. For the first time, an innovative update scheme that enables selective updating without requiring additional transistors is demonstrated. This approach is experimentally validated through an all-InGaZnO (IGZO) thin-film transistor (TFT) 3-transistor 1-capacitor (3T1C) synaptic circuit. IGZO TFTs are specifically chosen for their ability to extend retention times due to extremely low leakage currents and their simplified fabrication processes at low temperatures. Fundamental synaptic operations, including controllable weight updates, long data retention, and stable programming endurance, are confirmed experimentally. Additionally, optimizing operational voltage conditions improves weight update behavior, which enhances network training performance. System-level analysis using a neural network hardware simulator with a derived weight update model demonstrates high training accuracy on the MNIST handwritten digit dataset and achieves maximum accuracy over 98%. With the proposed selection method and tunable weight updates, 3T1C synaptic circuit is a promising candidate for scalable large-scale deep neural network accelerators based on analog compute-in-memory technology.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"510-515"},"PeriodicalIF":2.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11026025","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144367074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fault Tolerance of Oscillatory Neural Network: Device Oscillator-Based Small Network to Digital Oscillator-Based Large Networks 振荡神经网络的容错：基于器件振荡器的小网络到基于数字振荡器的大网络

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-04 DOI: 10.1109/JEDS.2025.3576359

Sai Shubham;Nikhilesh Myanapuri;Siddharth Mohanty;Sandip Lashkare

{"title":"Fault Tolerance of Oscillatory Neural Network: Device Oscillator-Based Small Network to Digital Oscillator-Based Large Networks","authors":"Sai Shubham;Nikhilesh Myanapuri;Siddharth Mohanty;Sandip Lashkare","doi":"10.1109/JEDS.2025.3576359","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3576359","url":null,"abstract":"Oscillatory Neural Networks (ONN) are inevitable when it comes to solving combinatorial optimization problems. ONNs are also extremely energy efficient for AI workloads compared to conventional Deep Neural Networks (DNNs). Analysis of fault and failure tolerance of ONNs is crucial for understanding the reliability of the networks. This work illustrates the fault tolerance of the ONN in solving constraint optimization problems such as vertex coloring and digit recognition problems. For vertex coloring, a 4-node network across various configurations and different component failure levels has been analyzed using a device oscillator. The findings confirm that the network is highly robust to failures, demonstrating tolerance to variations in resistance of up to 40% and in capacitance of up to 60%. The analysis was then extended to bigger networks varying from 16-node network to 784-node network, using a digital oscillator for digit recognition of digits 0, 1, and 7. The results suggest that the tolerance shoots up rapidly as the network size increases, enhancing the stability of the ONN, making it highly robust. A saturation point exists beyond which the law of diminishing returns is observed. A tolerance of up to 99.9% in frequency fault and up to 59% in stuck-at fault is observed for extremely large networks of size 784 neurons.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"899-908"},"PeriodicalIF":2.4,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11023548","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced Single-Diode Solar Cell Model: Analytical Solutions Using Lambert W Function and Circuit Innovations 增强型单二极管太阳能电池模型：利用Lambert W函数和电路创新的解析解

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-06-02 DOI: 10.1109/JEDS.2025.3575706

Martin Ćalasan;Snežana Vujošević;Kristina Bakić

{"title":"Enhanced Single-Diode Solar Cell Model: Analytical Solutions Using Lambert W Function and Circuit Innovations","authors":"Martin Ćalasan;Snežana Vujošević;Kristina Bakić","doi":"10.1109/JEDS.2025.3575706","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3575706","url":null,"abstract":"This paper highlights significant advancements in the creation and enhancement of equivalent circuit models for solar cells. First, two novel configurations are proposed to enhance the classic single-diode model: one adds a diode between the terminal connections, while the other inserts a diode and resistor in series between the same terminals. Second, original analytical expressions for the current-voltage (I-V) characteristics of each proposed circuit are derived using the Lambert W function. Third, the performance of these models is rigorously evaluated on a variety of solar cells under diverse environmental conditions. Results demonstrated the models’ accuracy and robustness, with Root Mean Square Error (RMSE) analysis showing superior alignment between simulated and experimental I-V curves compared to existing single-, double-, and triple-diode solar cell models from the literature. Finally, the proposed approach enhances the mathematical precision in modeling solar cell behavior and provides a reliable framework for optimizing solar energy systems, contributing to improved performance and efficiency in practical applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"501-509"},"PeriodicalIF":2.0,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11020651","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications 基于VTH补偿技术的多比特IGZO 2T0C DRAM

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-29 DOI: 10.1109/JEDS.2025.3565658

Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu

{"title":"IGZO 2T0C DRAM With VTH Compensation Technique for Multi-Bit Applications","authors":"Kaifei Chen;Wendong Lu;Jiebin Niu;Menggan Liu;Fuxi Liao;Xuanming Zhang;Zihan Li;Naide Mao;Kaiping Zhang;Congyan Lu;Bok-Moon Kang;Jiawei Wang;Di Geng;Nianduan Lu;Guilei Wang;Zhengyong Zhu;Guanhua Yang;Chao Zhao;Arokia Nathan;Ling Li;Ming Liu","doi":"10.1109/JEDS.2025.3565658","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3565658","url":null,"abstract":"In this work, we proposed and experimentally demonstrated the novel dual-gate (DG) indium-gallium-zinc oxide (IGZO) two-transistor-zero-capacitance (2T0C) dynamic random-access memory (DRAM) for array-level multi-bit storage. Unlike traditional 2T0C DRAM, data writing strategy of the novel DG bit-cell is discharging process from storage node (SN) to bit line, achieving in-cell threshold voltage (VTH) compensation without sacrificing bit-cell layout. VTH modulation derived from the top gate of read transistor makes noticeable <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, with a record-high ratio (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN/<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VDATA) of 1.46, which improves the headroom for multi-bit storage. Moreover, the optimized transistors with positive VTH and high ON-state current enable long retention time (>1500 s) and ultra-fast writing speed (< 10 ns). Under the synergistic effect of VTH compensation and <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VSN boosting, non-overlap 3-bit storage operation among 25 cells is achieved with one order reduction of standard deviation. This study establishes a critical foundation for implementing multi-bit storage applications of IGZO 2T0C DRAM in large-scale array.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"439-443"},"PeriodicalIF":2.0,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10979978","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications 用于射频、功率和光电子应用的超宽带隙半导体器件

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-28 DOI: 10.1109/JEDS.2025.3562252

引用次数: 0

Investigating the Switching Dynamics of Antiferroelectric Capacitor Using Multidomain Phase-Field Approach 用多域相场法研究反铁电电容器的开关动力学

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-25 DOI: 10.1109/JEDS.2025.3564212

Muhammad Mainul Islam;Mohammad Adnaan;Sou-Chi Chang;Hai Li;Ian A. Young;Azad Naeemi

引用次数: 0

Analysis of InAs/InAsSb Superlattice Miniband Positions for a Cascade LWIR Detector 级联LWIR探测器InAs/InAsSb超晶格微带位置分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-24 DOI: 10.1109/JEDS.2025.3563981

K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk

{"title":"Analysis of InAs/InAsSb Superlattice Miniband Positions for a Cascade LWIR Detector","authors":"K. Murawski;K. Majkowycz;K. Michalczewski;J. Jureńczyk;Ł. Kubiszyn;T. Manyk;M. Kopytko;B. Seredyński;P. Martyniuk","doi":"10.1109/JEDS.2025.3563981","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563981","url":null,"abstract":"The paper presents an analysis of the miniband transitions of long- infrared (LWIR) interband cascade photodetectors (ICIP), with type-II superlattices (T2SLs), gallium-free (“Ga-free”) InAs/InAsSb (xSb <inline-formula> <tex-math>${=}0.39$ </tex-math></inline-formula>) absorber, grown by molecular beam epitaxy (MBE) on a GaAs (001) substrate. The results collected based on the photoluminescence (PL) and spectral response (SR) measurements were combined with theoretical calculations using the (<inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> Hamiltonian) k<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>p model for both strained and strain-free structure. The temperature dependence of HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, LH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1, SO<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>C1 and HH<inline-formula> <tex-math>${_{{1}}} rightarrow $ </tex-math></inline-formula>C1 was determined. Their respective 300 K energies were 114 meV, 195 meV, 290 meV and 380 meV, respectively. Moreover, the Varshni parameters were determined. For the PL results, 85 meV was observed across the entire temperature range. Remarkably, at cryogenic temperatures additional blue-shifted 5 meV and 14 meV transitions within the energy gap (Eg) occurred, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"390-395"},"PeriodicalIF":2.0,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10975787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0