IEEE Journal of the Electron Devices Society最新文献_第4页

Sub-0.1/h Bias Instability Achieved in Mode-Matched MEMS Gyroscopes Through Self-Clocking 通过自时钟实现模式匹配MEMS陀螺仪低于0.1/h的偏置不稳定性

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2025-07-11 DOI: 10.1109/JEDS.2025.3588165

Xuewen Liu;Junjie Bi;Guangyang Chen;Xukai Ding;Hongsheng Li

{"title":"Sub-0.1/h Bias Instability Achieved in Mode-Matched MEMS Gyroscopes Through Self-Clocking","authors":"Xuewen Liu;Junjie Bi;Guangyang Chen;Xukai Ding;Hongsheng Li","doi":"10.1109/JEDS.2025.3588165","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3588165","url":null,"abstract":"Bias drift remains a major challenge limiting the application of MEMS vibratory gyroscopes in high-precision fields. This paper presents a bias compensation approach through self-clocking. First, this study systematically analyzes the factors contributing to bias drift under dual-force feedback control, including quadrature stiffness coupling, in-phase damping coupling, and capacitive misalignment. In addition, the impact of phase error in the drive and sense modes on the bias output is thoroughly analyzed. And correlation analysis identifies quadrature stiffness coupling and in-phase damping couplings as the dominant error sources. To address these, the proposed method first suppresses quadrature errors through phase error correction and self-clocking operation. A detailed phase error correction method in the drive and sense modes is presented. The mechanism of self-clocking in digital systems of MEMS gyroscopes is investigated, aiming to achieve stable phase-frequency characteristics by synchronizing the sampling rate with the input signal frequency. This operation significantly reduces the quadrature error coupling on the bias output. Residual in-phase damping errors are then further suppressed using a drive-mode frequency self-compensation strategy. Experimental results demonstrate that the proposed approach reduces gyroscope bias instability from <inline-formula> <tex-math>$0.22^{circ }/h$ </tex-math></inline-formula> to <inline-formula> <tex-math>$0.06^{circ }/h$ </tex-math></inline-formula>. Additionally, nonlinearity is improved significantly, with the deviation reduced from 40 ppm to 9 ppm, confirming enhanced output stability and linearity.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"628-639"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078417","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling of FEOL and BEOL Amorphous Gallium Oxide-Based Ferroelectric FETs With a Metal Interlayer for Multilevel Operation in Short Channel Devices FEOL和BEOL非晶氧化镓基铁电场效应管在短通道器件中多电平工作的金属中间层的建模

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-28 DOI: 10.1109/JEDS.2026.3697979

Chiara Rossi;Daniel Lizzit;Charlotte van Dijck;Thanh Luan Phan;Catherine Dubourdieu;David Esseni

{"title":"Modeling of FEOL and BEOL Amorphous Gallium Oxide-Based Ferroelectric FETs With a Metal Interlayer for Multilevel Operation in Short Channel Devices","authors":"Chiara Rossi;Daniel Lizzit;Charlotte van Dijck;Thanh Luan Phan;Catherine Dubourdieu;David Esseni","doi":"10.1109/JEDS.2026.3697979","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3697979","url":null,"abstract":"Ferroelectric field effect transistors (FeFETs) are among the most promising candidates for the implementation of artificial synapses for neuromorphic computing. However, their scaling poses big challenges, as multilevel behavior is hindered by the two-level or very-few-level polarization behavior reported for devices featuring an aggressive lateral scaling. Moreover, the switching and stabilization of ferroelectric polarization, and consequently the device operation, is inherently linked to high levels of charge trapping in the gate stack, limiting the reliability and increasing the variability of the FeFETs. In this work we investigate, by means of calibrated TCAD simulations, FeFETs integrating a metal interlayer inside the gate stack. FeFETs are designed so that, by properly biasing the device, the metal interlayer can get charged thanks to charge tunneling through the dielectric layer. We first investigate a conventional front-end-of-line implementation, consisting of an aggressively scaled FeFET featuring a ferroelectric hafnium zirconium oxide and a dielectric hafnium oxide in the gate stack, a single-crystal silicon channel, and highly-doped source and drain pockets. Then we consider a back-end-of-line compatible device structure featuring lightly–doped amorphous gallium-oxide channel material, with Schottky-type tungsten contacts. We show that, for both architectures, the charge in the metal interlayer can effectively stabilize the ferroelectric polarization, even for a negligible charge trapping in the dielectric stack. Moreover, the interplay between ferroelectric polarization and charge in the metal interlayer enables a multilevel operation even for a uniform ferroelectric polarization.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"677-685"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11538167","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overcoming the Mobility–Stability Trade-Off Using an Ultra-Thin Oxide Capping Layer via N2O Plasma Treatment 利用N2O等离子体处理超薄氧化盖层克服迁移率与稳定性的权衡

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-19 DOI: 10.1109/JEDS.2026.3676152

Yi-Xuan Chen;Yi-Xin He;Yu-Shan Hsieh;Cheng-Kun Liu;Hui-Hsuan Li;Po-Heng Pao;Jia-Hao Chih;Bo-Heng Liu;Tsung-Te Chou;Chien-Ying Su;Yu-Hsien Lin;Chao-Hsin Chien

{"title":"Overcoming the Mobility–Stability Trade-Off Using an Ultra-Thin Oxide Capping Layer via N2O Plasma Treatment","authors":"Yi-Xuan Chen;Yi-Xin He;Yu-Shan Hsieh;Cheng-Kun Liu;Hui-Hsuan Li;Po-Heng Pao;Jia-Hao Chih;Bo-Heng Liu;Tsung-Te Chou;Chien-Ying Su;Yu-Hsien Lin;Chao-Hsin Chien","doi":"10.1109/JEDS.2026.3676152","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3676152","url":null,"abstract":"In this work, we first employed an ultra-thin capping layer and nitrous oxide (N2O) plasma treatment to fabricate 3.2 nm indium oxide (In2O3) bottom-gate FETs via atomic layer deposition (ALD). The capped layer provided hydrogen-related defects, enabling the N2O plasma treatment to maintain high on-current (Ion). With a 30 s N2O plasma treatment on capped In2O3, the device exhibited a subthreshold swing (S.S.) of 94 mV/dec, mobility of 61 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, enhancement-mode operation, and improved immunity to stress-induced degradation. The low-frequency noise (LFN) is attributed to mobility fluctuations (<inline-formula> <tex-math>$Delta mu $ </tex-math></inline-formula>) originating from the channel region. The device exhibits a normalized drain current noise power spectral density (SID/I<inline-formula> <tex-math>${_{text {D}}} {^{{2}}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$5.43times 10^{-12}$ </tex-math></inline-formula> Hz<inline-formula> <tex-math>${}^{text {$mathord {-}$1}}$ </tex-math></inline-formula>, a benchmark value among oxide semiconductor field-effect transistors (FETs). X-ray photoelectron spectroscopy (XPS) analysis reveals that N2O plasma treatment induces oxidation and the formation of interstitial oxygen, which consequently shifts the threshold voltage (VT). This approach effectively addresses the trade-off between mobility and positive VT, offering a promising solution for high-performance 3D integration applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"225-233"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11448788","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory 带间隧道效应对NAND闪存电荷阱层的影响

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-22 DOI: 10.1109/JEDS.2026.3693239

Seongwoo Kim;Beomgeun Lee;Seungjae Baik;Myounggon Kang

引用次数: 0

Metric- and Geometry-Dependent Mechanical Stress Effects on Hot-Carrier Degradation in nMOSFETs nmosfet中热载流子退化的机械应力效应

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-09-10 DOI: 10.1109/JEDS.2026.3732629

Byeonghun Lee;Dong Kyu Kim;So Hyeon Lee;Hyunsang Hwang

{"title":"Metric- and Geometry-Dependent Mechanical Stress Effects on Hot-Carrier Degradation in nMOSFETs","authors":"Byeonghun Lee;Dong Kyu Kim;So Hyeon Lee;Hyunsang Hwang","doi":"10.1109/JEDS.2026.3732629","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3732629","url":null,"abstract":"This work investigates the effect of externally applied uniaxial mechanical stress (MS) on hot-carrier degradation (HCD) in nMOSFETs. Uniaxial tensile and compressive MS of ±300 MPa are applied via four-point bending to investigate purely mechanical effects. Among the monitored parameters, including threshold voltage shift, saturation current degradation, and linear current degradation, only linear current degradation shows a clear order of tensile > unstressed > compressive. The impact ionization rate and power-law time exponents remain unchanged across the applied MS range, indicating that MS barely alters the trap generation kinetics. The apparent MS separation in linear current degradation is attributed to the MS-dependent initial resistance and the MS-proportional hot-carrier flux. It is also shown that the MS-induced separation decreases at high gate voltage and in devices with shorter and narrower channels. These findings demonstrate that when assessing HCD reliability under MS, the choice of degradation metric, sensing gate voltage, and device geometry must be carefully considered.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"863-868"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11686008","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149034030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Device Design of Material-Defined Ge Quantum Dots/Si-Based Barriers for Charge Stability and Sensing 材料定义锗量子点/硅基电荷稳定性和传感势垒的器件设计

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-09-07 DOI: 10.1109/JEDS.2026.3731214

Ting Tsai;I-Hsiang Wang;Yu-Wen Chiu;Chi-Cheng Lai;David M. T. Kuo;Horng-Chih Lin;Pei-Wen Li

引用次数: 0

Low-Power Dual-I/O Emission Driver Circuit for Metal-Oxide TFT-Based AMOLED Displays 金属氧化物tft基AMOLED显示器的低功耗双i /O发射驱动电路

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-08-31 DOI: 10.1109/JEDS.2026.3728679

Jungsuk Oh;Hyeongmin Kim;Yikyoung You;Sangwoon Lee;Junhyung Lim;Kyoungseok Son;Jaybum Kim;Youngoo Kim;Kyunghoe Lee;Kyounghoon Chung;Keechan Park

{"title":"Low-Power Dual-I/O Emission Driver Circuit for Metal-Oxide TFT-Based AMOLED Displays","authors":"Jungsuk Oh;Hyeongmin Kim;Yikyoung You;Sangwoon Lee;Junhyung Lim;Kyoungseok Son;Jaybum Kim;Youngoo Kim;Kyunghoe Lee;Kyounghoon Chung;Keechan Park","doi":"10.1109/JEDS.2026.3728679","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3728679","url":null,"abstract":"Conventional emission driver circuits in organic light-emitting diode (OLED) displays typically rely on periodic boosting of internal nodes to maintain stable output voltages, which inevitably accompanies periodic charging and discharging of internal capacitors. This not only leads to high dynamic power consumption but also increases circuit complexity due to the boosting structures. To solve this issue, we propose a novel emission driver circuit that employs charging-delay-based bootstrapping with complementary dual-input and output signals. The charging-delay bootstrapping method eliminates the need for periodic charging and discharging of the internal capacitor, thereby reducing dynamic power consumption, and the dual-input scheme simplifies the overall circuit structure. SPICE simulation results confirm that the proposed circuit maintains stable output voltage waveforms under various pulse-width-modulation (PWM) driving conditions of the OLED display while achieving up to 64.4% reduction of power consumption compared with conventional circuits. Furthermore, measurement results from fabricated test samples confirm that the circuit maintains stable output voltage waveforms even after 300 hours of continuous operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"777-785"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11672770","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

P-Channel Tri-Gate Nanowire InGaN/GaN/AlN/InAlGaN MOS-HFET for Power Switching Applications 功率开关用p沟道三栅纳米线InGaN/GaN/AlN/InAlGaN MOS-HFET

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-03-18 DOI: 10.1109/JEDS.2026.3694315

Jian-Hong Ke;Ching-Sung Lee;Chung-Liang Liao;Wei-Chou Hsu

{"title":"P-Channel Tri-Gate Nanowire InGaN/GaN/AlN/InAlGaN MOS-HFET for Power Switching Applications","authors":"Jian-Hong Ke;Ching-Sung Lee;Chung-Liang Liao;Wei-Chou Hsu","doi":"10.1109/JEDS.2026.3694315","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3694315","url":null,"abstract":"This work reports record-high three-terminal on-state drain-source breakdown voltage (BV<inline-formula> <tex-math>${}_{DS}$ </tex-math></inline-formula>) of -975 V and superior switching characteristics of p-channel InGaN/GaN/AlN/ InAlGaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with a tri-gate nanowire structure. Improved gate modulation capability and breakdown performance were achieved by the devised tri-gate nanowire and gate field-plate (GFP) structures. Non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique was used to deposit the high-k wide-bandgap Al2O3 as the gate dielectric and surface passivation simultaneously. The present p-channel tri-gate nanowire MOS-HFET design has exhibited improved maximum drain-source current density (<inline-formula> <tex-math>$I_{DS,~max}$ </tex-math></inline-formula>) of −28.0 mA/mm, subthreshold swing (SS) of 75.6 mV/dec, on/off current ratio (<inline-formula> <tex-math>$I_{on}/I_{off}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$1.1times 10^{8}$ </tex-math></inline-formula>, two-terminal off-state gate-drain breakdown voltage (BV<inline-formula> <tex-math>${}_{GD}$ </tex-math></inline-formula>) of 995 V, BV<inline-formula> <tex-math>${}_{DS}$ </tex-math></inline-formula> of −975 V, and Baliga’s figure of merit (BFOM) of 60.5 MW/cm2. The reliability of the present design was also evaluated through time-dependent electrical stress, demonstrating its advantageous potential for high-voltage complementary power-switching circuit applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"297-303"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11522794","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Harvesting Asymmetry in Semitransparent Polymer Solar-Cells Based on a Laminated Transparent Electrode 基于层压透明电极的半透明聚合物太阳能电池能量收集不对称性研究

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-06-05 DOI: 10.1109/JEDS.2026.3700104

Changhun Yun;Moon Hee Kang

{"title":"Energy-Harvesting Asymmetry in Semitransparent Polymer Solar-Cells Based on a Laminated Transparent Electrode","authors":"Changhun Yun;Moon Hee Kang","doi":"10.1109/JEDS.2026.3700104","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3700104","url":null,"abstract":"Semitransparent polymer solar cells (ST-PSCs) with laminated transparent electrodes are promising candidates for building-integrated photovoltaics. However, the optical mechanisms governing their bidirectional performance remain underexplored. We systematically investigated the photovoltaic response of a vacuum-free laminated transparent electrode (LTE) comprising PEDOT:PSS/silver nanowire (AgNW) integrated with a PTB7:PC71BM photoactive layer (PAL) under top-side and bottom-side illumination. External quantum efficiency (EQE) measurements combined with transfer-matrix (TMM) optical simulations were used to deconvolute the optical and electrical contributions to the observed performance asymmetry. A 20.5% photocurrent reduction was measured upon top-side illumination (9.24 mA cm−2) compared with bottom-side (11.63 mA cm−2), which optical simulations attributed to wavelength-dependent parasitic absorption in the PEDOT:PSS/AgNW thin layer (300–450 nm) and to interfacial exciton quenching combined with the LTE’s direct proximity to the PAL. The open-circuit voltage remained nearly invariant across both illumination directions, demonstrating that the vacuum-free lamination process preserved the electronic integrity of the active layer. The device achieved 3.79% power conversion efficiency with 36.9% average visible transmittance. The introduction of a diffuse scattering paper layer at the rear recovered 10.1% of the lost photocurrent through photon recycling, thereby increasing the short-circuit current density to 12.80 mA cm−2 and efficiency to 4.45%. These findings establish the dominant optical loss mechanisms in laminated transparent electrodes and demonstrate a scalable light-management strategy for enhancing the semitransparent photovoltaic performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"389-398"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11552626","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Trap-Based Modeling and Mechanisms of Non-Monotonic Hot-Carrier Degradation in Cryogenic CMOS Devices 低温CMOS器件中非单调热载子降解的阱建模与机理研究

IF 2.9 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2026-01-01 Epub Date: 2026-06-08 DOI: 10.1109/JEDS.2026.3701063

Junru Qu;Xinze Li;Dong Liu;Ran Tao;Yuanxi Liao;Yuchen Gu;Di Yang;Qing Tian;Ying Sun;Yongyu Wu;Dawei Gao;Bing Chen;Yong Ding;Genquan Han;Ran Cheng

{"title":"Trap-Based Modeling and Mechanisms of Non-Monotonic Hot-Carrier Degradation in Cryogenic CMOS Devices","authors":"Junru Qu;Xinze Li;Dong Liu;Ran Tao;Yuanxi Liao;Yuchen Gu;Di Yang;Qing Tian;Ying Sun;Yongyu Wu;Dawei Gao;Bing Chen;Yong Ding;Genquan Han;Ran Cheng","doi":"10.1109/JEDS.2026.3701063","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3701063","url":null,"abstract":"This work experimentally characterized and investigated the temperature dependence of hot carrier injection (HCI) at low temperature (LT) for 130 nm foundry-level CMOS with no resolvable transient self-heating-effect (SHE) induced current droop under the tested conditions. Cryogenic virtual source transistor model together with trap models at LT are developed and employed to extract the related carrier and trap parameters. For both n- and pFETs, the temperature dependence of HCI-induced degradation (HCD) exhibits a non-monotonic aggravation from 300 K to 8 K. For nFETs, the HCD is mainly caused by interface traps, while for pFETs, it is additionally controlled by the electron trapping to existing oxide traps, which causes the opposite shift of <inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula> when the stress time is short and the temperature is low. Based on the extracted trap parameters, both types of traps strongly correlate to the mean free path <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>. Therefore, <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> shows the maximum value at 45 K, where <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula> reaches the maximum due to the reduced phonon scattering and the enhanced ionized impurity scattering. The temperature, voltage and time dependence of the HCD can be precisely calculated by the trap-based model developed in this work. Careful design and process optimizations are necessary to improve the LT HCI reliability of Si CMOS for various LT applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"399-407"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11554037","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0