IEEE Journal of the Electron Devices Society最新文献_第5页

Prediction of Single Event Effect in Inverter Circuit Based on Deep Learning 基于深度学习的逆变电路单事件效应预测

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-05 DOI: 10.1109/JEDS.2025.3561075

Jin Huang;Rong Zhao;Shulong Wang;Xingyuan Yan;Hao Zhou;Liutao Li;Shupeng Chen;Hongxia Liu

{"title":"Prediction of Single Event Effect in Inverter Circuit Based on Deep Learning","authors":"Jin Huang;Rong Zhao;Shulong Wang;Xingyuan Yan;Hao Zhou;Liutao Li;Shupeng Chen;Hongxia Liu","doi":"10.1109/JEDS.2025.3561075","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3561075","url":null,"abstract":"Fully Depleted Silicon on Insulator (FDSOI) technology can solve the short channel effect very effectively, with low power consumption, and low voltage, and can improve the subthreshold characteristics of the device. In addition, FDSOI devices have good radiation resistance, which has become an important research object in the field of device research. Single event effect (SEE) is an important index of radiation resistance of FDSOI devices. At present, the research on SEE of FDSOI devices typically employs heavy-ion irradiation experiments and TCAD software simulations. Taking FDSOI technology as an example, this paper presents a research method of device modeling and performance prediction based on deep learning. The accuracy of the peak of transient current <inline-formula> <tex-math>$(I_{peak})$ </tex-math></inline-formula> predicted by this method is 96.45%, the accuracy of total collected charge <inline-formula> <tex-math>$(Q_{total})$ </tex-math></inline-formula> is 97.86%, and the determination coefficient of drain transient current pulse (It) is 0.97717. This method can obviously improve the simulation speed and reduce the calculation cost, and provide a new feasible method for the research of FDSOI devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"431-438"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10982521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Corrections to “Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure” 对“GeSn/GeSiSn双势垒结构中空穴共振隧道负差分电阻的出现”的修正

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-05 DOI: 10.1109/JEDS.2025.3542189

Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka

引用次数: 0

Compact Modeling of 3D NAND Flash Memory With Ferroelectric Characteristics: A Comparative Analysis of O/N/O and O/N/F Structures 具有铁电特性的三维NAND闪存的紧凑建模：O/N/O和O/N/F结构的比较分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-05 DOI: 10.1109/JEDS.2025.3567077

Sunghyun Woo;Jihwan Lee;Gyunseok Ryu;Myounggon Kang

引用次数: 0

Channel Length Dependence of Effective Barrier Height Experienced by Charge Carriers in Schottky-Barrier Transistors Based on Si-Nanowire Arrays 基于硅纳米线阵列的肖特基势垒晶体管中载流子所经历的有效势垒高度的沟道长度依赖性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-04 DOI: 10.1109/JEDS.2025.3547860

Dae-Young Jeon;So Jeong Park;Sebastian Pregl;Jens Trommer;André Heinzig;Thomas Mikolajick;Walter M. Weber

引用次数: 0

Advanced Microfluidic Biofuel Cells Using Gold and Silver Leaf on Paper and PDMS Substrates: Toward Implantable Energy Solution 在纸和PDMS衬底上使用金和银叶子的先进微流控生物燃料电池：迈向可植入的能量解决方案

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-04 DOI: 10.1109/JEDS.2025.3547869

S. Vanmathi;Sanket Goel

{"title":"Advanced Microfluidic Biofuel Cells Using Gold and Silver Leaf on Paper and PDMS Substrates: Toward Implantable Energy Solution","authors":"S. Vanmathi;Sanket Goel","doi":"10.1109/JEDS.2025.3547869","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547869","url":null,"abstract":"An exploration of new and simplified electrode materials such as gold leaf (GL), and silver leaf (SL) based approaches to enhance the efficiency and scalability of microfluidic biofuel cell renewable energy sources has generated significant interest. Our research aims to utilize the unique properties of these materials to create advanced biofuel cells, with a specific focus on implantable devices. By employing nanoporous gold and patterned silver leaf, are designing flexible, efficient, and scalable biofuel cells that have the potential to revolutionize energy solutions in medical and wearable technologies. Microfluidic biofuel cells with nanostructured gold and silver leaf devices harvest ultra-low power energy, making them more practical for real-world applications. The gold and silver leaf enzymatic biofuel cell (LEBFC) operates using glucose as fuel, with glucose oxidase functioning at the anode and laccase at the cathode, both coating the GL and SL bioelectrodes. These leaf microfluidic devices, fabricated using polydimethylsiloxane (PDMS) and filter paper, demonstrated a peak open circuit voltage of 197 mV and 448 mV, along with a maximum power density of <inline-formula> <tex-math>$28.7 mu mathrm{~W} / mathrm{cm}^2$ </tex-math></inline-formula> and <inline-formula> <tex-math>$93.6 mu mathrm{~W} / mathrm{cm}^2$ </tex-math></inline-formula>, respectively. Such flexible devices are lightweight, non-toxic, edible, and biodegradable, designed for optimal load connection to ensure stable performance while reducing weight. Please replace with this sentence. It opens new opportunities for sustainable power generation and offers promising applications in wearable, implantable, and portable microelectronic devices, where reliable, low-power energy sources are inexpensive.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"173-181"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909661","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Stability of Gate Driver Circuits Based on 4H-SiC MOSFETs at 300°C for High-Power Applications 基于4H-SiC mosfet的栅极驱动电路在300°C下的热稳定性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-03 DOI: 10.1109/JEDS.2025.3546959

Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki

{"title":"Thermal Stability of Gate Driver Circuits Based on 4H-SiC MOSFETs at 300°C for High-Power Applications","authors":"Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki","doi":"10.1109/JEDS.2025.3546959","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3546959","url":null,"abstract":"The operation and reliability of gate driver circuits based on 4H-SiC MOSFETs at temperatures up to 300°C were reported. Due to the advantages of 4H-SiC MOSFETs, the driver circuit can overcome limitations in complicated circuit design and power dissipation associated with SiC BJTbased technology. Additionally, the stability of implanted 4H-SiC resistors can address the reliability issues of SiC CMOS-based driver circuits, which are caused by the instability in the threshold voltage of P-channel SiC MOSFETs. In this study, the switching characteristics of the gate driver circuit were improved when the ambient temperature increased. The decrease of threshold voltage and increase of carrier mobility of the 4H-SiC MOSFETs may account for the improvement in switching characteristics of the gate driver circuit. The output signal of the gate driver circuit still showed proper characteristics after 600 min of continuous operation at 300°C in an air ambient. These results indicate that the gate driver circuit based on 4H-SiC MOSFET technology is promising to apply for high power applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"161-167"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10908627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Analysis of Rare-Earth Doped Oxide Thin-Film Transistors Using Neural Network Method 基于神经网络方法的稀土掺杂氧化物薄膜晶体管性能分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-03 DOI: 10.1109/JEDS.2025.3547646

Zengyi Peng;Xianglan Huang;Yuanyi Shen;Weijing Wu;Min Li;Miao Xu;Lei Wang;Zhenghui Gu;Zhuliang Yu;Junbiao Peng

{"title":"Performance Analysis of Rare-Earth Doped Oxide Thin-Film Transistors Using Neural Network Method","authors":"Zengyi Peng;Xianglan Huang;Yuanyi Shen;Weijing Wu;Min Li;Miao Xu;Lei Wang;Zhenghui Gu;Zhuliang Yu;Junbiao Peng","doi":"10.1109/JEDS.2025.3547646","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547646","url":null,"abstract":"The work analyzes the key impact factors on the performances of rare-earth element doped oxide thin-film transistors (TFTs), which are potentially used for high performance displays, by comparatively using a Bayesian Neural Network (BNN) method and Artificial Neural Network (ANN) method based on published and self-experimental data which was exhaustively collected. Both BNN and ANN methods can effectively identify the primary impact factors among rare-earth element type, doping concentration, thin film thickness, channel length and width, which are key factors to determine the TFTs performances. Comparisons between the BNN and ANN methods, the BNN approach offers more reliable and robust predictions on the dataset. Accordingly, the efficient neural network models tailored to the data features were accurately established. A key outcome from the BNN models is the relative importance ranking of the influence factors and relationship between the carrier mobility and element type, concentration as well. To the TFT mobility, rare-earth element concentration is the most critical factor, suggesting lower concentration exhibited higher mobility, followed by the rare-earth element type. To the sub-threshold swing performance of TFTs, the rare-earth element type is the most significant influence factor, suggesting higher valence rare-earth is superior to lower valence one, followed by the element concentration. The results are basically consistent with experimental tendency. These insights could effectively guide the design of oxide semiconductor materials and TFT device structure, to achieve high-performance (high mobility and high stability) oxide TFT devices for displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"263-269"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909085","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IGZO 2T1C DRAM With Low Operation Voltage and High Current Window 具有低工作电压和大电流窗的IGZO 2T1C DRAM

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-02 DOI: 10.1109/JEDS.2025.3566162

Wendong Lu;Kaifei Chen;Menggan Liu;Fuxi Liao;Zijing Wu;Naide Mao;Zihan Li;Xuanming Zhang;Congyan Lu;Jiebin Niu;Bok-Moon Kang;Jing-Hong Shi;Xie-Shuai Wu;Gui-Lei Wang;Zhengyong Zhu;Jiawei Wang;Lingfei Wang;Di Geng;Nianduan Lu;Guanhua Yang;Chao Zhao;Ling Li

{"title":"IGZO 2T1C DRAM With Low Operation Voltage and High Current Window","authors":"Wendong Lu;Kaifei Chen;Menggan Liu;Fuxi Liao;Zijing Wu;Naide Mao;Zihan Li;Xuanming Zhang;Congyan Lu;Jiebin Niu;Bok-Moon Kang;Jing-Hong Shi;Xie-Shuai Wu;Gui-Lei Wang;Zhengyong Zhu;Jiawei Wang;Lingfei Wang;Di Geng;Nianduan Lu;Guanhua Yang;Chao Zhao;Ling Li","doi":"10.1109/JEDS.2025.3566162","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3566162","url":null,"abstract":"In this work, we propose and experimentally demonstrate a novel IGZO 2T1C cell. Novel bit-cell applies read-word-line to the capacitor terminal and utilize the coupling effect of the capacitor to achieve storage node (SN) voltage modulation. By this design, a larger current window can be achieved by biasing the read transistor to the region with the steepest subthreshold slope. Through optimizing the gate dielectric thickness, DG IGZO transistor of <inline-formula> <tex-math>${mathrm { L}}_{mathrm {CH}}$ </tex-math></inline-formula>=50 nm achieves ultra-low subthreshold slope of 63.9 mV/dec. Based on optimized devices, the implementation of DRAM features an ultra-high current window (Idata‘1’/Idata‘0’) of <inline-formula> <tex-math>$sim {mathrm {10}}^{mathrm {3}}$ </tex-math></inline-formula> at ultra-low write voltage of 0.2 V. Furthermore, the proposed novel 2T1C bit-cell provides a more reliable gate-controlled read scheme. This work paves the forward way for low voltage and reliable sensing IGZO DRAM application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"444-449"},"PeriodicalIF":2.0,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981849","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144090766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) 负电容互补场效应管（CFET）设计优化的几点思考

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-27 DOI: 10.1109/JEDS.2025.3546314

Sandeep Semwal;Pin Su

引用次数: 0

Nanomole Process: Enabling Localized Metallic Back-Gates for Enhanced Cryogenic Front-to-Back Coupling in FDSOI Quantum Dots 纳米分子工艺：在FDSOI量子点中实现局部金属后门以增强低温前后耦合

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-25 DOI: 10.1109/JEDS.2025.3545661

Fabio Bersano;Niccolò Martinolli;Ilan Bouquet;Michele Ghini;Eloi Collette;Liza Žaper;Floris Braakman;Martino Poggio;Mathieu Luisier;Adrian Mihai Ionescu

{"title":"Nanomole Process: Enabling Localized Metallic Back-Gates for Enhanced Cryogenic Front-to-Back Coupling in FDSOI Quantum Dots","authors":"Fabio Bersano;Niccolò Martinolli;Ilan Bouquet;Michele Ghini;Eloi Collette;Liza Žaper;Floris Braakman;Martino Poggio;Mathieu Luisier;Adrian Mihai Ionescu","doi":"10.1109/JEDS.2025.3545661","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3545661","url":null,"abstract":"This paper introduces a novel integration method of localized metallic back-gates into fully-depleted silicon-on-insulator (FDSOI) multi-gate FETs, enabling robust front-to-back electrostatic coupling from room temperature to cryogenic conditions, without the need for substrate implantation. The fabrication process, termed the Nanomole process, utilizes nanometric vapor-phase etching of the buried oxide or silicon substrate with vapor-HF and XeF2 gases. This is followed by atomic layer deposition (ALD) of a dielectric material and Pt, with precise patterning achieved through inductively coupled plasma etching. Detailed analysis of the process demonstrates controllable etch rates based on device geometry, providing calibrated guidelines for scalable manufacturing. Symmetric mid-k dual-gating is reported in devices featuring a Si-film thickness of 24 nm, with a top and bottom gate oxide equivalent thickness (EOT) of 6.5 nm. Electrical characterization of multi-gate FDSOI SETs, operated as FETs, confirms effective threshold voltage tuning through dual-gate operation, with consistent performance from room temperature to millikelvin regimes. Additionally, quantum mechanical simulations based on the effective mass approximation at 4 K offer insights into the electrostatic behavior of dual-gated SOI quantum dot devices in both planar and nanowire geometries. This scalable and versatile technological solution opens new possibilities for advanced quantum devices, such as charge and spin qubits, by enabling in situ control over volume inversion, electron valley splitting, and spin-orbit interaction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"210-218"},"PeriodicalIF":2.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10902357","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0