IEEE Journal of the Electron Devices Society最新文献

{"title":"Dielectric-Stack-Engineered Anti-Ambipolar Transistors for Low-Voltage Ternary Logic","authors":"Juhyung Seo;Jihyun Shin;Ulrike Kraft;Hocheon Yoo;Ryoma Hayakawa;Yutaka Wakayama","doi":"10.1109/JEDS.2026.3737142","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3737142","url":null,"abstract":"We demonstrate an ultralow-voltage ternary multi-valued logic (MVL) inverter based on an extended <inline-formula> <tex-math>$p$ </tex-math></inline-formula>-channel anti-ambipolar transistor (E<inline-formula> <tex-math>$p$ </tex-math></inline-formula>-AAT) employing an optimized HfO2/polystyrene gate dielectric stack. The HfO2 dielectric enables low-voltage operation, while the polystyrene surface layer provides a low-surface-energy interface for stable organic channel formation. The E<inline-formula> <tex-math>$p$ </tex-math></inline-formula>-AAT exhibits an intrinsic N-shaped transfer characteristic with a clear negative transconductance region, explained by the combined contributions of the N1, P1, and P2 channels. Integrated with an <inline-formula> <tex-math>$n$ </tex-math></inline-formula>-type transistor, the E<inline-formula> <tex-math>$p$ </tex-math></inline-formula>-AAT realizes a ternary MVL inverter with three distinct logic states at a supply voltage of 2 V without additional circuit complexity. These results highlight the potential of HfO2/polystyrene-based E<inline-formula> <tex-math>$p$ </tex-math></inline-formula>-AATs for MVL circuits.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"875-880"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11721265","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149249432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Leakage and High-Breakdown Enhancement-Mode InAlGaN/GaN HEMTs Using a Non-Recessed Mist-CVD Li-Doped NiO/Al2O3 p-Gate Stack","authors":"Yan-Kuei Wu;Yu-Hsuan Chen;Hao-Chun Hung;Rong-Ming Ko;Wei-Chou Hsu","doi":"10.1109/JEDS.2026.3691182","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3691182","url":null,"abstract":"Enhancement-mode (E-mode) InAlGaN/GaN high-electron-mobility transistors (HEMTs) are highly desirable for fail-safe power and RF applications; however, achieving stable normally-off operation without inducing plasma damage remains challenging due to the strong polarization effects in InAlGaN barriers. In this work, non-recessed E-mode InAlGaN/GaN HEMTs enabled by a mist chemical vapor deposition (mist-CVD)–grown Li-doped NiO/Al2O3 p-gate stack are demonstrated. The Al2O3 interlayer serves as a low-damage interface buffer and leakage-suppression dielectric, while the p-type Li-doped NiO layer provides active electrostatic modulation to effectively deplete the polarization-induced two-dimensional electron gas without gate recessing. Compared with undoped p-NiO and Al2O3-only gate configurations, the Li-doped NiO (p-Li:NiO) device exhibits clear enhancement-mode operation with the threshold voltage shifting from −2.36 V to +0.32 V. A high maximum transconductance of 498 mS/mm and an increased saturation drain current of 523 mA/mm are achieved, together with a substantially suppressed gate leakage current of <inline-formula> <tex-math>$9.8times 10^{-{9}}$ </tex-math></inline-formula> mA/mm at <inline-formula> <tex-math>${V}_{G}$ </tex-math></inline-formula> = −10 V. Moreover, the p-Li:NiO-gated HEMT demonstrates an exceptional off-state breakdown voltage of 2423 V (<inline-formula> <tex-math>${I}_{D}$ </tex-math></inline-formula> = 1 nA/mm), resulting in a Baliga’s figure of merit of 2.14 GW/cm2. Long-term DC bias stress measurements up to 15,000 s reveal minimal drain-current degradation and excellent threshold-voltage stability, confirming the robustness of the proposed gate stack. These results establish mist-CVD Li-doped NiO/ Al2O3 p-gate engineering as a reliable and process-compatible solution for high-performance, non-recessed enhancement-mode InAlGaN/GaN HEMTs targeting next-generation GaN power electronic applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"258-267"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11511710","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148000394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Plasma Processes and Associated Mechanisms of Hybrid Bonding for Heterogeneous Integration: A Review","authors":"Mei-Chien Lu","doi":"10.1109/JEDS.2026.3697973","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3697973","url":null,"abstract":"The hybrid bonding for heterogeneous integration has gained momentum for advanced applications in image sensors (IS), high performance computing (HPC), and artificial intelligence (AI). The hybrid bonding can enable the chip-to-chip interconnections at ultra-high density for increased bandwidth, energy efficiency and design feasibility with scalability beyond achievable by microbumps. The continuous improvement is yet ongoing to expand to applications requiring low hybrid bonding temperature, deep submicron hybrid bonding pad pitch and high quality of hybrid bonding with high yield and reliability performance. The multi-disciplinary research to understand the bonding mechanisms on materials and processing on metal and dielectrics with different characteristics could help to further advance the technology. This review emphasizes the roles of plasma processes on hybrid bonding especially on plasma processed dielectric characteristics, plasma surface treatment enhanced hybrid bonding quality, impact of post annealing to the plasma activated dielectric bonding, associated dielectric-dielectric bonding mechanisms, impact of plasma treatment on Cu surface, and Cu surface passivation during plasma activation. It first refreshes the fundamental technology developed from Si/SiO2 wafer bonding to lay the foundation followed by the recent progress in the understanding of mechanisms of SiCN-SiCN bonding including but not limiting to plasma damage, dangling bonds, water stress corrosion, and interfacial voids. The requirements of dielectric capping layer and a few alternative candidates for capping layer dielectrics are reviewed for feasibility. The requirements of pre-bonding Cu surface is atomically clean. However, the embedded Cu pads in dielectrics would be exposed to the same plasma conditions as the dielectrics. Concerns of Cu surface compound formation during plasma surface activation and the progresses of co-optimization plasma chemistry for both dielectric and Cu are addressed. The challenges and future development are highlighted for reaching the ultimate manufacturing goals of high yield and high reliability hybrid bonding for versatile applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"346-368"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11538206","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of 3D-DRAM Architecture With Oxide-Semiconductor Channel Through Process and Device Simulation","authors":"Jiseok Hong;Nouredine Rassoul;Assawer Soussou;Geert Eneman;Subhali Subhechha;Hyungrock Oh;Attilio Belmonte;Jan van Houdt;Anne S. Verhulst","doi":"10.1109/JEDS.2026.3715074","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3715074","url":null,"abstract":"Scaling of conventional 6F<inline-formula> <tex-math>${}^{2}~1$ </tex-math></inline-formula>T-1C DRAM is increasingly constrained as the buried-channel array transistor approaches its physical limits below the 10-nm node. Monolithic three-dimensional (3D) DRAM improves density through vertical stacking, while oxide semiconductor (OSC) channels promise low leakage. In this work we investigate a monolithically stackable OSC-based 3D-DRAM cell using an integrated framework combining process emulation, TCAD device simulation, parasitic extraction, and analytical modeling. Key geometric parameters are analyzed together with storage-node and parasitic capacitances extracted from process-emulated 3D structures. The optimized device achieves an on-current of <inline-formula> <tex-math>$14.5~mu $ </tex-math></inline-formula>A/cell and a storage capacitance of 1.34 fF. The proposed architecture exhibits favorable intrinsic-cell retention, delay, and energy characteristics, while highlighting remaining challenges in process integration and reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"500-506"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11614411","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Prolonged Negative Threshold Voltage Shift Induced by Low Drain Bias in Schottky p-GaN Gate HEMTs","authors":"Myeongsu Chae;Hyungtak Kim","doi":"10.1109/JEDS.2026.3726880","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3726880","url":null,"abstract":"In this work, threshold voltage (V<inline-formula> <tex-math>${}_{mathrm {th}}$ </tex-math></inline-formula>) instability was investigated under drain bias stress in Schottky p-GaN gate high electron mobility transistors (HEMTs). A negative shift in threshold voltage was observed under a very low drain bias condition. The negative shift is likely due to an intrinsic donor-like trap state in the p-GaN layer. In contrast, positive shifts in threshold voltage occurred in two distinct phases under higher drain bias stress. With increasing temperature, the initial positive shift was alleviated, while the subsequent positive shift became pronounced during the prolonged stress period. This suggests that multiple mechanisms contribute to the observed positive shifts in threshold voltage. These positive shifts are associated with the Schottky junction barrier and defect state in the GaN buffer layer, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"828-835"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11666893","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148986132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Global Stress Analysis in Fin-Patterned Si/SiGe Nanosheets Stack and Its Impact on GAA-NS Transistors for Next-Generation CMOS Technology","authors":"Amit Kumar Singh Chauhan;Imtiyaz Ahmad Khan;Kunal;Harsh Raju;Sanjeev Kumar Manhas","doi":"10.1109/JEDS.2026.3658868","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3658868","url":null,"abstract":"Si/SiGe nanosheet (NS)-based CMOS technology is emerging as a leading candidate for sub-3 nm technology nodes owing to its excellent electrostatic control and scalability. A critical challenge, however, lies in understanding the stress evolution during sequential stacking and fin patterning of Si/SiGe nanosheets, which strongly impacts carrier transport and reliability of the IC. In this work, we systematically investigate the stress distribution in Si/SiGe superlattice nanosheets after fin pattering and analyze its influence on the Si channel region of gate-all-around nanosheet (GAA-NS) transistors. The SiGe nanosheets (Ge mole fraction <inline-formula> <tex-math>${=} 0.35$ </tex-math></inline-formula>) exhibit an initial compressive stress of 2.17 GPa, while the Si nanosheets are initially stress-neutral. Fin patterning induces tensile stress in the Si layers due to relaxation of compressive stress in the SiGe nanosheets, leading to a residual tensile stress in the final GAA-NS channel. The extracted maximum in-plane stresses reach 0.43 GPa (<inline-formula> <tex-math>$sigma _{mathrm { xx}}$ </tex-math></inline-formula>, along the channel length) and 0.96 GPa (<inline-formula> <tex-math>$sigma _{mathrm { yy}}$ </tex-math></inline-formula>, along the width), depending on device geometry. Electrical simulations confirm that this residual biaxial tensile stress enhances the drive current of both n-type and p-type GAA-NS transistors by more than 8% at a fixed gate metal work function. These findings offer crucial design insights for stress-engineered Si/SiGe nanosheet CMOS technology to boost device performance and ensure reliability at beyond-3 nm nodes.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"710-718"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11366113","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148746947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experiment Investigation of La₂O₃ Dipole-Last Cap-Less VFB Tuning Technology With Low-Thermal Post Deposition Anneal","authors":"Yu Wang;Jiaxin Yao;Yanzhao Wei;Qingzhu Zhang;Huaxiang Yin","doi":"10.1109/JEDS.2025.3637894","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3637894","url":null,"abstract":"In this study, the effect of post-deposition anneal (PDA) temperature on flat-band voltage (VFB) modulation using the La2O3 dipole-last cap-less <inline-formula> <tex-math>$rm V_{FB}$ </tex-math></inline-formula> tuning technique is investigated, in which the large positive <inline-formula> <tex-math>$rm V_{FB}$ </tex-math></inline-formula> modulation range is observed. Simultaneously, the lower equivalent oxide thickness (EOT) is obtained. Experimental results revealed that the La2O3 dipole-last cap-less process, conducted with a 650°C PDA, achieved <inline-formula> <tex-math>$rm V_{FB}$ </tex-math></inline-formula> modulation of 120 mV and reduction in EOT of 0.09 nm. Additionally, this process was found to suppress the increase in interface trap density (Dit) and gate leakage current. However, due to the high thermal budget, La2O3 dipole-last cap-less process resulted in increased the voltage hysteresis during dual-sweep Capacitance–voltage (C–V) measurements, indicating a rise in trap/detrap electron density (Not). Meanwhile, high-resolution transmission electron microscope (HRTEM) image and energy dispersive X-ray (EDX) analysis revealed that La did not diffuse into the <inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula> high-<inline-formula> <tex-math>$rm kappa $ </tex-math></inline-formula> layer and O atomic ratio in the <inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula> layer was found to decrease with increasing PDA temperature. Furthermore, an interpretative model with La2O3-assisted oxygen migration is proposed for explaining of <inline-formula> <tex-math>$rm V_{FB}$ </tex-math></inline-formula> modulation by La2O3 dipole-last cap-less process. These findings provide the insights into the <inline-formula> <tex-math>$rm V_{FB}$ </tex-math></inline-formula> positive modulation of the La2O3 dipole-last cap-less <inline-formula> <tex-math>$rm V_{FB}$ </tex-math></inline-formula> tuning technique in <inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula> high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> dielectric layers.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"546-552"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11271281","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148749818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact GaAs-Based Bandpass Filter Using Symmetric Multi-Stub Resonator","authors":"Yiqun Liu;Xiaoyu Weng;Ruoying Zhang;Tantan Zhao;Zeqiang Chen;Gaojian Liu","doi":"10.1109/JEDS.2026.3724289","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3724289","url":null,"abstract":"In this paper, a symmetric multi-stub resonator (SMSR) is proposed for the design of millimeter-wave on-chip bandpass filters (BPFs) with wide bandwidths, low insertion losses (ILs), and compact sizes. The multimode resonant characteristics are investigated and can be adjusted by varying the dimensions of the SMSR, enabling flexible control of the filtering responses. To validate the proposed idea, two BPF prototypes are designed and fabricated using a 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m gallium arsenide (GaAs) process. The measured results show that the fabricated devices operate at center frequencies of 51.3 GHz and 52 GHz, with 3-dB fractional bandwidths of 24.8% and 25.5%, and minimum in-band ILs of 1.07 dB and 1.1 dB, respectively. Excluding the G-S-G pads, the two proposed BPFs occupy core areas of only <inline-formula> <tex-math>$0.063~lambda _{0} times 0.042~lambda _{0}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$0.063~lambda _{0} times 0.055~lambda _{0}$ </tex-math></inline-formula>, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"771-776"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11657409","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simultaneous Measurement of Gate Switching Instability and Charge Pumping Current With Three-Level Stress Pulses in SiC MOSFETs","authors":"Matteo Nigris;Dick Scholten;Matteo Meneghini","doi":"10.1109/JEDS.2026.3712942","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3712942","url":null,"abstract":"Silicon Carbide (SiC) MOSFETs show a positive threshold voltage (<inline-formula> <tex-math>${V}_{th}$ </tex-math></inline-formula>) drift after prolonged gate switching stress (GSS), where the gate voltage is switched between a negative low level and a positive high level. This degradation phenomenon is referred to as gate switching instability (GSI), drawing a parallel to the bias temperature instability (BTI) observed in silicon MOSFETs. We developed a measurement setup to assess the charge pumping (CP) current during GSS. In dedicated on-wafer test structures, the increase in charge pumping current due to GSS consistently correlates with the threshold voltage drift. This finding supports the hypothesis that GSI is caused by the creation of acceptor-like interface traps. To explore the characteristics of the traps responsible for GSI, we developed a measurement procedure with three-level waveforms for GSS. With a low level of the stress waveform at −10 V, we observe that trap states near the valence band with an emission time constant between 20 ns and <inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula> s roughly account for 50% of the GSI-drift, whereas they account for more than 80% of the GSI-drift at a low level of −2 V. The time evolution of GSI is usually characterized by a power law with an exponent near the unity. However, with our setup, we discovered that the time progression of the GSI-induced degradation, excluding BTI effects, is more accurately represented by the combination of a power law with an exponent of about 0.2 to 0.3, and another power law with an exponent close to one. We dubbed the former power law “<italic>early-GSI</i>”.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"477-485"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11606491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Model for Hot-Electron Injection in the Passivation Layer of AlGaN/GaN HFETs Based on Monte Carlo Simulations","authors":"Pierpaolo Palestri;Luca Sayadi;Alessandro Ruggieri;Andrea Minetto;Gerhard Prechtl;Luca Selmi;Oliver Häberlen","doi":"10.1109/JEDS.2026.3714991","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3714991","url":null,"abstract":"We propose a lean model for hot-electrons in AlGaN/GaN HFETs, aimed at estimating the flux of carriers injected into the passivation layer above the AlGaN layer in the device drift region. Monte Carlo transport simulations are used to determine the hot-electron distribution and to verify the accuracy of the model equations. The model can be straightforwardly implemented into TCAD simulators to provide an estimate of the charge injected and/or trapped in the passivation during high drain voltage stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"516-524"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11614405","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}