Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu
{"title":"High-Precision GaN-Based-SenseFET Design Based on a Lumped Parameter Electro-Thermal Network Model","authors":"Xiaotian Tang;Qimeng Jiang;Sen Huang;Xinhua Wang;Xinyu Liu","doi":"10.1109/JEDS.2025.3563644","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3563644","url":null,"abstract":"The lossless and accurate current sensing technology is highly desirable for feedback control, fast over-current protection, and diagnostics-prognostics development for high-frequency and high-efficiency power systems. The SenseFET technology, where a current sensor is monolithically integrated with a power transistor, has been widely used in power ICs due to its high precision and low cost. However, for a gallium nitride (GaN) lateral power device in multi-finger configurations, the non-uniform temperature distribution hinders its application in high-precision scenarios. This paper aims to address this issue through a design method of SenseFETs based on a lumped parameter electro-thermal network (LPETN) model. Based on the proposed model, the time-dependent temperature and conduction current distribution are obtained, and the optimized finger selection for the accurate current sense is performed. The thermal network part of the model is validated by the finite element method (FEM) results, and the electrical part is validated through LTSPICE simulation. Finally, taking a 50-finger GaN high electron mobility transistor (HEMT) device as an example, this model is used to select the fingers of a SenseFET for current sensing. Compared with the traditional method, the proposed approach significantly improves the accuracy of the SenseFET, which demonstrates its effectiveness.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"414-421"},"PeriodicalIF":2.0,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10974612","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-Heating Effects in RF Region of FDSOI MOSFETs at Cryogenic Temperatures","authors":"Hung-Chi Han;Edoardo Charbon;Christian Enz","doi":"10.1109/JEDS.2025.3562752","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562752","url":null,"abstract":"Radio-frequency (RF) circuits are crucial to qubit manipulation, for which transistor self-heating effects may influence performance and possibly change the quantum state. This paper presents an analytical RF model of FDSOI MOSFETs considering dynamic self-heating effects down to 3.3 K for the first time. Parameter extraction involves analytical calculation and optimization using the iteratively re-weighted least squares (IRLS) and Monte Carlo methods. The temperature rise is estimated by capturing the correlation between thermal resistance and device temperature. This work provides a method for modeling FDSOI RF performance and for analyzing dynamic self-heating effects at cryogenic temperatures.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"396-405"},"PeriodicalIF":2.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970722","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Low Static-Power D Flip-Flop With Unipolar Thin Film Transistors on a Flexible Substrate","authors":"Shubham Ranjan;Sparsh Kapar;Czang-Ho Lee;William Wong;Manoj Sachdev","doi":"10.1109/JEDS.2025.3562575","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562575","url":null,"abstract":"There is increasing interest in affordable and flexible electronics, driven by the need for displays, conformable body sensors, and Internet-of-Things (IoT) gadgets. Amorphous silicon (a-Si:H), transition metal oxides, and organic thin-film transistors (TFTs) have demonstrated cost-effective large-scale production. As TFTs are typically unipolar in nature, they pose challenges for implementing CMOS-like circuits. Conventional methods to realize circuits in these technologies often lead to restricted voltage swing and excessive direct path current. While several methods have been proposed to counter the voltage swing issue, these methods fail to address the direct path current problem. This article presents low static-power D flip-flops (DFFs) using unipolar TFTs, which significantly reduces the direct path current. The proposed and conventional DFF designs were fabricated on a glass and flexible substrate using a-Si:H TFTs. Additionally, the impact of bending the flexible substrates was examined to assess the robustness and performance of the DFFs under mechanical strain. The measurement results show that the proposed design based DFF saves average total power by 79.8% compared to conventional design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"406-413"},"PeriodicalIF":2.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10970726","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143913349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliable Multistate RRAM Devices for Reconfigurable CAM and IMC Applications","authors":"Shengpeng Xing;Zijian Wang;Zhen Wang;Pengtao Li;Xuemeng Fan;Ziyang Zhang;Guobin Zhang;Jianhao Kan;Qi Luo;Shuai Zhong;Yishu Zhang","doi":"10.1109/JEDS.2025.3562399","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562399","url":null,"abstract":"This work presents a reliable multistate RRAM device based on a Cu/Ta2O5/WO<inline-formula> <tex-math>${}_{text {3-x}}$ </tex-math></inline-formula>/Pt structure, utilizing fully CMOS-compatible materials. The device demonstrates four distinct resistive states under varying switching voltages, achieving a swift response time of 25 ns and an on/off ratio exceeding <inline-formula> <tex-math>$10{^{{4}}}$ </tex-math></inline-formula>. Additionally, it demonstrates a robust data retention time exceeding <inline-formula> <tex-math>$10^{6}$ </tex-math></inline-formula> seconds and endures more than <inline-formula> <tex-math>$10^{4}$ </tex-math></inline-formula> pulses in endurance tests. Statistical analysis conducted over 100 cycles across ten devices reveals consistent resistance characteristics, with variations maintained below 10%. Leveraging these advantages, the RRAM devices were integrated with MOS transistors to construct a 4T2R unit-based array, enabling reconfigurable applications such as analog voltage-based content-addressable memory (CAM) and in-memory computing (IMC) accelerators. Notably, the proposed solution reduces energy consumption by over 20% in CAM applications and significantly enhances energy efficiency for fingerprint recognition tasks through convolution operations, achieving more than three times the energy efficiency compared to conventional GPU and CPU systems while maintaining an accuracy of 98%.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"383-389"},"PeriodicalIF":2.0,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10969850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":">3kV NiO/Ga2O3 Heterojunction Diodes With Space-Modulated Junction Termination Extension and Sub-1V Turn-On","authors":"Advait Gilankar;Abishek Katta;Nabasindhu Das;Nidhin Kurian Kalarickal","doi":"10.1109/JEDS.2025.3562028","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3562028","url":null,"abstract":"This work demonstrates high-performance vertical NiO/Ga2O3 heterojunction diodes (HJDs) with a 2-step space-modulated junction termination extension. Distinct from the current state-of-the-art Ga2O3 HJDs, we achieve breakdown voltage exceeding 3 kV with a low turn on voltage (VON) of 0.8V, estimated at a forward current density (IF) of 1 <inline-formula> <tex-math>$A-cm^{text {-2}}$ </tex-math></inline-formula>. The measured devices exhibit excellent turn-on characteristics achieving 100 <inline-formula> <tex-math>$A-cm^{text {-2}}$ </tex-math></inline-formula> current density at a forward bias of 1.5V along with a low differential specific on-resistance (Ron,sp) of 4.4 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-cm2. The SM-JTE was realized using concentric NiO rings with varying widths and spacing that approximates a gradual reduction in JTE charge. The unipolar figure of merit (FOM) calculated exceeds 2 GW-cm2 and is among the best reported for devices with a sub-1V turn-on. The fabricated devices also displayed minimal change in forward I-V characteristics post reverse bias stress of 3 kV applied during breakdown voltage testing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"373-377"},"PeriodicalIF":2.0,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10967383","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Call for Nominations for Editor-in-Chief IEEE Electron Device Letters","authors":"","doi":"10.1109/JEDS.2025.3558645","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3558645","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1076-1076"},"PeriodicalIF":2.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960702","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Call for Nominations for Editor-in-Chief IEEE Transactions on Electron Devices(TED)","authors":"","doi":"10.1109/JEDS.2025.3558646","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3558646","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1077-1077"},"PeriodicalIF":2.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960700","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Investigating Self-Heating Effects in Ferroelectric FinFETs for Reliable In-Memory Computing","authors":"Swati Deshwal;Shubham Kumar;Swetaki Chatterjee;Anirban Kar;Shivendra Singh Parihar;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/JEDS.2025.3559332","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3559332","url":null,"abstract":"Ferroelectric (Fe) FET has emerged as a promising candidate for efficient in-memory computing due to its properties, such as non-volatility and low power. However, scaled 3D devices such as Fe-FinFET suffer from significant self-heating effects (SHE) and process variations. These issues cause inconsistent performance and reduce reliability, limiting their applicability in high-performance applications like ternary content addressable memory (TCAM) and Hyperdimensional computing (HDC). In this paper, we explore the impact of SHE on 14 nm Fe-FinFETs using a cross-layer framework, analyzing how these effects and associated variations affect both circuit-level (TCAM cells) and system-level (HDC) performance. Our results reveal an increased error probability in Hamming distance (HD) calculations through the TCAM array when SHE and variations are present. Additionally, we demonstrate how SHE and variations influence the inference accuracy of the HDC framework.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"838-844"},"PeriodicalIF":2.4,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960387","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144764084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin
{"title":"Cryogenic InP HEMTs With Enhanced fmax and Reduced On-Resistance Using Double Recess","authors":"Yuxuan Chen;Fugui Zhou;Yongheng Gong;Yongbo Su;Wuchang Ding;Jingyuan Shi;Peng Ding;Zhi Jin","doi":"10.1109/JEDS.2025.3557432","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557432","url":null,"abstract":"Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device’s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device’s RON is <inline-formula> <tex-math>$410~Omega cdot mu $ </tex-math></inline-formula>m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device’s maximum oscillation frequency(<inline-formula> <tex-math>$f_{max }$ </tex-math></inline-formula>) by reducing the parasitic capacitance. At 7 K, the device’s <inline-formula> <tex-math>$f_{max }$ </tex-math></inline-formula> reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the <inline-formula> <tex-math>$rm Si_{3}N_{4}$ </tex-math></inline-formula> passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device’s cryogenic performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"366-372"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10948522","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jangseop Lee;Taras Ravsher;Daniele Garbin;Sergiu Clima;Robin Degraeve;Attilio Belmonte;Hyunsang Hwang;Inhee Lee
{"title":"Optimizing Pulse Conditions for Enhanced Memory Performance of Se-Based Selector-Only Memory","authors":"Jangseop Lee;Taras Ravsher;Daniele Garbin;Sergiu Clima;Robin Degraeve;Attilio Belmonte;Hyunsang Hwang;Inhee Lee","doi":"10.1109/JEDS.2025.3557732","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557732","url":null,"abstract":"In this study, we investigated the effect of pulse falling time (Tfall) on the electrical characteristics of SiGeAsSe-based selector-only memory (SOM) devices. Our experimental results demonstrate that increasing the <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> leads to an increased threshold voltage (Vth) and reduced <inline-formula> <tex-math>$mathrm { V_{th}}$ </tex-math></inline-formula> drift in SiGeAsSe devices. The optimized devices exhibit a remarkable memory window (> 1 V) and significantly suppressed drift characteristics (~10 mV/dec.). Electrical measurements at high temperatures demonstrate that <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> is one of the important factors in material relaxation, and these improvements are attributed to the intentionally induced reconfiguration of the chalcogenide film. Furthermore, our results reveal that a suitable <inline-formula> <tex-math>$mathrm { T_{fall}}$ </tex-math></inline-formula> can effectively mitigate the degradation of the memory window at high temperatures. These findings afford valuable insights into the role of material relaxation in SOM devices, potentially aiding the development of high-performance memory devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"362-365"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10949046","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143830515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}