IEEE Journal of the Electron Devices Society最新文献_第6页

Modeling the Increase in Effective Mobility in Short-Channel Oxide Thin-Film Transistors 短沟道氧化物薄膜晶体管有效迁移率增长建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-03 DOI: 10.1109/JEDS.2025.3557401

Oliver Durnan;Reem Alshanbari;Hong-Rae Cho;Ioannis Kymissis;Chang-Hyun Kim

引用次数: 0

Spike-Timing Dependent Learning Dynamics in Silicon-Doped Hafnium-Oxide-Based Ferroelectric Field Effect Transistors 掺硅氧化铪基铁电场效应晶体管的峰值时序依赖学习动力学

IF 2.4 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-01 DOI: 10.1109/JEDS.2025.3556675

Masud Rana Sk;Apu Das;Gautham Kumar;Deepanshi Bhatnagar;Sourodeep Roy;Yannick Raffel;Maximilian Lederer;Konrad Seidel;Sourav De;Bhaswar Chakrabarti

{"title":"Spike-Timing Dependent Learning Dynamics in Silicon-Doped Hafnium-Oxide-Based Ferroelectric Field Effect Transistors","authors":"Masud Rana Sk;Apu Das;Gautham Kumar;Deepanshi Bhatnagar;Sourodeep Roy;Yannick Raffel;Maximilian Lederer;Konrad Seidel;Sourav De;Bhaswar Chakrabarti","doi":"10.1109/JEDS.2025.3556675","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556675","url":null,"abstract":"Brain-inspired computing, with its potential for energy-efficient spatio-temporal data processing, has spurred significant interest in spiking neural networks and their hardware implementations. Leveraging their non-volatile memory and analog tunability, Ferroelectric field-effect transistors have emerged as promising candidates for realizing low-power synaptic devices within spiking neural networks. However, previous ferroelectric field-effect transistor-based implementations of spike-timing-dependent plasticity, a crucial learning mechanism in spiking neural networks, have often relied on complex circuit topologies or suffered from high energy consumption. Here, we report a comprehensive study of spike-timing-dependent plasticity learning dynamics in silicon-doped hafnium oxide-based ferroelectric field effect transistors, demonstrating precise control of synaptic weight modulation using various spike shapes and timings. We investigate the impact of different spike waveforms on energy consumption and find that triangular spikes achieve a 20% reduction in energy consumption compared to rectangular spikes, a significant improvement for large-scale spiking neural network implementations. Our results highlight the potential of single-device ferroelectric field-effect transistor synapses for realizing energy-efficient and scalable spiking neural networks, paving the way for next-generation neuromorphic computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"762-768"},"PeriodicalIF":2.4,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144764079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Proposal and Simulation of β-Ga₂O₃ Hetero- Junction Schottky Diodes With Low Work-Function Anode and High Breakdown Voltage 低功函数阳极高击穿电压β-Ga₂O₃异质结肖特基二极管的提出与仿真

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-04-01 DOI: 10.1109/JEDS.2025.3556408

Ce Wang;Hong Zhou;Sami Alghamdi;Chunxu Su;Zhihong Liu;Kui Dang;Xuefeng Zheng;Xiaohua Ma;Peijun Ma;Yue Hao;Jincheng Zhang

{"title":"Proposal and Simulation of β-Ga₂O₃ Hetero- Junction Schottky Diodes With Low Work-Function Anode and High Breakdown Voltage","authors":"Ce Wang;Hong Zhou;Sami Alghamdi;Chunxu Su;Zhihong Liu;Kui Dang;Xuefeng Zheng;Xiaohua Ma;Peijun Ma;Yue Hao;Jincheng Zhang","doi":"10.1109/JEDS.2025.3556408","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556408","url":null,"abstract":"In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (Von) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm2, simultaneously. The proposed structure provides a new approach for realizing high performance <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 SBDs with high reverse blocking and low loss capabilities.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"334-342"},"PeriodicalIF":2.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945755","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory 基于冲击电离的高耐久单晶体管CMOS低温存储器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-31 DOI: 10.1109/JEDS.2025.3552036

Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter

{"title":"Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory","authors":"Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter","doi":"10.1109/JEDS.2025.3552036","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552036","url":null,"abstract":"This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of (<inline-formula> <tex-math>$10{^{{7}}}~I_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{0}$ </tex-math></inline-formula> sense current ratio) and prolonged retention. The memory is enabled by the bistable <inline-formula> <tex-math>$I_{D}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V_{G}$ </tex-math></inline-formula> transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to <inline-formula> <tex-math>$approx ~45$ </tex-math></inline-formula> ns at T < 10 K and cycling endurance surpassing <inline-formula> <tex-math>$10^{9}$ </tex-math></inline-formula> cycles while maintaining the <inline-formula> <tex-math>$I_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{0}$ </tex-math></inline-formula> memory window. Retention times of >10 s with a 30x memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W-range) candidate for local cache memory to support quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"355-361"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10946245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors 应变工程二维 MoTe2 相变晶闸管的性能和可扩展性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-31 DOI: 10.1109/JEDS.2025.3556316

Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu

{"title":"Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors","authors":"Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu","doi":"10.1109/JEDS.2025.3556316","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556316","url":null,"abstract":"This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math>$leq 0.5$ </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math>$geq 10{^{{5}}}$ </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math>$leq 0.6mu $ </tex-math></inline-formula>m and A<inline-formula> <tex-math>$leq 0.3mu $ </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math>$leq 1.2mu $ </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math>$leq 65{^{text {o}}}$ </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"343-349"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945750","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts 具有源/漏金属触点的ML型和BL型MoS2 GAA NS场效应管的电特性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-29 DOI: 10.1109/JEDS.2025.3575015

Yueh-Ju Chan;Min-Hui Chuang;Yiming Li

{"title":"Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts","authors":"Yueh-Ju Chan;Min-Hui Chuang;Yiming Li","doi":"10.1109/JEDS.2025.3575015","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3575015","url":null,"abstract":"This paper reports source/drain (S/D) contact issues in monolayer and bilayer (BL) <inline-formula> <tex-math>$mathrm {MoS_{2}}$ </tex-math></inline-formula> devices through density-functional-theory (DFT) calculation and device simulation. We begin by analyzing material properties and van der Waals gaps at metal contacts of <inline-formula> <tex-math>$mathrm {MoS_{2}}$ </tex-math></inline-formula> using DFT calculation. These results are then used for device simulation, aligning closely with experimental data. For the first time, the model is extended to 3D gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) simulation, enabling contact resistance <inline-formula> <tex-math>$(R_{C})$ </tex-math></inline-formula> estimation. This work addresses key challenges by reducing computational demands compared to non-equilibrium Green function method and accurately calibrating devices with various metal contacts and gate lengths. Simulations with C-type S/D contacts achieve an <inline-formula> <tex-math>$R_{C}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$89.6~Omega $ </tex-math></inline-formula>-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m in 7-channel GAA BL <inline-formula> <tex-math>$mathrm {MoS_{2}}$ </tex-math></inline-formula> NS FETs, offering an interesting study for 2D material-based devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"485-493"},"PeriodicalIF":2.0,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017515","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144264230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Gamma Ray Irradiation on the Blocking Characteristics of Edge Termination on 4H-SiC and a Novel Anti-Ionizing Radiation Technology 伽玛射线辐照对4H-SiC封边特性的影响及一种新型抗电离辐射技术

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-28 DOI: 10.1109/JEDS.2025.3574497

Chuan-Han Chen;Bing-Yue Tsui;Der-Sheng Chao

引用次数: 0

AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications 多用途阶梯场极板漏极扩展FinFET的ai辅助设计

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-27 DOI: 10.1109/JEDS.2025.3555327

Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu

{"title":"AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications","authors":"Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu","doi":"10.1109/JEDS.2025.3555327","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3555327","url":null,"abstract":"Fin Field-Effect-Transistor (FinFET) has become fundamental components in advanced integrated circuit, while the drain-extended FinFET (DE-FinFET) features a lightly doped drain extension region to improve the device’s breakdown voltage. However, both structural refinement and the optimal integration of various parameters remain limited in achieving comprehensive optimization of device performance. This study introduces a novel DE-FinFET featuring a stepped field plate to improve overall performance of device. Moreover, within an AI-assisted design framework, predictive modeling and multi-objective optimization of the device are accomplished using Kolmogorov–Arnold Networks (KAN) and the Nondominated Sorting Genetic Algorithm (NSGA-III). More importantly, the proposed framework enables efficient device design and performance evaluation, achieving an average prediction accuracy of 98.19% for electrical performance metrics while being over two million times faster than traditional Technology Computer-Aided-Design (TCAD) simulations. In addition, it effectively generates Pareto-optimal solutions, delivering an average improvement of 9.03% across key electrical performance metrics. The proposed novel device of DE-FinFET offers a new route toward tailoring electrical properties. Meanwhile, the methodology of AI-assisted design not only accelerates device design but also enables customizable solutions for multi-purpose applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"326-333"},"PeriodicalIF":2.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10943177","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Non-Linear Partial Differential Equation Solver Based on Analog Memristor Crossbar Arrays 基于模拟忆阻交叉栅阵列的非线性偏微分方程求解器

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-26 DOI: 10.1109/JEDS.2025.3573409

Jiabao Ye;Bing Chen;Nuo Xu;Jiantao Zhou;Rongjun Mu;Chao Du;Wei D. Lu

引用次数: 0

Editorial for the J-EDS Special Issue for ESSERC 2024 ESSERC 2024 J-EDS特刊社论

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-21 DOI: 10.1109/JEDS.2025.3547035

Anne S. Verhulst

引用次数: 0