IEEE Journal of the Electron Devices Society最新文献

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Oxide Phototransistor Array With Multiply-and-Accumulation Functions for In-Sensor Image Processing 用于传感器内图像处理的具有乘法和累加函数的氧化物光电晶体管阵列
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-25 DOI: 10.1109/JEDS.2025.3545885
Saisai Wang;Xiaotao Jing;Wanlin Zhang;Rui Wang;Hong Wang;Qi Huang
{"title":"Oxide Phototransistor Array With Multiply-and-Accumulation Functions for In-Sensor Image Processing","authors":"Saisai Wang;Xiaotao Jing;Wanlin Zhang;Rui Wang;Hong Wang;Qi Huang","doi":"10.1109/JEDS.2025.3545885","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3545885","url":null,"abstract":"Advanced in-sensor computing paradigm has gradually become a research hotspot in this IOT era of sensor data proliferation. However, most existing in-sensor computing devices are plagued by a complex structure, and the uniformity of the sensor array is difficult to ensure. Moreover, photoconductive devices are incapable of achieving on-chip current summation because the regulation of photoresponsivity usually leads to inconsistent dark current, thereby impeding the practical implementation of artificial neural networks (ANNs) on the sensor array. In this work, we developed a <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> ultraviolet (UV) image sensor array based on solution-processed indium oxide (In2O3) phototransistors. The devices exhibit tunable responsivity and unified dark current under negative gate voltage (Vgs), enabling the direct execution of multiply-and-accumulation (MAC) operations. Consequently, two key applications of ANN were successfully demonstrated: image convolution and classification.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"378-382"},"PeriodicalIF":2.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10904187","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Power a-IGZO TFT Emission Driver With Shoot-Through Current-Free QB Control Block 具有通射无电流QB控制块的低功耗a-IGZO TFT发射驱动器
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-24 DOI: 10.1109/JEDS.2025.3544840
Won-Been Jeong;Sang-Hoon Kim;Seung-Woo Lee
{"title":"Low-Power a-IGZO TFT Emission Driver With Shoot-Through Current-Free QB Control Block","authors":"Won-Been Jeong;Sang-Hoon Kim;Seung-Woo Lee","doi":"10.1109/JEDS.2025.3544840","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3544840","url":null,"abstract":"This paper proposes an emission driver for active-matrix organic light emitting diode (AMOLED) displays using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs). The proposed circuit effectively eliminates shoot-through current in QB control block, achieving 97% reduction in power consumption compared to conventional one. It stably operates in both depletion and enhancement modes and supports pulse-width modulation (PWM) driving for better low gray level expression of AMOLED displays. Simulation results show that the proposed circuit has the robust performance for high-resolution AMOLED displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"139-144"},"PeriodicalIF":2.0,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10899845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization and Modeling of MOSFET Series Resistance Down to 4 K 低至4k的MOSFET串联电阻的表征与建模
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-21 DOI: 10.1109/JEDS.2025.3544738
Yuhuan Lin;Zhizhao Ma;Shilong Li;Tianyue Wen;Yuxuan Zhou;Hao Su;Shenghua Zhou;Longyang Lin;Yida Li;Kai Chen
{"title":"Characterization and Modeling of MOSFET Series Resistance Down to 4 K","authors":"Yuhuan Lin;Zhizhao Ma;Shilong Li;Tianyue Wen;Yuxuan Zhou;Hao Su;Shenghua Zhou;Longyang Lin;Yida Li;Kai Chen","doi":"10.1109/JEDS.2025.3544738","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3544738","url":null,"abstract":"MOSFET parasitic series resistance <inline-formula> <tex-math>$({R}_{SD})$ </tex-math></inline-formula> is an important parameter when channel length scales down. This paper presents a systematic study of <inline-formula> <tex-math>${R}_{SD}$ </tex-math></inline-formula> extracted from the mobility constant method down to 4 K. For the first time, the anomalous behavior of <inline-formula> <tex-math>${R}_{SD}$ </tex-math></inline-formula> with temperature lowering is interpreted and modeled by combined effects of dopant freeze-out and mobility. Excellent fit between the standard N/P-MOSFET measurement data and this model for 40 nm bulk device from leading foundry is shown from 300 K to 4 K. In addition, <inline-formula> <tex-math>${R}_{SD}$ </tex-math></inline-formula> change with width scaling combined with temperature effects is also discussed.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"297-302"},"PeriodicalIF":2.0,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10899824","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of an Integrated MEMS Magnetic Gradiometer Rejecting Vibrations and Stray Fields 抑制振动和杂散场的集成MEMS磁梯度计设计
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-19 DOI: 10.1109/JEDS.2025.3543662
Enrico Gasparin;Arno Hoogerwerf;Dara Bayat;Guido Spinola Durante;Yves Petremand;Maurizio Tormen;Michel Despont;Gaël Close
{"title":"Design of an Integrated MEMS Magnetic Gradiometer Rejecting Vibrations and Stray Fields","authors":"Enrico Gasparin;Arno Hoogerwerf;Dara Bayat;Guido Spinola Durante;Yves Petremand;Maurizio Tormen;Michel Despont;Gaël Close","doi":"10.1109/JEDS.2025.3543662","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543662","url":null,"abstract":"Magnetic sensors are often used near current-carrying wires or electrical motors generating significant magnetic interference. To mitigate the effects of these stray fields, the traditional design approach relies on a differential sensing scheme: multiple magnetometers are spaced apart, and the field differences are measured. Despite being rejected, stray fields still constrain the design space. Extra linear range and matched channels are required to accommodate their peak amplitude without saturation or residual common-mode leakage. On the contrary, single-point MEMS gradiometers rely on the force acting on a magnet, which is directly proportional to the magnetic field gradient. The stray field is intrinsically rejected by the magnetic transducing mechanism, even before entering the measurement chain. The range of the measurement chain can then be largely optimized for the gradient, independently of the stray field amplitude. This paper discusses the design of a single-point MEMS gradiometer. By design, it rejects magnetic stray fields and mechanical disturbances like vibrations and gravity. It is the first single-point MEMS gradiometer capable of operating unshielded and in various orientations. The prototype achieves a noise density of 4 nT/mm/<inline-formula> <tex-math>$sqrt {mathrm { Hz}}$ </tex-math></inline-formula> within a measurement range of <inline-formula> <tex-math>${pm } 300~{mu }$ </tex-math></inline-formula>T/mm. The paper demonstrates the sensor’s effectiveness in a bus-bar current sensing application. Design limitations and future design prospects are also outlined.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"228-236"},"PeriodicalIF":2.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892099","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays 基于有机TFTs的高鲁棒集成栅极驱动器用于有源矩阵显示器
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-18 DOI: 10.1109/JEDS.2025.3542951
Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li
{"title":"A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays","authors":"Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li","doi":"10.1109/JEDS.2025.3542951","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542951","url":null,"abstract":"A highly robust integrated gate driver based on organic thin-film transistors (OTFTs) is proposed that effectively addresses the output degradation caused by depletion-mode operation, instability and variation. The series-connected two-transistor structures and the inverters generate positive gateto- source voltages for internal nodes, which eliminate the leakage current and voltage ripples in depletion-mode operation and extend the support threshold voltage (<inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula>) range. The simulation waveforms of the 538th stage have no degradation, considering the <inline-formula> <tex-math>$Delta V_{TH}$ </tex-math></inline-formula> range from 1.18 to -0.53 V for single-gate (SG) OTFT and that from 2.13 to -8.07 V for dual-gate (DG) OTFT. The fabricated gate drivers generate stable scan signals with almost negligible voltage ripples for SG- and DG-OTFT with <inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula> of +7.9 and +1.8 V, respectively. In a 5.8-inch AMOLED panel (resolution: 538×302), the circuit can operate at a frame rate range from 1 to 45 Hz, driven by clocks with a frequency of 12.5 kHz and a swing from 0 to -15 V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"128-133"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891473","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-Aligned Staggered Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors With Ultra-Low Contact Resistance for High-Speed Circuits Application 自对准交错非晶铟镓锌氧化物薄膜晶体管的超低接触电阻应用于高速电路
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-18 DOI: 10.1109/JEDS.2025.3543212
Chuanke Chen;Xinlv Duan;Congyan Lu;Xichen Chuai;Wanming Wu;Chunyu Zhang;Chen Gu;Guanhua Yang;Nianduan Lu;Di Geng;Ling Li
{"title":"Self-Aligned Staggered Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors With Ultra-Low Contact Resistance for High-Speed Circuits Application","authors":"Chuanke Chen;Xinlv Duan;Congyan Lu;Xichen Chuai;Wanming Wu;Chunyu Zhang;Chen Gu;Guanhua Yang;Nianduan Lu;Di Geng;Ling Li","doi":"10.1109/JEDS.2025.3543212","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543212","url":null,"abstract":"A self-aligned (SA) staggered structure for amorphous-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is proposed. The bottom contact between n+-IGZO and source/drain (S/D) enables larger contact area and shorter current-transmission distance, thus reducing the contact resistance. The non-overlap structure helps to eliminate the overlap-induced parasitic capacitance, thereby improving the device operating speed. The fabricated SA staggered a-IGZO TFTs exhibit good performance, including channel-width-normalized contact resistance (RCW) as low as 1.53 <inline-formula> <tex-math>$Omega cdot mathrm{~cm}$ </tex-math></inline-formula> and transit frequency (fT) as high as 1.4 GHz, which are quite competitive in the field of high-speed a-IGZO TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"135-138"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891703","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform for Reliable Cryogenic IC Design 通用低温CMOS器件建模和eda兼容平台的可靠低温IC设计
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-17 DOI: 10.1109/JEDS.2025.3542589
Zhidong Tang;Zewei Wang;Yumeng Yuan;Chang He;Xin Luo;Ao Guo;Renhe Chen;Yongqi Hu;Longfei Yang;Chengwei Cao;Lin Lin Liu;Liujiang Yu;Ganbing Shang;Yongfeng Cao;Shoumian Chen;Yuhang Zhao;Shaojian Hu;Xufeng Kou
{"title":"Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform for Reliable Cryogenic IC Design","authors":"Zhidong Tang;Zewei Wang;Yumeng Yuan;Chang He;Xin Luo;Ao Guo;Renhe Chen;Yongqi Hu;Longfei Yang;Chengwei Cao;Lin Lin Liu;Liujiang Yu;Ganbing Shang;Yongfeng Cao;Shoumian Chen;Yuhang Zhao;Shaojian Hu;Xufeng Kou","doi":"10.1109/JEDS.2025.3542589","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542589","url":null,"abstract":"This paper outlines the establishment of a generic cryogenic CMOS database in which key electrical parameters and transfer characteristics of the MOSFETs are quantified as functions of device size, temperature/frequency responses. Meanwhile, comprehensive device statistical analysis is conducted to evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS compact model into the process design kit (PDK), the cryogenic 4 Kb SRAM and 5-bit flash ADC are designed, and their performance is investigated and optimized based on the EDA-compatible platform, hence laying a solid foundation for large-scale cryogenic IC design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"117-127"},"PeriodicalIF":2.0,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Harmonic Enhancement of Terahertz GaN Planar Gunn Oscillators With Multiple Gates 多门太赫兹GaN平面Gunn振荡器的谐波增强
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-17 DOI: 10.1109/JEDS.2025.3543017
Ying Wang;Shuai Hui;Yu-Xin Fu;Yuan-Zhu Xia;He Guan
{"title":"Harmonic Enhancement of Terahertz GaN Planar Gunn Oscillators With Multiple Gates","authors":"Ying Wang;Shuai Hui;Yu-Xin Fu;Yuan-Zhu Xia;He Guan","doi":"10.1109/JEDS.2025.3543017","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543017","url":null,"abstract":"In this paper, we propose a novel design of GaN-based planar Gunn oscillator as terahertz signal source. The oscillator has multiple gates and each gate can be individually biased. By controlling gate bias voltage and distance to the barrier layer, the output oscillating current can be formed in such a way that the higher harmonics are more powerful than the fundamental one. This is because multiple Gunn domains created under the gates in the channel are synchronized. Compared to the conventional single-domain diode, this multi-gate configuration not only increases the frequency and output power but also provides superior harmonic control, leading to higher efficiency and more stable operation at terahertz frequencies. We will review the design details and analysis on domain forming conditions using a physics-based numerical model. The optimal parameters for high power, high DC-RF conversion efficiency and high frequency will be given. Specifically, in dual-gate device, when it works in the dual-domain mode, the second harmonic is enhanced, reaching a frequency of 310.5 GHz with 7.6 mW of power and 11.2% efficiency. The tri-gate device operating in tri-domain mode further enhances the third harmonic to 417.0 GHz, with 9.57 mW of power and 9.23% efficiency. The multi-gate structure allows for more efficient harmonic generation, greater frequency tunability, and better power management, all of which are crucial for advanced terahertz application such as mixing, frequency multiplexing, and signal amplification.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"145-153"},"PeriodicalIF":2.0,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of van der Waals-Based Photovoltaic Devices 基于范德华的光伏设备建模
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-14 DOI: 10.1109/JEDS.2025.3542168
Ángel A. Díaz-Burgos;Enrique G. Marin;Francisco Pasadas;Francisco G. Ruiz;Andrés Godoy
{"title":"Modeling of van der Waals-Based Photovoltaic Devices","authors":"Ángel A. Díaz-Burgos;Enrique G. Marin;Francisco Pasadas;Francisco G. Ruiz;Andrés Godoy","doi":"10.1109/JEDS.2025.3542168","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542168","url":null,"abstract":"Two-dimensional Transition Metal Dichalcogenide-based van der Waals heterostructures have been proposed for avant-garde, highly scalable optoelectronic and excitonic devices. Although ab initio techniques have been thoroughly employed to analyze these confined systems from a microscopic perspective, a robust mesoscopic description for device-scale simulation is still lacking. In this work, we account for the recent reports on the role of interlayer excitons and the band alignment in van der Waals-based optoelectronic devices, developing an extended van Roosbroeck system within the framework of the Drift-Diffusion approximation. Ultrafast interlayer charge transfer of photo-generated carriers is incorporated effectively, as is interlayer recombination. This description succeeds in reproducing selected experimental measurements of a van der Waals-based gated-diode, providing a comprehensive physical description of the involved magnitudes.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"219-227"},"PeriodicalIF":2.0,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10887203","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm² 具有高可靠性和685 MW/cm²功率特性的3kv GaN MISHEMT
IF 2 3区 工程技术
IEEE Journal of the Electron Devices Society Pub Date : 2025-02-13 DOI: 10.1109/JEDS.2025.3533920
Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu
{"title":"A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm²","authors":"Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2025.3533920","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3533920","url":null,"abstract":"In this letter, GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) are fabricated on Si substrates with an ultra-high breakdown voltage of over 3 kV using a 90-nm in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> layer as both the gate dielectric and surface passivation. The devices exhibit low off-state leakage current (on/off ratio of <inline-formula> <tex-math>$10{^{{9}}}$ </tex-math></inline-formula>), high forward gate breakdown voltage (>122 V), and state-of-the-art figure of merit (685 MW/cm2). Moreover, the reliability of the in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> dielectric is evaluated through the high-temperature gate bias test. The results are fitted with a Weibull distribution, estimating a 10-year estimation of 100 ppm. The maximum gate-source voltage of over 70 V is obtained. This letter presents a strategy for mass producing GaN-on-Si MISHEMTs with high breakdown voltage and reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"106-111"},"PeriodicalIF":2.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10886964","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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