IEEE Journal of the Electron Devices Society最新文献

{"title":"Junction-Selective Hysteretic Conductance Modulation at the C–B Interface of a Thin-Film BJT","authors":"Emad Iranmanesh;Zuhao Li;Yuanhao Xia;Mingzhe Song;Charalabos Doumanidis;Hang Zhou","doi":"10.1109/JEDS.2026.3710724","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3710724","url":null,"abstract":"Thin-film bipolar junction transistors provide a compact platform for integrating multiple electronic functions within a single vertical device structure. Here, we demonstrate junction-selective hysteretic conductance modulation localized at the collector–base (C–B) junction of a thin-film BJT fabricated using an asymmetric ITO/ZnO/P3HT/ZnO heterostructure on a flexible substrate. Electrical measurements reveal repeatable bias-history-dependent current–voltage behavior confined to the C–B junction, accompanied by cycle-dependent conductance evolution, while the emitter–base (E–B) junction maintains stable injection-dominated transport and preserved transistor amplification before and after C–B electrical stressing. Dwell-time-dependent measurements reveal a systematic dependence on voltage dwell time, consistent with a kinetically limited interfacial process and field-assisted barrier modulation at the C–B junction. The demonstrated junction-selective behavior establishes a thin-film transistor architecture in which localized conductance modulation and transistor operation coexist within the same device structure.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"450-458"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11598892","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Voltage Normally-Off β-Ga2O3 MOSFETs With 10-nm Ultrathin Heavily Doped Channels","authors":"Rui Shen;Chongde Zhang;Xinxin Yu;Zhonghui Li;Tengfei Gu;Mingfei Li;Ao Liu;Likun Zhou;Bing Qiao;Yuechan Kong;Tangsheng Chen;Shulin Gu;Rong Zhang;Jiandong Ye","doi":"10.1109/JEDS.2026.3739566","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3739566","url":null,"abstract":"Enhancement-mode (E-mode) Ga2O3 field-effect transistors (FETs) are highly desirable for safe and efficient power electronics, yet achieving normally-off operation remains challenging due to the difficulty of fully depleting carriers in thick bulk-doped channels and the absence of effective p-type doping. In this work, we demonstrate high-voltage E-mode <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) enabled by 10nm ultrathin heavily Si-doped (<inline-formula> <tex-math>$sim 1times 10 ^{19}$ </tex-math></inline-formula> cm−3) channels grown by metalorganic chemical vapor deposition (MOCVD). The ultrathin-channel design, assisted by a high-work-function gate metal and fluorine plasma treatment, fully depletes the channel at zero gate bias without gate recessing or heterojunction gates. The device with gate to drain spacing (<inline-formula> <tex-math>$L_{mathrm {GD}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>m exhibits a threshold voltage (<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>) of 4.5 V, a specific on-resistance (<inline-formula> <tex-math>$R_{mathrm {on,sp}}$ </tex-math></inline-formula>) of 29.04 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2, a breakdown voltage (<inline-formula> <tex-math>$V_{mathrm {br}}$ </tex-math></inline-formula>) of 1440 V and a corresponding power figure of merit (PFOM) of 71.4 MW/cm2 While extending <inline-formula> <tex-math>$L_{mathrm {GD}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$16~mu $ </tex-math></inline-formula>m, the <inline-formula> <tex-math>$V_{mathrm {br}}$ </tex-math></inline-formula> was increased to 2530 V - a record high for lateral E-mode <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 MOSFET without field plates This etch-free design minimizes interface damage and provides a scalable pathway for high-voltage normally-off Ga2O3 power electronics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"898-902"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11719563","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149249429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Power Loss in the Substrate on the Efficiency of RF GaN-on-Si HEMTs","authors":"Pieter Cardinael;Alexis Divay;Ismael Charlet;Yveline Gobil;Erwan Morvan;Jean-Pierre Raskin","doi":"10.1109/JEDS.2026.3678426","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3678426","url":null,"abstract":"In RF GaN-on-Si technology, the semiconducting Si substrate can couple to the overlying circuitry and cause substrate loss, which is known to degrade the performance of passive structures. An impact on active devices also exists. This paper presents the first experimental correlation between insertion loss measured on coplanar waveguide (CPW) lines and a degradation in the power added efficiency (PAE) of GaN-on-Si HEMTs. To quantify the PAE penalty suffered by using a lossy substrate, we propose a simple simulation procedure which accounts for the presence of a parasitic surface conductance (PSC) layer at the surface of the high resistivity Si. The simulated substrate, which can accurately reproduce the CPW line measurements of different wafers, is then used to generate an aggregated substrate resistance. A simple model of the power amplifier (PA) allows to estimate the PAE drop caused by power dissipation in the substrate. The simulated substrate impact, which can be as high as 15 PAE percentage points at 28 GHz, matches the experimentally observed difference between HEMTs fabricated on different substrates. Furthermore, the physics-based simulation enables analysis of operating frequency and dopant diffusion effects in Si. Finally, a specification on substrate effective resistivity for a negligible substrate impact on the PA is given.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"234-241"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11456867","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of FDSOI Technology for Energy-Efficient Cryo-CMOS Circuits","authors":"Arpit Rao;David R. Daughton;Benjamin Chacko;Jason Chonko;Yukang Kuang;Sarah Guenther;Subhanshu Gupta","doi":"10.1109/JEDS.2026.3679963","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3679963","url":null,"abstract":"High-performance cryo-CMOS circuits are the foundation for quantum computing hardware. The energy efficiency of cryo-CMOS circuits is limited by the changing operating point of the device as the temperature drops. Operating point calibration becomes imperative to achieve energy-efficient designs, yet accurate threshold-voltage calibration at deep-cryogenic temperatures proves challenging. At cryogenic temperatures, conventional threshold-voltage extraction methods fail as the device operating point exhibits a nonlinear shift with temperature, rendering standard threshold voltage extraction methods unreliable, particularly in the low-<inline-formula> <tex-math>$V_{mathrm {GS}}$ </tex-math></inline-formula> regime where cryo-CMOS circuits are typically biased for energy efficiency. This work characterizes flip-well 22 nm FDSOI technology and demonstrates a robust methodology for operating point calibration using back-gate control across a variety of <inline-formula> <tex-math>$V_{mathrm {DS}}$ </tex-math></inline-formula>. Established extraction methods, including constant current, maximum transconductance, second-derivative, third-derivative, linear extraction, and transconductance-to-current ratio, are performed to assess their applicability under cryogenic conditions. In doing so, we demonstrate that back-gate tuning provides an effective and scalable mechanism for compensating operating-point shifts without emphasis on the absolute value of the threshold voltage. Calibrated threshold voltage results across temperature are presented for a 22 nm FDSOI super-low-VT (SLVT) transistor using body bias sweeps from 0 to + 2 V. To enable circuit-level calibration in the low-<inline-formula> <tex-math>$V_{mathrm {GS}}$ </tex-math></inline-formula> regime, this work identifies the body-coefficient <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> as a relevant metric for biasing, capturing the effective sensitivity of gate threshold voltage to back-gate bias. The extracted <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> exhibits nonlinearity with respect to both temperature and bias conditions, providing a physically meaningful and design-relevant parameter for energy-efficient cryo-CMOS calibration.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"213-224"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11459433","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FDSOI-Based Cryogenic Circuit Performance Enhancement Using Back-Biasing and Threshold Voltage Engineering","authors":"Tapas Dutta;Fikru Adamu-Lema;Djamel Bensouiah;German Cherstvov;Plamen Asenov;Asen Asenov","doi":"10.1109/JEDS.2026.3691285","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3691285","url":null,"abstract":"In this work, we use predictive cryogenic spice based compact models derived using a process design kit re-centering approach for 22 nm FDSOI technology to analyze the impact of back-gate biasing on circuit performance. We focus on analysis of power-delay trade-offs while varying the supply voltage at room and cryogenic temperature (4K). We show that back-biasing is necessary to mitigate the effects of the higher threshold voltages observed at cryogenic temperature. We further show that simple “threshold voltage engineering” has the potential to provide much better performance, compared to room temperature.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"268-273"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11513225","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Trade-off of Program Speed and Z-Interference According to Trap Position in 3-D NAND Flash Memory","authors":"Gyuhyeon Lee;Minseok Kim;Jesun Park;Seung Jae Baik;Myounggon Kang","doi":"10.1109/JEDS.2026.3695129","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3695129","url":null,"abstract":"This work proposes a distance-dependent trap model to overcome the limitations of conventional Technology Computer-Aided Design (TCAD) models, which fail to accurately represent the non-uniform charge distribution resulting from electron energy relaxation under strong tunneling conditions in 3D NAND flash memories. By incorporating a spatially varying capture cross-section within the charge trap layer (CTL), the model effectively captures trap centroid shifts under realistic programming conditions. Implemented through the physical model interface (PMI) in Sentaurus TCAD, this model shows significantly improved alignment with experimental data for incremental step pulse programming (ISPP) characteristics when compared to the conventional Shockley-Read-Hall (SRH) model. Additionally, a systematic analysis of trap distribution effects on programming speed and Z-interference is conducted. The results indicate a clear trade-off: traps located near the tunneling oxide (TOX) enhance programming speed but increase Z-interference, whereas traps near the blocking oxide (BOX) reduce Z-interference, but with slower programming speeds. These findings demonstrate the importance of precise control over trap distribution to optimize the performance and reliability of 3D NAND Flash memories.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"339-345"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11527313","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Performance ZTO:F Thin-Film Transistor via Optimization of Damage-Free In-Situ F-Doping","authors":"Xuemei Yin;Wei Huang;Wei Zhong;Yayi Chen;Yi Li;Delang Lin","doi":"10.1109/JEDS.2026.3701726","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3701726","url":null,"abstract":"Zinc tin oxide (ZTO) is a highly promising active-layer material for metal oxide thin-film transistors (MO TFTs) due to its low cost, absence of precious metals, and environmental friendliness. However, owing to its low intrinsic carrier concentration, ZTO materials typically exhibit relatively low carrier mobility. Doping is the most common method for modifying thin films to enhance their performance, but conventional plasma doping causes high surface damage. To address this drawback, this work proposes a damage-free in-situ fluorine-doping technique based on co-sputtering. We investigated the mechanisms by which key process parameters influence film and device performance, and ZTO:F films and devices achieve optimal performance through process optimization. The ZTO:F TFT with optimal performance was obtained under conditions of <inline-formula> <tex-math>$P_{mathrm {FTO}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$P_{mathrm {ZnO}}~ text = 25$ </tex-math></inline-formula> W/75 W, <inline-formula> <tex-math>$P_{mathrm {O2}}$ </tex-math></inline-formula> of 5%, sputtering pressure of 1.5 Pa, and annealing at <inline-formula> <tex-math>$350~^{circ }$ </tex-math></inline-formula>C, exhibiting a saturation mobility (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>sat) of 14.2 cm2V−1s−1, a turn-on voltage (<inline-formula> <tex-math>$V_{mathrm {on}}$ </tex-math></inline-formula>) of 0 V, a subthreshold slope (SS) of 0.089 V/dec, and an <inline-formula> <tex-math>$I_{mathrm {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{mathrm {off}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$2.47times 10^{9}$ </tex-math></inline-formula>. This further expands the potential for applying ZTO in scenarios with stringent performance requirements.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"408-415"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11556147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Enhancement of Schottky Barrier MOSFET by Laser-Induced Low Temperature Dopant Segregation for Monolithic-3D Integration","authors":"Feixiong Wang;Yadong Zhang;Jinbiao Liu;Shuang Liu;Yunjiao Bao;Shujuan Mao;Mingzheng Ding;Zhaohao Zhang;Jiaxin Yao;Qingzhu Zhang;Huaxiang Yin","doi":"10.1109/JEDS.2025.3602898","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3602898","url":null,"abstract":"Monolithic 3-Dimensional (M3D) integration has emerged as a promising approach to extend Moore’s Law. However, overcoming the thermal limitations associated with fabricating top-tier devices remains a significant challenge. In this study, laser-induced silicide dopant segregation (LSDS) source/drain (S/D) technology is explored to optimize the performance of low thermal budget (Low-TB, <inline-formula> <tex-math>$leq 500$ </tex-math></inline-formula> °C for 2 hours) Schottky Barrier MOSFET fabricated as top-tier devices for M3D integration. A nanosecond-pulsed green laser is employed to induce dopant segregation in Schottky S/D regions, resulting in a sharpened interface with a high Schottky barrier and elevated impurity concentration. This process enables the fabrication of high-performance CMOS devices, achieving I<inline-formula> <tex-math>${}_{ON}~{gt }$ </tex-math></inline-formula> <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m at <inline-formula> <tex-math>$L_{G} {=} 500$ </tex-math></inline-formula> nm with limited variation. Experimental results show that the S/D series resistance is reduced by 28.7% and 11.9% for N and P MOSFETs at 1.0 J/cm2 compared to the conventional rapid thermal annealing (RTA) process. Furthermore, inverters, ring oscillators, and logic gates are successfully demonstrated, showing the multi-functionality of this approach and its potential as an alternative fabrication scheme for M3D circuit applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"621-627"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142297","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Dislocations on Minority Carrier Lifetime in 300-mm Si Wafers During a High Thermal Budget Process","authors":"Jiuyang Yuan;Bozhou Cai;Yoshiji Miyamura;Wataru Saito;Shin-Ichi NIshizawa","doi":"10.1109/JEDS.2025.3637754","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3637754","url":null,"abstract":"A quantitatively analysis of the impact of process-induced dislocations on minority carrier lifetime in 300-mm Si wafer was presented. High thermal budget processes, such as oxidation and impurity diffusion, are essential in Insulated Gate Bipolar Transistor (IGBT) fabrication but can induce dislocations in large-diameter Si wafers. These dislocations may degrade the minority carrier lifetime, directly impairing device performance. Therefore, establishing a quantitative relationship between dislocation density and lifetime is crucial for process control and yield improvement. In this paper, we first demonstrate that dislocation propagation during thermal processes can be effectively suppressed by controlling the magnitude of a parameter “f”, which represents the dislocation propagation rate. Subsequently, wafers with varying dislocation density were fabricated through a series of consecutive thermal cycles. The dislocation density was determined by numerical calculation, while the corresponding minority carrier lifetime was measured using the micro-photoconductivity decay (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>-PCD) method. A quantitative correlation between dislocation density and lifetime was established. These findings contribute to preventing dislocation-induced lifetime degradation during high thermal budget process in power device manufacturing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"553-560"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11269314","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deterministic Precessional MRAM With Low Write Error Rate: Fokker-Planck Modeling and Design Optimization","authors":"Stanislav Sin;Saeroonter Oh","doi":"10.1109/JEDS.2025.3648736","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3648736","url":null,"abstract":"Magnetoresistive memory has matured into a commercially viable technology, with current-controlled spin-transfer torque (STT) MRAM serving as an industry standard for spintronics due to its good performance metrics and compatibility with silicon transistors. However, STT MRAM requires large current densities, resulting in limited scalability and energy inefficiency. Voltage-controlled precessional (VCP) MRAM can mitigate this problem by reducing current requirements by two orders of magnitude, but suffers from high write error rate (WER) due to sensitivity to the write pulse duration (WPD) and process and temperature variations. To overcome these limitations, we propose a voltage-controlled deterministic precessional (VCDP) MRAM, which realizes robust deterministic switching via magnetoresistance-induced energy asymmetry. Fokker-Planck simulations confirm low WER of <inline-formula> <tex-math>$10^{-9}$ </tex-math></inline-formula> with a WPD of 23.7 ns and energy consumption of <inline-formula> <tex-math>$sim ~110.9$ </tex-math></inline-formula> fJ/bit, validating VCDP MRAM as a promising candidate for storage-class or main memory applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"660-667"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11316333","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}