IEEE Journal of the Electron Devices Society最新文献_第6页

Investigation on the Dynamic Characteristics of Hydrogen Plasma Treated p-GaN HEMTs Circuit Using ASM-GaN Model 利用 ASM-GaN 模型研究氢等离子体处理 p-GaN HEMT 电路的动态特性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-03 DOI: 10.1109/JEDS.2024.3407098

Fan Li;Shiqiang Wu;Ang Li;Yuhao Zhu;Miao Cui;Jiangmin Gu;Ping Zhang;Yinchao Zhao;Huiqing Wen;Wen Liu

{"title":"Investigation on the Dynamic Characteristics of Hydrogen Plasma Treated p-GaN HEMTs Circuit Using ASM-GaN Model","authors":"Fan Li;Shiqiang Wu;Ang Li;Yuhao Zhu;Miao Cui;Jiangmin Gu;Ping Zhang;Yinchao Zhao;Huiqing Wen;Wen Liu","doi":"10.1109/JEDS.2024.3407098","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3407098","url":null,"abstract":"This study demonstrates the first work that achieves accurate modeling of Hydrogen plasmatreated (H-treated) p-GaN gate devices with the ASM-GaN model, facilitating simulations for applications in monolithic integrated circuit (IC) design. The workflow for ASM-GaN model parameter extraction and optimization using IC-CAP is proposed. The I-V characteristics of both Enhancement / Depletion (E/D) mode devices are modeled and fitted. The impact of device capacitance on the dynamic properties of monolithic IC is investigated through the ASM model. The results demonstrate that Cds, Cgd, and Cgs have different effects on the monolithic logic circuit performances. The high-level fitting of experimental data and circuit simulation of Inverter, NAND, and Comparator circuits proves the credibility of the modeling workflow and device capacitance modulation. This work provides a method to speed up the GaN monolithic IC design by accurate modeling with fast parameter extraction workflow regardless of the fabrication process. The reliable prediction of the circuit’s dynamic performance will lay the foundation for designing and scaling up the GaN monolithic IC application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10543269","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A General Toolkit for Advanced Semiconductor Transistors: From Simulation to Machine Learning 先进半导体晶体管通用工具包：从模拟到机器学习

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-05-16 DOI: 10.1109/jeds.2024.3401852

Antonio J. García-Loureiro, Natalia Seoane, Julian G. Fernández, Enrique Comesaña

引用次数: 0

HCMS: A Hybrid Conductance Modulation Scheme Based on Cell-to-Cell Z-Interference for 3D NAND Neuromorphic Computing HCMS：基于细胞间 Z 干涉的混合电导调制方案，用于 3D NAND 神经形态计算

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-05-06 DOI: 10.1109/jeds.2024.3397005

Anyi Zhu, Lei Jin, Jianquan Jia, Tianchun Ye, Ming Zeng, Zongliang Huo

引用次数: 0

Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology 65 纳米 CMOS 技术的低温小尺寸效应和面向设计的可扩展紧凑型建模

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-26 DOI: 10.1109/JEDS.2024.3394167

Alberto Gatti;Filip Tavernier

引用次数: 0

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory 用于可靠无电容存储器的独立双栅 BEOL 晶体管的基于物理的紧凑模型

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-25 DOI: 10.1109/JEDS.2024.3393418

Lihua Xu;Kaifei Chen;Zhi Li;Yue Zhao;Lingfei Wang;Ling Li

{"title":"Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory","authors":"Lihua Xu;Kaifei Chen;Zhi Li;Yue Zhao;Lingfei Wang;Ling Li","doi":"10.1109/JEDS.2024.3393418","DOIUrl":"10.1109/JEDS.2024.3393418","url":null,"abstract":"Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi-gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to \u0000<inline-formula> <tex-math>$sim ~50$ </tex-math></inline-formula>\u0000 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation-resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10508593","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140806832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Heat Generation Mechanisms of Self-Heating Effects in SOI-MOS SOI-MOS 中自热效应的发热机制

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-24 DOI: 10.1109/JEDS.2024.3393019

Zheng-Lai Tang;Bing-Yang Cao

{"title":"Heat Generation Mechanisms of Self-Heating Effects in SOI-MOS","authors":"Zheng-Lai Tang;Bing-Yang Cao","doi":"10.1109/JEDS.2024.3393019","DOIUrl":"10.1109/JEDS.2024.3393019","url":null,"abstract":"The development of microelectronic devices to the nanoscale intensifies self-heating challenges, affecting efficiency and durability. Understanding the mechanisms of heat generation at this scale is crucial, yet research extending beyond Joule heat remains limited. This paper simulates the self-heating effect of Silicon-On-Insulator Metal-Oxide-Semiconductor Field Effect Transistors (SOI-MOS) at the nanoscale and researches the characteristic and influence of different heat generation mechanisms, including the Joule heat, recombination heat and Peltier-Thomson heat. Our results provide a detailed two-dimensional distribution and intensity of various heat generation mechanisms within the silicon channel layer. It is found that Peltier-Thomson heat has the same magnitude as Joule heat at the nanoscale, and exhibits an alternating distribution pattern of hot and cold sources under the gate. But recombination heat is relatively negligible. The analysis of the influence of different heat mechanisms emphasizes the important role of Joule heat. While the offset effect limits the impact of Peltier-Thomson heat, its significance to device thermal performance should not be ignored. More importantly, this study investigates the impact of characteristic size on different heat generation mechanisms, revealing the size dependence of Peltier-Thomson heat.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10508189","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140804707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comparative Study on the Effects of Planarity of Access Region on the Low-Frequency Noise Performance of InAlN/GaN HFETs 接入区平面度对 InAlN/GaN 高频晶体管低频噪声性能影响的比较研究

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-22 DOI: 10.1109/JEDS.2024.3392174

Yatexu Patel;Pouya Valizadeh

引用次数: 0

Blue Laser Diode Annealed Top-Gate Low Temperature Poly-Si TFTs With Low Resistance of Source/Drain From Deposited n + Layer 经蓝色激光二极管退火的顶栅低温多晶硅 TFT，其源极/漏极的低电阻来自沉积的 n + 层

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-22 DOI: 10.1109/jeds.2024.3392183

Hongyuan Xu, Guangmiao Wan, Xu Wang, Xiaoliang Zhou, Jing Liu, Jinming Li, Lei Lu, Shengdong Zhang

引用次数: 0

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress 负偏压照明应力后非晶 InGaZnO 薄膜晶体管阈值电压的增加

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-16 DOI: 10.1109/JEDS.2024.3388727

Dongsheng Hong;Bing Zhang;Dongli Zhang;Mingxiang Wang;Rongxin Wang

引用次数: 0

An Experimentally Verified Temperature Dependent Drain Current Fluctuation Model for Low Temperature Applications 经实验验证的低温应用漏极电流随温度波动模型

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-15 DOI: 10.1109/JEDS.2024.3388840

Ying Sun;Yuchen Gu;Jing Wan;Xiao Yu;Bing Chen;Dawei Gao;Ran Cheng;Genquan Han

{"title":"An Experimentally Verified Temperature Dependent Drain Current Fluctuation Model for Low Temperature Applications","authors":"Ying Sun;Yuchen Gu;Jing Wan;Xiao Yu;Bing Chen;Dawei Gao;Ran Cheng;Genquan Han","doi":"10.1109/JEDS.2024.3388840","DOIUrl":"10.1109/JEDS.2024.3388840","url":null,"abstract":"In this work, an accurate temperature-dependent drain current \u0000<inline-formula> <tex-math>$I_{mathrm { D}}$ </tex-math></inline-formula>\u0000 fluctuation model valid from 10 to 300 K was proposed for 18 nm ultra-thin body and buried oxide (UTBB) n-channel field effect transistors (n-FETs). The temperature dependence of \u0000<inline-formula> <tex-math>$I_{mathrm { D}}$ </tex-math></inline-formula>\u0000 fluctuation was characterized and investigated from 300 K down to 10 K. In moderate inversion mode, \u0000<inline-formula> <tex-math>$I_{mathrm { D}}$ </tex-math></inline-formula>\u0000 fluctuation is more severe at sub-100 K while in the strong inversion mode, it still can be overshadowed by the charge screening effect. Cryogenic virtual source (CVS) device model was used to extract and analyze the carrier density and mobility which are used in the current fluctuation model. The current fluctuation model was experimentally verified under different inversion conditions, showing it can be used to analyze and optimize the flicker noise in the low temperature (LT) circuit applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10499957","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0