IEEE Journal of the Electron Devices Society最新文献

{"title":"Effective Reduction of Hydrogen Diffusion and Reliability Degradation in Peripheral Transistor of Peripheral-Under-Cell (PUC) NAND Flash Memory","authors":"Eunyoung Park;Hyun-Yong Yu","doi":"10.1109/JEDS.2024.3418212","DOIUrl":"10.1109/JEDS.2024.3418212","url":null,"abstract":"Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that excess hydrogen is injected into the peripheral transistor, resulting in degradation of reliability. Therefore, we propose the hydrogen diffusion model in PUC to investigate the degradation of peripheral transistor by excess hydrogen using Sentaurus 3D technology Computer-Aided Design (TCAD) and suggest an optimal process to improve reliability. As a result, by applying the bonding process and adjusting the cell alloy process sequence, the amount of excess hydrogen injection is reduced by 87% and the NBTI lifetime showed about 8.3 times greater result and TDDB breakdown time improved more than 9.1 times compared to the PUC structure made through a sequential process. Additionally, this process effectively alleviates excess hydrogen injection in the NAND cell with an increased number of WL. These results could provide critical insight for designing a PUC that ensures the reliability of peripheral transistor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568956","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation","authors":"Chanwoo Park;Seungjun Lee;Junghwan Park;Kyungjin Rim;Jihun Park;Seonggook Cho;Jongwook Jeon;Hyunbo Cho","doi":"10.1109/JEDS.2024.3417521","DOIUrl":"10.1109/JEDS.2024.3417521","url":null,"abstract":"We address the challenges associated with traditional analytical models, such as BSIM, in semiconductor device modeling. These models often face limitations in accurately representing the complex behaviors of miniaturized devices. As an alternative, Neural Compact Models (NCMs) offer improved modeling capabilities, but their effectiveness is constrained by a reliance on extensive datasets for accurate performance. In real-world scenarios, where measurements for device modeling are often limited, this dependence becomes a significant hindrance. In response, this work presents a large-scale pre-training approach for NCMs. By utilizing extensive datasets across various technology nodes, our method enables NCMs to develop a more detailed understanding of device behavior, thereby enhancing the accuracy and adaptability of MOSFET device simulations, particularly when data availability is limited. Our study illustrates the potential benefits of large-scale pre-training in enhancing the capabilities of NCMs, offering a practical solution to one of the key challenges in current device modeling practices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566861","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection","authors":"Musaib Rafiq;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/JEDS.2024.3416441","DOIUrl":"10.1109/JEDS.2024.3416441","url":null,"abstract":"The developments in the nascent field of artificial-intelligence-of-things (AIoT) relies heavily on the availability of high-quality multi-dimensional data. A huge amount of data is being collected in this era of big data, predominantly for AI/ML algorithms and emerging applications. Considering such voluminous quantities, the collected data may contain a substantial number of outliers which must be detected before utilizing them for data mining or computations. Therefore, outlier detection techniques such as Mahalanobis distance computation have gained significant popularity recently. Mahalanobis distance, the multivariate equivalent of the Euclidean distance, is used to detect the outliers in the correlated data accurately and finds widespread application in fault identification, data clustering, singleclass classification, information security, data mining, etc. However, traditional CMOS-based approaches to compute Mahalanobis distance are bulky and consume a huge amount of energy. Therefore, there is an urgent need for a compact and energy-efficient implementation of an outlier detection technique which may be deployed on AIoT primitives, including wireless sensor nodes for in-situ outlier detection and generation of high-quality data. To this end, in this paper, for the first time, we have proposed an efficient Ferroelectric FinFET-based implementation for detecting outliers in correlated multivariate data using Mahalanobis distance. The proposed implementation utilizes two crossbar arrays of ferroelectric FinFETs to calculate the Mahalanobis distance and detect outliers in the popular Wisconsin breast cancer dataset using a novel inverter-based threshold circuit. Our implementation exhibits an accuracy of 94.1% which is comparable to the software implementations while consuming a significantly low energy (27.2 pJ).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10563982","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HfO₂ Thin Films by Chemical Beam Vapor Deposition for Large Resistive Switching Memristors","authors":"Federico Vittorio Lupo;Mauro Mosca;Sarunas Bagdzevicius;Rashmi Rani;William Maudez;Estelle Wagner;Maria Pia Casaletto;Salvatore Basile;Giacomo Benvenuti;Isodiana Crupi;Roberto Macaluso","doi":"10.1109/JEDS.2024.3416516","DOIUrl":"10.1109/JEDS.2024.3416516","url":null,"abstract":"We present chemical beam vapor deposition (CBVD) as a valuable technique for the fabrication of good quality HfO2-based memristors. This deposition technique gives the opportunity to rapidly screen material properties in combinatorial mode and to reproduce the optimized conditions homogenously on large substrates. Cu/HfO2/Pt memory devices with three different oxide thicknesses were fabricated and electrically characterized. A bipolar resistive switching and forming free behavior was seen in all the tested devices. Lower switching voltages than similar devices fabricated by employing different deposition techniques were observed. The conduction mechanism in the low resistance state can be ascribed to filamentary copper, while a trap-controlled space charge limited current conduction was observed in the high resistance state. The comparative evaluation of devices with different oxide thicknesses allows to infer that devices with thicker HfO2 film (25 nm) are more performing in terms of ROFF/RON ratio (\u0000<inline-formula> <tex-math>$10{^{{6}}}$ </tex-math></inline-formula>\u0000), and reproducible resistive switching over more than 100 cycles in both low and high resistance states. Thinner oxide devices (20 nm and 16 nm), despite similar long retention time (\u0000<inline-formula> <tex-math>$10{^{{4}}}$ </tex-math></inline-formula>\u0000 s), and lower SET/RESET voltages show instead a smaller memory window and a switching instability. These results, compared also with other reported in literature for similar memristive structures realized with other deposition techniques, show that CBVD can be considered as a promising technique for realizing HfO2-based non-volatile memory devices with good performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10563993","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes","authors":"Murad G. K. Alabdullah;M. A. Elmessary;D. Nagy;N. Seoane;A. J. García-Loureiro;K. Kalna","doi":"10.1109/JEDS.2024.3416200","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3416200","url":null,"abstract":"The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current (\u0000<inline-formula> <tex-math>${I}_{mathrm {mathbf { DD}}}$ </tex-math></inline-formula>\u0000) because the gate scaling to 10 nm results in a decline of the current (by \u0000<inline-formula> <tex-math>$mathbf {10.7}$ </tex-math></inline-formula>\u0000%). \u0000<inline-formula> <tex-math>${I}_{mathrm {mathbf {DD}}}$ </tex-math></inline-formula>\u0000 of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches \u0000<inline-formula> <tex-math>$1times 10^{20} mathrm {cm^{-3}}$ </tex-math></inline-formula>\u0000, or increase by \u0000<inline-formula> <tex-math>$mathbf {3.8}$ </tex-math></inline-formula>\u0000% if the high-\u0000<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula>\u0000 dielectric layer equivalent oxide thickness (EOT) is less than \u0000<inline-formula> <tex-math>$mathbf {1.0}$ </tex-math></inline-formula>\u0000 nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. \u0000<inline-formula> <tex-math>${I}_{mathrm {mathbf {DD}}}$ </tex-math></inline-formula>\u0000 will increase by 3% and by 14% in the 10 nm gate NS FET with the \u0000<inline-formula> <tex-math>$langle 110rangle $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$langle 100rangle $ </tex-math></inline-formula>\u0000 channel orientations, respectively, when a strain of \u0000<inline-formula> <tex-math>$mathbf {0.5}$ </tex-math></inline-formula>\u0000% is applied to the channel, with a negligible increase for larger strain values (\u0000<inline-formula> <tex-math>$mathbf {0.7}$ </tex-math></inline-formula>\u0000% and \u0000<inline-formula> <tex-math>$mathbf {1.0}$ </tex-math></inline-formula>\u0000%).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10561475","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141631061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust Bidirectional Gate Driver on Array Based on Indium Gallium Zinc Oxide Thin-Film Transistor for In-Cell Touch Displays","authors":"Liufei Zhou;Fuchao He;Xiaojun Guo;Haihong Wang;Mingxin Wang;Yuning Zhang;Baoping Wang","doi":"10.1109/JEDS.2024.3404595","DOIUrl":"10.1109/JEDS.2024.3404595","url":null,"abstract":"In this paper, we propose a bidirectional gate driver on array (GOA) circuit design based on indium gallium zinc oxide (IGZO) thin-film transistor (TFT) to support time-division driving method (TDDM) for in-cell touch displays. The proposed circuit allows the touch panel to pause the display for touch sensing operations to achieve a touch reporting rate as twice as the frame rate of a display. A dual low-level maintaining unit design is used to suppress influence of the threshold voltage shift of TFTs through alternately turning on the devices. Owing to recovery of threshold voltage shift under negative bias, this design can maintain stable performance during long time operation. A narrow border 6.5” in-cell LCD panel of 90 Hz display with a 180 Hz touch reporting rate is finally demonstrated.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10559899","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Special Issue on Intelligent Sensor Systems for the IEEE Journal of Electron Devices","authors":"","doi":"10.1109/JEDS.2024.3405552","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3405552","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10558801","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141334027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers","authors":"","doi":"10.1109/JEDS.2024.3412339","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3412339","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10558802","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141333957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Call for Nominations Editor-in-Chief IEEE Transactions on Device and Materials Reliability","authors":"","doi":"10.1109/JEDS.2024.3369770","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3369770","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10558850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141334003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs","authors":"Yunjiao Bao;Gangping Yan;Lei Cao;Chuqiao Niu;Qingkun Li;Guanqiao Sang;Lianlian Li;Yanzhao Wei;Xuexiang Zhang;Jie Luo;Yanyu Yang;Gaobo Xu;Huaxiang Yin","doi":"10.1109/JEDS.2024.3414469","DOIUrl":"10.1109/JEDS.2024.3414469","url":null,"abstract":"In this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with the general back gate IGZO TFT structure, the Ioff of the proposed IGZO TFT reduces from \u0000<inline-formula> <tex-math>$2.57times 10{^{-}14 }$ </tex-math></inline-formula>\u0000 A/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m to \u0000<inline-formula> <tex-math>$7.57times 10{^{-}16 }$ </tex-math></inline-formula>\u0000 A/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m, achieving two orders of magnitude improvement. This breakthrough has the potential to increase the retention time of DRAM applications by nearly 100 times. Moreover, the pronounced novel structure has mitigated parasitic capacitance, thereby leading to a notable 47.7% reduction in write latency within dynamic-random-access-memory (DRAM) circuits. The relevant operation mechanism is carefully demonstrated and verified by the simulation of the electric field and potential barrier results by technical computer-aided design (TCAD). Furthermore, the impacts of the dual gate work function level, the length, and the type of isolation dielectric between dual work function gates are systematically investigated. The results show that the off-state leakage is further reduced by increasing the difference of the work function levels between in dual gates, the dielectric length (LD) and using the isolation layer with a lower dielectric constant. The PIDWF gate IGZO TFT exhibits scalability and is capable of achieving an 84.6% reduction in leakage current even with ultra-short channel lengths, which offers a promising application for future 3D DRAM applications with little extra cost.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10557586","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}