IEEE Journal of the Electron Devices Society最新文献

{"title":"Tungsten Trioxide Nanoparticles Modified Cuprous Oxide Film Non-Enzymatic Dopamine Sensor","authors":"Jung-Chuan Chou;Wei-Shun Chen;Po-Hui Yang;Po-Yu Kuo;Chih-Hsien Lai;Yu-Hsun Nien","doi":"10.1109/JEDS.2024.3387324","DOIUrl":"10.1109/JEDS.2024.3387324","url":null,"abstract":"Non-enzymatic dopamine (DA) sensors are important in diagnosing and treating human diseases. However, non-enzymatic sensors frequently encounter interference from other substances, posing a challenge of poor selectivity for such sensors. Herein, we prepared tungsten trioxide nanoparticles (WO3 NPs) via a simple hydrothermal method and immobilized them onto a cuprous oxide (Cu2O) film. The results demonstrate that WO3 NPs offer improved selectivity, thus avoiding interference from other substances. The DA sensor based on the Cu2O film modified with WO3 NPs exhibits excellent DA detection performance, with a wide linear range of \u0000<inline-formula> <tex-math>$1~mu text{M}$ </tex-math></inline-formula>\u0000 to 10 mM, a low limit of detection of \u0000<inline-formula> <tex-math>$0.21~mu text{M}$ </tex-math></inline-formula>\u0000, and good selectivity against common interfering substances. This non-enzymatic DA sensor features a simple structure, easy fabrication, small size, and suitability for mass production.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496458","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully Vertical GaN-on-SiC p-i-n Diodes With BFOM of 2.89 GW/cm2","authors":"Jialun Li;Renqiang Zhu;Ka Ming Wong;Kei May Lau","doi":"10.1109/JEDS.2024.3386857","DOIUrl":"10.1109/JEDS.2024.3386857","url":null,"abstract":"This letter reports a high-performance fully-vertical GaN-on-SiC p-i-n diode enabled by a conductive n-AlGaN buffer. The buffer conductivity was optimized by tuning the Al composition. The diode presents an ultra-low specific ON-resistance of 0.25 \u0000<inline-formula> <tex-math>$text{m}Omega cdot $ </tex-math></inline-formula>\u0000cm2, a high current swing of 1011, and a high breakdown voltage of 850 V with a 5-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000-thick drift layer, leading to a Baliga’s figure of merit (BFOM) of 2.89 GW/cm2. The diode performance at elevated temperatures and the OFF-state leakage mechanism are analyzed. The demonstrated fully-vertical GaN-on-SiC p-i-n diode with a conductive buffer reveals a simple way towards realizing high-performance fully-vertical GaN-on-SiC devices for high power applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496446","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Proposing an Accurate and Fast Optical Batch Inspection Method of Mini-/Micro-LEDs","authors":"Zhen Li;Mei-Cong Huang;Xiong-Jun Cao;Da Xu;Yi Lin;Zhong Chen;Zi-Quan Guo","doi":"10.1109/JEDS.2024.3386528","DOIUrl":"10.1109/JEDS.2024.3386528","url":null,"abstract":"Based on the microscopic hyperspectral imaging technique, an optical batch inspection method has been proposed by the authors to efficiently and precisely obtain the absolute emission spectra of red (R), green (G), and blue (B) Mini-/Micro-light-emitting diodes (Mini-/Micro-LEDs). The RGB Mini-LEDs (with a chip area of \u0000<inline-formula> <tex-math>$200,,mu text{m},,times 100,,mu text{m}$ </tex-math></inline-formula>\u0000) based array is selected for carrying out this experiment. Via the proposed method, the photometric and colorimetric properties of each Mini-LED pixel could be derived in detail. In this proposed method, an optimized Canny-based algorithm has been used for quickly detecting the effectively emitting area in the collected hyperspectral images, thus saving more time for workers. While compared with the traditional integrating-sphere-based method, the measured data between the proposed method and traditional method are in fairly good consistence, with their maximum deviation of < 3.2%. The external quantum efficiency (EQE) and chromaticity coordinates of each Mini-LED are acquired at the temperature ranging from 300 K to 340 K by the proposed method. Three RGB Micro-LEDs (with a chip area of \u0000<inline-formula> <tex-math>$10,,mu text{m},,times 10,,mu text{m}$ </tex-math></inline-formula>\u0000) based arrays are also selected for the optical batch detection, and the pseudocolor maps of normalized electroluminescence (EL) intensity for RGB Micro-LEDs are analyzed. Finally, the optical crosstalk of RGB Mini-LEDs is quantitatively defined and analyzed. The optical crosstalk effects are more prominent for red Mini-LEDs than the other two. Results indicate that the proposed method has shown potential applications in the field of Mini-/Micro-LEDs’ batch inspection.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10495305","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Buffer Charge Redistribution on RF Losses and Harmonic Distortion in GaN-on-Si Substrates","authors":"Pieter Cardinael;Sachin Yadav;Bertrand Parvais;Jean-Pierre Raskin","doi":"10.1109/JEDS.2024.3386170","DOIUrl":"10.1109/JEDS.2024.3386170","url":null,"abstract":"Understanding and mitigation of substrate RF losses and signal distortion are critical to enable high-performance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity \u0000<inline-formula> <tex-math>$({rho }_{eff})$ </tex-math></inline-formula>\u0000 in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the \u0000<inline-formula> <tex-math>${rho }_{eff}$ </tex-math></inline-formula>\u0000 degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in \u0000<inline-formula> <tex-math>${rho }_{eff}$ </tex-math></inline-formula>\u0000 at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of \u0000<inline-formula> <tex-math>$2^{mathrm{ nd}}$ </tex-math></inline-formula>\u0000 harmonic power of up to 5dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaN-on-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage (\u0000<inline-formula> <tex-math>$text{V}_{text {FB}}$ </tex-math></inline-formula>\u0000) of the Metal-Insulator-Semiconductor (MIS) structure. Free carrier transport across the buffer is shown to have the greatest contribution on the large time constants, highlighting the importance of vertical transport paths in GaN-on-Si stacks.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10495002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine Learning-Based Compact Model Design for Reconfigurable FETs","authors":"Maximilian Reuter;Johannes Wilm;Andreas Kramer;Niladri Bhattacharjee;Christoph Beyer;Jens Trommer;Thomas Mikolajick;Klaus Hofmann","doi":"10.1109/JEDS.2024.3386113","DOIUrl":"10.1109/JEDS.2024.3386113","url":null,"abstract":"In integrated circuit design compact models are the abstraction layer which connects semiconductor physics and circuit simulation. Established compact models like BSIM provide a powerful platform for many kinds of conventional MOSFETs. However, novel device concepts like reconfigurable FETs (RFETs) come with a higher expressiveness. Due to their altered transport physics as compared to classical inversion mode MOSFETs those devices are hard to describe in a closed form expression by classical compact models. Table models bridge this gap for devices with novel features or materials, but circuit simulation becomes slow and inaccurate due to interpolation and convergence difficulties. Table model data can, however, be translated to closed form expressions, providing equation based models without the need for interpolation during simulation time. This work shows data driven approaches to generate compact models from biasing tables without physical analysis of the device behavior. Two automated modeling techniques are applied to a recently emerged RFET, forming a Verilog-A compact model for DC and transient simulation in Cadence Virtuoso. Drive current is implemented as a neural network, large enough to accurately predict behavior of a multi-gate device. The high dynamic range from \u0000<inline-formula> <tex-math>$mA$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$pA$ </tex-math></inline-formula>\u0000 is covered by combining a linear model for high currents and a logarithmic model for low currents. For transient simulation precise models for electrode charges are essential. Here, symbolic regression provides human-readable closed form expressions which allow direct implementation in Verilog-A. The compact model approach is demonstrated with device data generated from a structural technology model (TCAD). However, the entire modeling flow can directly be used on real device measurements, if a technology model is unavailable or unpractical. We show that the presented machine learning based compact models show better convergence, more accurate predictions and faster simulation \u0000<inline-formula> <tex-math>$(82$ </tex-math></inline-formula>\u0000 to 308 times) in Cadence SPECTRE than simple table models generated from the same device.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10494540","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs","authors":"Anirban Kar;Shivendra Singh Parihar;Jun Z. Huang;Huilong Zhang;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan","doi":"10.1109/JEDS.2024.3384008","DOIUrl":"10.1109/JEDS.2024.3384008","url":null,"abstract":"Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10488034","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140582831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT Under Bias and Temperature Stress","authors":"Muhammad Aslam;Shu-Wei Chang;Yi-Ho Chen;Yao-Jen Lee;Yiming Li;Wen-Hsi Lee","doi":"10.1109/JEDS.2024.3406676","DOIUrl":"10.1109/JEDS.2024.3406676","url":null,"abstract":"ABSTRACT Amorphous indium gallium zinc oxide (a-IGZO)-based thin film transistors (TFTs) are increasingly becoming popular because of their potential in futuristic applications, including CMOS technology. Given the demand for CMOS-compatible, ultra-scaled, reliable, and high-performing devices, we fabricate and analyze scaled-channel a-IGZO-TFTs with an optimal double-gate structure, a thin nanosheet-based channel, and an effective high- \u0000<inline-formula> <tex-math>$kappa$ </tex-math></inline-formula>\u0000 dielectric namely HfO2. The reliably reported double gate IGZO nanosheet TFTs (DG-IGZO-NS-TFTs) are tested under positive and negative bias stress at variant temperatures, and the resulting modulations are analyzed critically. The reported DG-IGZO-NSTFTs exhibit a negative side threshold voltage shift (\u0000<inline-formula> <tex-math>$Delta$ </tex-math></inline-formula>\u0000Vth) accompanied by an increase in Ion/Ion(0) under negative bias temperature stress (NBTS) at elevated temperatures, which indicates the presence of additional charges. An anomalous negative side shifting of the Vth is observed under positive bias temperature stress (PBTS), where diffused hydrogen atoms are identified as introducing excess n-type carriers into the channel and causing the observed \u0000<inline-formula> <tex-math>$Delta$ </tex-math></inline-formula>\u0000Vth. The spectroscopic analysis is performed to establish evidence for the assumed mechanisms, and the role of individual gates is investigated in the context of performance variance under temperature-bias stress. Moreover, the partial reversibility of the stress-induced degradation is experimentally established and methodically discussed. Overall, the reported results offer a comprehensive understanding of scaled-channel DG-NS-IGZO-TFTs, which help shape performance-enhancement strategies, control degradation mechanisms, and define appropriate application scenarios.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10540482","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141188932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Quantum Dot Light-Emitting Diodes With DAA Doped Electron Transport Layer","authors":"Haomin Chen;Qunying Zeng;Yangbin Zhu;Tuo Wu;Yijie Fan;Tailiang Guo;Hailong Hu;Fushan Li","doi":"10.1109/JEDS.2024.3382874","DOIUrl":"10.1109/JEDS.2024.3382874","url":null,"abstract":"Zinc oxidenanoparticles (ZnO NPs) is widely used as electron transport layer material in quantum dot light-emitting diodes (QLED) due to its high carrier mobility, unique photoelectric properties and good stability. However, because ZnO has higher electron mobility than organic hole transport materials, the carrier transport is unbalanced. In addition, ZnO NPs has many surface defects, which is easy to capture electrons or holes, increasing the probability of non-radiative recombination. To solve these problems, we carefully selected an organic compound diallylamine (DAA) doping method to modify the surface of ZnO. DAA is found to not only reduce the quenching at the interface between ZnO and QD, but also regulate the energy level position to promote the carrier injection balance of QLED devices. Compared with control ZnO QLED, the external quantum efficiency (EQE) of the red QLED with DAA-modified ZnO NPs is significantly improved, the peakEQE of the devices increased by 21% from 18.8% to 23.6%. respectively. It is a simple and economical solution for manufacturing high-performance QLED.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10485228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140324058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvement of AlGaN/GaN HEMT Noise Figure Using Thick Cu Metallization for Satellite Communication Applications","authors":"Howie Tseng;Yueh-Chin Lin;Chieh Cheng;Po-Wei Chen;Heng-Tung Hsu;Yi-Fan Tsao;Edward Yi Chang","doi":"10.1109/JEDS.2024.3381030","DOIUrl":"10.1109/JEDS.2024.3381030","url":null,"abstract":"In this study, AlGaN/GaN high-electron-mobility-transistor (HEMT) with thick Cu metallization is investigated, and the Radio Frequency (RF) performance and the reliability are analyzed. By applying thick Cu metallization of \u0000<inline-formula> <tex-math>$6.0 ~mu text{m}$ </tex-math></inline-formula>\u0000 as interconnect, the cut-off frequency (fT), the maximum oscillation frequency (fmax), and the power performance can be improved. Besides, the thick-Cu-metallized device exhibits reduced minimum noise figure (NFmin) of 0.7, 1.0, 2.2 and 2.8 dB at 12, 14, 28 and 38 GHz, respectively, which can be attributed to the reduction of the source and drain resistance caused by thick Cu metallization. Furthermore, for stress test under high drain-to-source voltage (VDS) and high temperature, the proposed device exhibits good stability. The results show that the thick Cu metallization technology has great potential to be applied in satellite communication system.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10478115","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140197315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bulk Carrier Contaminations and Their Effects on MOSFETs Under Energy Harvesting Systems","authors":"Yuta Watanabe;Takaya Sugiura;Nobuhiko Nakano","doi":"10.1109/JEDS.2024.3403649","DOIUrl":"10.1109/JEDS.2024.3403649","url":null,"abstract":"Energy harvesters, such as photovoltaic cells, generate carriers in the deep substrate regions; these carriers can affect MOSFETs and deteriorate their performance or even cause malfunctioning. In this study, we discussed the effects of bulk carrier contamination on integrated MOSFETs in the context of energy-harvesting devices. We confirmed that the close integration of MOSFET circuits in a photovoltaic cell causes malfunctioning under strong light illumination. Moreover, numerical simulations revealed that PMOS is highly sensitive to carrier contamination as a forward pn-junction from the bulk-side storage carriers into the NWell region. Furthermore, increasing the distance from the illumination window was not an effective countermeasure, and alternative methods, such as the silicon-on-insulator substrate, n−-substrate, or NMOS logic, should be implemented for such large-scale integration.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10536006","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141150325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}