IEEE Journal of the Electron Devices Society最新文献_第7页

Dynamic Response of Low-Voltage Thin Film Phototransistors Based on DNTT Organic Semiconductor 基于DNTT有机半导体的低压薄膜光电晶体管的动态响应

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-21 DOI: 10.1109/JEDS.2025.3553583

Antonio Vettoliere;Fabio Chiarella;Vincenzo Izzo;Marcello Campajola;Paolo Scotto Di Vettimo;Patrizia Minutolo;Alberto Aloisio;Ettore Sarnelli

{"title":"Dynamic Response of Low-Voltage Thin Film Phototransistors Based on DNTT Organic Semiconductor","authors":"Antonio Vettoliere;Fabio Chiarella;Vincenzo Izzo;Marcello Campajola;Paolo Scotto Di Vettimo;Patrizia Minutolo;Alberto Aloisio;Ettore Sarnelli","doi":"10.1109/JEDS.2025.3553583","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3553583","url":null,"abstract":"We analyzed the dynamic response to the light of organic field-effect transistors in bottom-gate/top-contact configuration. We fabricated Al/Al2O3/SAM/DNTT/Au phototransistors by evaporating thin film layers through shadow masks on flexible PEN (polyethylene naphthalate) substrates. The structure is composed of Al layer as the gate electrode, and Au used both for Source and Drain electrodes. DNTT (Dinaphtho[2,3-b:<inline-formula> <tex-math>$2^{prime }$ </tex-math></inline-formula>,<inline-formula> <tex-math>$3^{prime }$ </tex-math></inline-formula>-f]thieno[3,2-b]thiophene) is the active organic semiconductor layer and Al2O3 is the dielectric material, chosen for the high value of the dielectric constant. SAM (self-assembled monolayer) was used to improve adhesion and interface properties between Al2O3 and DNTT. The transistors, sensitive to blue light, were biased at low-voltage (Vgs and <inline-formula> <tex-math>$mathrm { V_{ds}}$ </tex-math></inline-formula> from 0 to 3.5 V). Devices showed low <inline-formula> <tex-math>$mathrm { I_{gs}}$ </tex-math></inline-formula> leakage currents, of the order of <inline-formula> <tex-math>$5x10^{-10}$ </tex-math></inline-formula> A, and a clear electro-optical response to the light. The maximum responsivity value was about 0.21 A/W in the static regime, while the lowest irradiance producing a measurable response in dynamic regime was <inline-formula> <tex-math>$13~mu $ </tex-math></inline-formula>W/cm2. Fast time components of the rise time of the light response for the analyzed phototransistors, of the order of few hundreds of ms, turned out to be among the fastest reported in literature for Al/AlOx/DNTT/Au organic phototransistor. These preliminary results are encouraging for developing organic phototransistors for visible light communication.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"317-325"},"PeriodicalIF":2.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10937183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power LTPO Scan Driver Circuit Using DC Power Supplied Buffer 一种使用直流电源缓冲器的低功耗LTPO扫描驱动电路

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-19 DOI: 10.1109/JEDS.2025.3571171

SangWoon Lee;JungSuk Oh;HyeongMin Kim;YiKyoung You;Nack-Hyeon Keum;HeeJu Moon;SangHun Kim;KeeChan Park;Hwarim Im

{"title":"A Low-Power LTPO Scan Driver Circuit Using DC Power Supplied Buffer","authors":"SangWoon Lee;JungSuk Oh;HyeongMin Kim;YiKyoung You;Nack-Hyeon Keum;HeeJu Moon;SangHun Kim;KeeChan Park;Hwarim Im","doi":"10.1109/JEDS.2025.3571171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3571171","url":null,"abstract":"This paper proposes a novel low-temperature polycrystalline silicon and oxide (LTPO) scan driver circuit integrating p-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and n-channel metal-oxide (MOx) TFTs. The proposed circuit employs a complementary metal-oxide-semiconductor inverter as an output buffer, allowing low-level voltage to be delivered from a DC power supply to the output node without relying on clock-supplied bootstrapping, which is typically required in most scan driver circuits to drive the output buffer. This design significantly lowers dynamic power consumption by up to 74% by reducing the power consumption due to charging/discharging the parasitic capacitance of the buffer TFT by the clock signals compared with the conventional LTPO scan driver circuits utilizing the clock-supplied bootstrapping method. Additionally, the proposed circuit reduces the positive bias applied to MOx TFTs to alleviate stress conditions effectively. Therefore, the proposed circuit can improve long-term reliability by mitigating the threshold voltage shifts of MOx TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"494-500"},"PeriodicalIF":2.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11006837","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Field-Effect Passivation of GaN-Based Blue Micro-Light-Emitting Diodes gan基蓝色微发光二极管的场效应钝化

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-18 DOI: 10.1109/JEDS.2025.3552171

Woo Jin Baek;Joon Pyo Kim;Song Hyeon Kuk;Juhyuk Park;Hyun Soo Kim;Dae-Myeong Geum;Sang Hyeon Kim

引用次数: 0

Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability 双层InGaSnO和氮掺杂InSnO薄膜晶体管的设计与优化，以提高迁移率和可靠性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-18 DOI: 10.1109/JEDS.2025.3552454

Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan

{"title":"Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability","authors":"Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2025.3552454","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552454","url":null,"abstract":"In this study, high-performance indium gallium tin oxide (IGTO) and nitrogen (N) doped indium tin oxide (ITO) hetero structured bilayer thin-film transistors (TFTs) are prepared by incorporating an N-doped ITO intercalation layer in single-layer IGTO TFTs. The performance of the IGTO/ITO:N bilayer TFTs is significantly improved compared with single-layer IGTO TFTs, with specific indicators including a field-effect mobility of 32.6 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, a subthreshold swing of 201 mV/dec, a threshold voltage shifts of 0.21 V and −0.45 V under ±10 V gate-bias stress. The results show that the performance enhancement is due to the rational design of the bilayer structure, in which the ITO layer functions as a charge-accumulation layer, providing additional electrons. Meanwhile, N doping effectively reduces the oxygen vacancies, thereby decreasing the interfacial trap density, and ultimately enhancing the performance of single-layer IGTO TFTs. Through X-ray photoelectron spectroscopy and low-frequency noise analyses, we further confirmed the positive effects of N doping and bilayer structure on reducing the defective states and enhancing the stability of TFTs. Overall, the strategy presented here is effective for preparing high performance oxide TFTs for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"290-296"},"PeriodicalIF":2.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of the Schottky Barrier Height on the Carrier Velocity Overshoot Behaviors in SOI nMOSFETs With Metal Source/Drain 肖特基势垒高度对金属源漏型SOI nmosfet载流子速度超调行为的影响

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-15 DOI: 10.1109/JEDS.2025.3569242

Rui Su;Yan Jing;Xinyi Zhang;Yi Jiang;Dawei Gao;Walter Schwarzenbach;Bich-Yen Nguyen;Junkang Li;John Robertson;Rui Zhang

引用次数: 0

High Power Added Efficiency Enhancement-Mode Γ-Gate RF HEMT With High/Low p-GaN Doping Profile 高功率附加效率增强模式Γ-Gate高/低p-GaN掺杂的RF HEMT

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-14 DOI: 10.1109/JEDS.2025.3551313

Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin

{"title":"High Power Added Efficiency Enhancement-Mode Γ-Gate RF HEMT With High/Low p-GaN Doping Profile","authors":"Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin","doi":"10.1109/JEDS.2025.3551313","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3551313","url":null,"abstract":"<inline-formula> <tex-math>$0.5~mu $ </tex-math></inline-formula>m enhancement-mode (E-mode) p-GaN <inline-formula> <tex-math>$Gamma $ </tex-math></inline-formula>-gate RF HEMT with engineered Mg doping profile in p-GaN layer was studied for high power amplifier application. With high/low Mg doping profile design in p-GaN, the traditional Ti/p-GaN Schottky gate behavior can be transformed to ohmic-gate after 550°C 3 minutes post-gate annealing. The ohmic-gate design of p-GaN HEMT can minimize poole-frenkel (PF) emission thus the flicker noise and current collapse (C.C) can be improved. A better gate-to-channel modulation ability is also obtained due to precipitous C-VG curve of low Mg (<inline-formula> <tex-math>$1times 10{^{{19}}}$ </tex-math></inline-formula>cm-3) doping concentration p-GaN layer. The fabricated device achieves a threshold voltage (VTH) of +1.1 V, and shows a low on-resistance (RON) of <inline-formula> <tex-math>$1.8~Omega cdot $ </tex-math></inline-formula>mm and an off-state breakdown voltage of 206 V. With the engineered Mg doping profile design, a 70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"285-289"},"PeriodicalIF":2.0,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10926554","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimize Gate-All-Around Devices Using Wide Neural Network-Enhanced Bayesian Optimization 基于广义神经网络增强贝叶斯优化的全门器件优化

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-13 DOI: 10.1109/JEDS.2025.3569528

Jiaye Shen;Zhiqiang Li;Zhenjie Yao

{"title":"Optimize Gate-All-Around Devices Using Wide Neural Network-Enhanced Bayesian Optimization","authors":"Jiaye Shen;Zhiqiang Li;Zhenjie Yao","doi":"10.1109/JEDS.2025.3569528","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3569528","url":null,"abstract":"Device design processes based on manual design experience require numerous experiments and simulations. As transistors continue to shrink, complex physical effects, such as quantum effects intensify, making the design process increasingly costly, whether based on experiments or technology computer-assisted design (TCAD) simulations. To reduce the experimental and simulation resources consumed during the design process, we propose a device optimization framework based on neural network-enhanced Bayesian Optimization (BO). We target two Figures of Merit (FoMs) of Nanowire field-effect transistor (NWFET) devices as optimization objectives: subthreshold swing (SS) and on-state current (Ion). By improving the neural network to better fit the nonlinear mapping between the objective functions and input parameters, we effectively optimize device parameters while reducing the number of TCAD simulations. Experimental results show that compared to Bayesian optimization frameworks based on Gaussian Process (GP), Random Forest (RF) and Deep Networks for Global Optimization (DNGO), our neural network-based Bayesian optimization framework reduced the number of iterations by 19.3%, 42.7% and 60.3%, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"456-463"},"PeriodicalIF":2.0,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11003089","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology 14nm FinFET技术锁相环电路老化分析及退化预测

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-11 DOI: 10.1109/JEDS.2025.3549754

Meng Li;Xin Xu;Xianghui Li;Yunpeng Li;Yiqun Shi;Qingqing Sun;Hao Zhu

{"title":"Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology","authors":"Meng Li;Xin Xu;Xianghui Li;Yunpeng Li;Yiqun Shi;Qingqing Sun;Hao Zhu","doi":"10.1109/JEDS.2025.3549754","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549754","url":null,"abstract":"This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"270-277"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918946","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hot Carrier Degradation in Si n-MOSFETs at Cryogenic Temperatures 低温下Si - n- mosfet的热载流子降解

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-11 DOI: 10.1109/JEDS.2025.3550268

Shunsuke Shitakata;Hiroshi Oka;Kimihiko Kato;Takumi Inaba;Shota Iizuka;Hidehiro Asai;Takahiro Mori

引用次数: 0

Enhancement of Near-Infrared Sensitivity in Silicon-Based Image Sensors to Oblique Chief Rays via Quasi-Surface Plasmon Resonance 准表面等离子体共振增强硅基图像传感器对斜主射线的近红外灵敏度

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-10 DOI: 10.1109/JEDS.2025.3549721

Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono

{"title":"Enhancement of Near-Infrared Sensitivity in Silicon-Based Image Sensors to Oblique Chief Rays via Quasi-Surface Plasmon Resonance","authors":"Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono","doi":"10.1109/JEDS.2025.3549721","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549721","url":null,"abstract":"A silicon-based image sensor is proposed, incorporating plasmonic diffraction gratings tailored to chief ray angles (CRAs), to enhance near-infrared (NIR) sensitivity improvement over a broad range of incident angles. Under quasi-surface plasmon resonance (quasi-SPR) conditions, the metal grating efficiently diffracted incident light into the silicon absorption layer. The period and width of the metal grating were adjusted at each pixel position according to CRAs, thereby improving the NIR sensitivity at sensor edges. The plasmonically diffracted light with angled chief ray was confined within the pixel photodiode. The photon confinement resulted in a significant improvement in absorption of approximately 37% or more, within an incident angle range of 30 degrees at a NIR wavelength of 940 nm and a silicon thickness of 3 μm. The improvement in NIR absorption over a broad incident angle range enhances the sensitivity of the entire sensor chip, representing a significant advancement for NIR cameras.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"278-284"},"PeriodicalIF":2.0,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918731","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0