IEEE Journal of the Electron Devices Society最新文献

{"title":"Importance of Structure Optimization to Achieve Large Orbital Energy Spacing in Si fin-Type Quantum Dot Devices","authors":"Jotaro J. Nakane;Hidehiro Asai;Minori Hashizume;Takahiro Horiba;Katsuhiro Kutsuki;Shota Iizuka;Yusuke Chiashi;Hiroshi Oka;Kimihiko Kato;Seiji Kajita;Takahiro Mori","doi":"10.1109/JEDS.2026.3719324","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3719324","url":null,"abstract":"Silicon spin qubits are a promising platform for large-scale quantum information processing, but operation at elevated temperature requires quantum dots with both large orbital energy spacing and large charging energy. In this work, we theoretically study silicon metal-oxide-semiconductor fin-type quantum dots and clarify how fin width and gate length determine these energy scales. Using a self-consistent quantum and semiclassical device-simulation framework, we calculate the orbital spectrum and total capacitance over a range of device dimensions. We find that the orbital energy spacing does not increase monotonically as the structure is narrowed. Instead, it exhibits a maximum at an intermediate fin width. This nonmonotonic behavior originates from a change in the character of the first excited orbital, from excitation along the gate-length direction in narrow fins to excitation across the fin width in wider fins. In contrast, the charging energy increases monotonically as fin width and gate length are reduced. The results show that aggressive isotropic scaling is not the optimal strategy for elevated-temperature qubit design. Rather, co-optimization of fin width and gate length near the orbital crossover region maximizes orbital energy spacing while preserving sufficiently large charging energy.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"733-739"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11640930","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148749295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Analysis of Oxidant Effects During ALD Process of Hf0.5Zr0.5O2 Ferroelectric Thin Films","authors":"Xiaopeng Li;Yilin Hou;Xiaoyu Dou;Yaoyu He;Yuwei Qu;Pengpeng Sang;Xuepeng Zhan;Xiaolei Wang;Jixuan Wu;Jiezhi Chen","doi":"10.1109/JEDS.2025.3570717","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3570717","url":null,"abstract":"To guide the process optimization of HfO2-based ferroelectric (FE) devices, the effects of oxidants (O3/H2O) during atomic layer deposition (ALD) process of Hf0.5Zr0.5O2 films are systematically investigated. The results indicate that using the stronger oxidant (O3) leads to higher remanent polarization (Pr) but poorer endurance, with significant leakage deterioration after wakeup and a pronounced imprint effect during cycling. In contrast, the weaker oxidant (H2O) results in lower Pr but improves polarization switching speed. The influence of oxidants on pre-existing defects and interfacial reactions may be potential key factors. Our findings provide valuable insights for process optimization tailored to specific application requirements.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"654-659"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11006054","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148748133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gate-All-Around Vertically Stacked Polycrystalline Silicon Nanosheet Channels Transistor Fabricated Using Low-Pressure and Low-Thermal-Budget Solid-Phase Crystallization Without Channel Trimming Processes","authors":"Po-Yi Kuo;Chou-Wei Wang","doi":"10.1109/JEDS.2026.3736437","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3736437","url":null,"abstract":"The gate-all-around (GAA) transistors with four vertically stacked (VS) polycrystalline silicon (poly-Si) nanosheet (NS) channels (GAA 4VS-NSTs) have been successfully fabricated and demonstrated without channel trimming processes. A novel low-pressure and low-thermal-budget solid-phase crystallization (LPLT-SPC) process was employed to crystallize the ultra-thin poly-Si NS channels, effectively preventing localized oxidation and improving the subthreshold swing (S.S.) characteristics. Structural optimization, including increased contact area between the poly-Si NS channels and the raised source/drain (S/D) regions, as well as a thicker raised S/D, further contributes to performance enhancement. Compared to conventional atmospheric pressure solid-phase crystallization (AP-SPC) devices, GAA 4VS-NSTs exhibit an excellent S.S. of approximately 72 mV/dec. at a channel length (L<inline-formula> <tex-math>${}_{mathrm {CH}}$ </tex-math></inline-formula>) of 250nm. Additionally, the 4VS channels provide significant enhancement in drain drive currents (I<inline-formula> <tex-math>${}_{mathrm {DS}}$ </tex-math></inline-formula>) normalized to the active footprint width (W<inline-formula> <tex-math>${}_{mathrm {FP}}$ </tex-math></inline-formula>), i.e., IDS/WFP.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"881-886"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703603","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149188500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Erratum to “Landau–Khalatnikov-Based Modeling and Design Methodology for 1T-1FeFET Ferroelectric Neuron Oscillators”","authors":"Xiangkai Zeng;Zhao-Yi Yan;Houfang Liu;Haitao Liu;Ruiting Zhao;Dapeng Huang;Lin-Wang Wang;Yi Yang;Tian-Ling Ren","doi":"10.1109/JEDS.2026.3735219","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3735219","url":null,"abstract":"In the above article [1], several production/typesetting errors were introduced during the publication process. These errors do not affect the technical content, results, or conclusions of the article. The corrections are as follows. 1)On page 508, in Section I, an extraneous opening parenthesis was introduced before Ref. [15]. The affected text should read: “The Preisach model, for instance, effectively reproduces hysteresis loops but offers little insight into the microscopic mechanism of polarization switching or temporal polarization dynamics [15].”2)On page 510, in Section II-D, the gate-to-drain capacitance symbol was incorrectly typeset as $C_{gs}$ . The affected sentence: “...while the gate-to-drain capacitance $C_{gs}$ is neglected in phase-diagram analysis due to its relatively small contribution compared to $C_{gs}$ .” should be corrected to: “...while the gate-to-drain capacitance $C_{gd}$ is neglected in phase-diagram analysis due to its relatively small contribution compared to $C_{gs}$ .”3)On page 511, in Section IV, an extraneous character was introduced immediately before the integral sign in the energy-per-spike expression. The expression should read:begin{equation*} E_{mathrm {spike}}approx int V_{DD} I_{D}left ({ t }right) dt.end{equation*} 4)On page 512, an unintended duplicate table was introduced. The table labeled Table 4, “Model Evaluation for Multi-Domain Case,” contains duplicated contentidentical to Table 5 and should be removed together with its caption. The current Table 5 should be numbered Table 4, and its caption should read: “Benchmark of 1T-1FeFET Neuron Model in This Work With Other Reported Solutions.”5)On page 513, in Section V, the braces enclosing the two arguments of the min operator were omitted. The expression should read:begin{equation*} min{left |{ V_{DD}-V_{GF} }right |, vert V_{GF}-C_{MOS}^{-1}C_{gd}V_{DD}vert }end{equation*} 6)On page 513, in Section V, an extraneous character was introduced immediately before the coefficient 2 in the approximation. The expression should read:begin{equation*} V_{DD}approx 2V_{GF}.end{equation*} 7)On page 513, in Section VI, an additional dash was introduced in the notation for the current-voltage characteristic. The notation should read “ $I!-!V$ characteristic.”8)On page 515, in Appendix B, “Dimensional Consistency,” the exponents in the unit of the Landau coefficient $beta $ were not rendered as superscripts. The unit should read $m^{5} mathord {left /{ vphantom {m^{5} left ({ Fcdot C^{2} }right)}}right.hspace {-1.2pt} } left ({ Fcdot C^{2} }right)$ .","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"874-874"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11737377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149188575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental Verification and Analytical Modeling of the Zero Temperature Coefficient in Half-Diamond and Diamond MOSFETs Under High-Temperature","authors":"Marco A. P. Peixoto;Luciano M. Camillo;Salvador P. Gimenez","doi":"10.1109/JEDS.2026.3686086","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3686086","url":null,"abstract":"This work presents an analytical and experimental investigation of the Zero Temperature Coefficient (ZTC) behavior for the drain current (IDS) in Half-Diamond (HDM) and Diamond (DM) Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (MOSFETs) across Triode and Saturation regions under high-temperature (<inline-formula> <tex-math>$T$ </tex-math></inline-formula>) conditions. The accuracy of the Camillo-Martino model (CM-Model) in predicting the gate voltage (VGS) at this bias point (VZTC) was evaluated using 180 nm Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology. Results confirm that HDM and DM preserve the Longitudinal Corner Effect (LCE) and the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) under high-T, yielding higher IDS/(W/L) than equivalent rectangular (RM) MOSFETs. The HDM exhibited IDS/(W/L) gains at ZTC of 50.3% and 71.6% (Triode and Saturation) over RM, while DM showed gains of 44.3% and 52.9%, respectively. Similar <inline-formula> <tex-math>${mathrm { V}}_{mathrm { ZTC}}$ </tex-math></inline-formula> values across all devices (3.2% maximum difference) confirm that innovative gate geometries do not alter ZTC biasing. Overall, HDM provides superior thermal stability, higher <inline-formula> <tex-math>${mathrm { I}}_{mathrm { DS}}$ </tex-math></inline-formula> capability, and reduced die area for low-power, high-<inline-formula> <tex-math>$T$ </tex-math></inline-formula> CMOS ICs. The CM-Model strongly agreed with experimental data, validating its use for innovative gate layouts with maximum errors of 0.79% (Saturation region) and 5.72% (Triode region) above 325 K.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"250-257"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11488733","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Short-Distance Thermally Driven Double-Helix Transverse Thermoelectric Generator Based on LTCC Technology","authors":"Hong-Zhi Jia;Hai-Chun Hao;Xue-Qing Tian;Bo Dai;Da-Wei Zhang;Ning Wang","doi":"10.1109/JEDS.2026.3689682","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3689682","url":null,"abstract":"Based on LTCC technology, a single through-hole double-helix transverse thermoelectric generator (TEG) structure with short-distance vertical thermal drive is proposed. A staggered distribution of cold and heat sources in the longitudinal direction is established in this structure. Hence, the external temperature difference can be effectively concentrated on both sides of the transverse Y-type thermoelectric unit, reducing the thermal resistance loss. In order to solve the problem of electrode encirclement in the single-helix transverse thermoelectric array structure, a cascaded structure of double-helix thermoelectric units is designed to construct a high-density parallel power generation unit to improve the energy harvesting capacity. The experimental results show that the output voltage of the proposed 170 pairs of thermocouple double-helix transverse TEG can reach up to 231.8mV, while the maximum output voltage factor is 0.12 mV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm<inline-formula> <tex-math>${}^{-2}cdot $ </tex-math></inline-formula>K−2 with the maximum output power factor of <inline-formula> <tex-math>$0.004~mu $ </tex-math></inline-formula>W<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm<inline-formula> <tex-math>${}^{-2}cdot $ </tex-math></inline-formula>K−2. Compared with the single-helix lateral TEG, the power generation capacity of the double-helix inductance TEG is increased by 82.52%. This work can provide additional solutions for energy harvesting of micro energy.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"287-292"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11503256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced Polarization Switching in HfZrO2 MFS FeFET Using WOx Interlayer","authors":"Eunjin Kim;Hyoungjin Park;Jiae Jeong;Jiyong Woo","doi":"10.1109/JEDS.2026.3695087","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3695087","url":null,"abstract":"We demonstrate that the memory window (MW) of HfZrO2 (HZO)-based ferroelectric field-effect transistors (FeFETs) with an InZnO channel/HZO/W gate stack can be noticeably widened to over 2 V by introducing an amorphous WO2.7 interlayer (IL) into the gate interface. Although an orthorhombic (o-) phase is clearly observed in HZO using microscopic images and diffraction patterns, a narrow MW of 0.5 V is obtained from the FeFET. Unlike those obtained from the HZO FeFET, a large 2 remnant polarization of <inline-formula> <tex-math>$19~mu $ </tex-math></inline-formula>C/cm2 and intense diffraction peaks corresponding to the o-phase are obtained from the HZO/WO2.7 FeFET. Surface topology and elemental analyses reveal that most of the phases of HZO can be uniformly transformed into the o-phase by the amorphous WO2.7 IL with a low thermal expansion coefficient of <inline-formula> <tex-math>$sim 1times 10^{-6}$ </tex-math></inline-formula> K−1. In addition, the WO2.7 IL prevents unwanted defect generation at the HZO/W gate interface. Therefore, the number of dipoles in the HZO/WO2.7 IL FeFET participating in switching increases without charge trapping, thereby improving cycling endurance and low-temperature (<inline-formula> <tex-math>$- 150~^{mathrm {o}}$ </tex-math></inline-formula>C) operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"318-323"},"PeriodicalIF":2.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11527210","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deep Learning Framework for Quantum-Aware Modeling and Inverse Parameter Extraction in CNTFETs","authors":"Yunlin Zou;Zhun Wei;Shuo Zhang;Enze Zhu;Changhao Qu;Wen-Yan Yin","doi":"10.1109/JEDS.2026.3705027","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3705027","url":null,"abstract":"This paper presents a machine learning (ML) framework for the modeling and inverse parameter extraction of carbon nanotube field-effect transistors (CNTFETs) with channel lengths below 100 nm. A high-fidelity dataset is generated using the non-equilibrium Green’s function (NEGF) formalism combined with acoustic phonon (AP) scattering to capture critical quantum transport effects. For forward modeling, a deep operator network (DeepONet) is employed to predict current-voltage (I-V) characteristics from structural and bias parameters, achieving significant improvements in inference efficiency while maintaining high accuracy. Furthermore, the DeepONet enables efficient multi-objective optimization, rapidly identifying optimal solutions that balance conflicting performance metrics. For inverse parameter extraction, a two-stage model is developed based on principal component analysis (PCA) and a multilayer perceptron (MLP), enabling the recovery of key device parameters from high-dimensional I-V data. A tandem model with a hybrid loss function combining inverse and forward consistency is leveraged to alleviate the non-uniqueness problem. The proposed framework enables rapid, quantum-aware device simulation and direct inverse design, providing a scalable solution for CNTFET development, design optimization, and process monitoring.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"430-441"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11570186","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frequency-Dependent Physical Mechanisms and Modeling of Dynamic ON-Resistance in SiC MOSFETs","authors":"Zhigang Wang;Yihui Song","doi":"10.1109/JEDS.2026.3710181","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3710181","url":null,"abstract":"To clarify the physical mechanisms of dynamic ON-resistance (<inline-formula> <tex-math>$R_{mathrm {on}}$ </tex-math></inline-formula>) in silicon carbide (SiC) MOSFETs, this work investigates how threshold-voltage shift (<inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula>) evolution and interface-trap kinetics vary with switching frequency. Based on this, physical models of static JFET resistance (<inline-formula> <tex-math>$R_{mathrm {JFET}}$ </tex-math></inline-formula>), <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> and dynamic <inline-formula> <tex-math>$R_{mathrm {on}}$ </tex-math></inline-formula> are developed to translate the frequency-dependent trap dynamics into predictable device-level electrical parameter variations. The switching behavior acting as an integrated figure of merit that links static conduction and dynamic behavior, is further analyzed using a five-terminal method. Two SiC MOSFET structures with engineered JFET regions: Single-Segment Modulated JFET MOSFET (SMJ-MOS) and Dual-Segment Modulated JFET MOSFET (DMJ-MOS) are employed, with DMJ-MOS exhibiting 15% lower static <inline-formula> <tex-math>$R_{mathrm {on}}$ </tex-math></inline-formula>, together with 91% reduced <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula>, 12% reduced dynamic <inline-formula> <tex-math>$R_{mathrm {on}}$ </tex-math></inline-formula>, and 31% reduced switching loss compared with the conventional SiC MOSFET.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"442-449"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11595544","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact Modeling for Sub-Threshold Synaptic Cells With a Contact Ideality Factor Based on a Pass-Transistor Concept","authors":"Younggeon Ko;Sungjae Park;Danyoung Cha;Sungsik Lee","doi":"10.1109/JEDS.2026.3713862","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3713862","url":null,"abstract":"We present a study on a compact model for pass transistor-based synaptic thin-film transistor (S-TFT) cells through a contact ideality factor. For the low power characteristics of the S-TFT cells, the TFTs can be operated in the sub-threshold region. Here, because of the contact resistance between the channel and electrodes (i.e., source and drain), an effective input voltage can be insufficient for the sub-threshold operation of the S-TFTs. To overcome this, a higher input voltage (V<inline-formula> <tex-math>${}_{mathrm {I}}$ </tex-math></inline-formula>) can be applied to the S-TFTs. In this case, from the experimental data of single S-TFTs, the enhanced weight-update characteristics are found whereas the power consumption is increased compared to the case of a reduced VI. As a result, a trade-off between the weight-update and low power characteristics is observed for the single S-TFTs. Here, to minimize the power dissipation, an S-TFT cell can be employed, where an S-TFT is connected in series with a load TFT. However, for the S-TFT cells, the unexpected updates of the synaptic weight (<inline-formula> <tex-math>$text{w}$ </tex-math></inline-formula>) are presented due to the implicit dependence of the <inline-formula> <tex-math>$text{w}$ </tex-math></inline-formula>. As an approach to solve this, a compact modeling with the Taylor series approximation of the output current can be applied at a sufficiently low VI, considering a contact ideality factor. When this compact model in the sub-threshold region is employed, despite the reduced VI, it shows a good agreement with the experimental results.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"470-476"},"PeriodicalIF":2.9,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11611193","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}