IEEE Journal of the Electron Devices Society最新文献_第7页

Investigation of Nitrogen-Based Plasma Passivation on GaN RF HEMTs Using Various Precursors 使用各种前驱体对氮基等离子体钝化 GaN 射频 HEMT 的研究

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-11 DOI: 10.1109/JEDS.2024.3412186

Qiaoyu Hu;Wei-Chih Cheng;Xiguang Chen;Chenkai Deng;Lina Liao;Wenmao Li;Yang Jiang;Jiaqi He;Yi Zhang;Chuying Tang;Peiran Wang;Kangyao Wen;Fangzhou Du;Yifan Cui;Mujun Li;Wenyue Yu;Robert Sokolovskij;Nick Tao;Qing Wang;Hongyu Yu

{"title":"Investigation of Nitrogen-Based Plasma Passivation on GaN RF HEMTs Using Various Precursors","authors":"Qiaoyu Hu;Wei-Chih Cheng;Xiguang Chen;Chenkai Deng;Lina Liao;Wenmao Li;Yang Jiang;Jiaqi He;Yi Zhang;Chuying Tang;Peiran Wang;Kangyao Wen;Fangzhou Du;Yifan Cui;Mujun Li;Wenyue Yu;Robert Sokolovskij;Nick Tao;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2024.3412186","DOIUrl":"10.1109/JEDS.2024.3412186","url":null,"abstract":"This study investigates the DC and RF performance of RF GaN High Electron Mobility Transistors (HEMTs) subjected to surface pretreatments by N\u00002\u0000 and N\u00002\u0000O plasma. The filling of nitrogen vacancies or the passivation effect introduced by the thin GaON layer result in enhanced DC characteristics and RF performance for devices treated with nitrogen-based plasma. Compared to the untreated device, the device treated with N\u00002\u0000 plasma exhibited a significant improvement in performance, i.e., the saturated current increased by approximately 16%, the characteristic frequency (f\u0000T\u0000) had an increase of 27.6 GHz, the maximum oscillating frequency (f\u0000max\u0000) increased by 60.4 GHz. Furthermore, the breakdown voltage had a 10.7% increase, and the dynamic/static on-resistance ratio decreased from 1.34 to 1.18. These results highlight the potential of nitrogen-based plasma treatments in improving the performance of RF GaN HEMTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10552704","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures 全面评估无结和反转模式纳米线 MOSFET 在高温下的性能

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-05 DOI: 10.1109/JEDS.2024.3409579

Rhaycen R. Prates;Sylvain Barraud;Mikael Cassé;Maud Vinet;Olivier Faynot;Marcelo A. Pavanello

{"title":"Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures","authors":"Rhaycen R. Prates;Sylvain Barraud;Mikael Cassé;Maud Vinet;Olivier Faynot;Marcelo A. Pavanello","doi":"10.1109/JEDS.2024.3409579","DOIUrl":"10.1109/JEDS.2024.3409579","url":null,"abstract":"This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar gate stack and state-of-art process, in the temperature range from 300 K to 580 K. The comparative analysis is performed through the main electrical parameters of the devices, such as the threshold voltage, subthreshold current and slope, DIBL, conduction current, mobility, and maximum transconductance extracted from experimental data. Devices with different fin widths are compared. It is demonstrated that the inversion-mode nanowire transistors present higher performance with three times higher maximum transconductance and conduction current and twice higher low field mobility than the junctionless’ with a fin width of 10 nm at a fixed temperature. On the other hand, the junctionless nanowire transistors presented higher thermal stability of their electrical parameters with a 75% lower variation of maximum transconductance with temperature, 77% lower maximum transconductance variation with temperature, and 22% lower temperature coefficient of mobility.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10549873","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing Interpretability of Neural Compact Models: Toward Reliable Device Modeling 增强神经紧凑模型的可解释性：实现可靠的设备建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-04 DOI: 10.1109/JEDS.2024.3409572

Chanwoo Park;Hyunbo Cho;Jungwoo Lee

{"title":"Enhancing Interpretability of Neural Compact Models: Toward Reliable Device Modeling","authors":"Chanwoo Park;Hyunbo Cho;Jungwoo Lee","doi":"10.1109/JEDS.2024.3409572","DOIUrl":"10.1109/JEDS.2024.3409572","url":null,"abstract":"Neural Compact Models (NCMs) have emerged as a crucial tool to meet the stringent demands of Design-Technology Co-Optimization (DTCO) and to overcome the complexities and prolonged development cycles encountered in traditional compact model creation. Despite their efficiency in simulating electronic devices, a significant barrier to the widespread adoption of NCMs in the industry remains: the lack of interpretability. In the semiconductor sector, where inaccuracies or failures can lead to considerable financial consequences, it is critical to ensure that the model’s predictions are both understandable and reliable. This study aims to enhance the interpretability of NCMs used for I-V and C-V characterizations by clarifying the physical significance of latent vectors. A regularization technique is employed to disentangle features within the latent space, and interpolation is used to visualize and elucidate each dimension’s physical impact. Our approach, which offers interpretable insights into the model’s functionality, seeks to encourage broader implementation of NCMs in the industry, thus accelerating advancements in DTCO.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10547540","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation on the Dynamic Characteristics of Hydrogen Plasma Treated p-GaN HEMTs Circuit Using ASM-GaN Model 利用 ASM-GaN 模型研究氢等离子体处理 p-GaN HEMT 电路的动态特性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-06-03 DOI: 10.1109/JEDS.2024.3407098

Fan Li;Shiqiang Wu;Ang Li;Yuhao Zhu;Miao Cui;Jiangmin Gu;Ping Zhang;Yinchao Zhao;Huiqing Wen;Wen Liu

{"title":"Investigation on the Dynamic Characteristics of Hydrogen Plasma Treated p-GaN HEMTs Circuit Using ASM-GaN Model","authors":"Fan Li;Shiqiang Wu;Ang Li;Yuhao Zhu;Miao Cui;Jiangmin Gu;Ping Zhang;Yinchao Zhao;Huiqing Wen;Wen Liu","doi":"10.1109/JEDS.2024.3407098","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3407098","url":null,"abstract":"This study demonstrates the first work that achieves accurate modeling of Hydrogen plasmatreated (H-treated) p-GaN gate devices with the ASM-GaN model, facilitating simulations for applications in monolithic integrated circuit (IC) design. The workflow for ASM-GaN model parameter extraction and optimization using IC-CAP is proposed. The I-V characteristics of both Enhancement / Depletion (E/D) mode devices are modeled and fitted. The impact of device capacitance on the dynamic properties of monolithic IC is investigated through the ASM model. The results demonstrate that Cds, Cgd, and Cgs have different effects on the monolithic logic circuit performances. The high-level fitting of experimental data and circuit simulation of Inverter, NAND, and Comparator circuits proves the credibility of the modeling workflow and device capacitance modulation. This work provides a method to speed up the GaN monolithic IC design by accurate modeling with fast parameter extraction workflow regardless of the fabrication process. The reliable prediction of the circuit’s dynamic performance will lay the foundation for designing and scaling up the GaN monolithic IC application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10543269","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A General Toolkit for Advanced Semiconductor Transistors: From Simulation to Machine Learning 先进半导体晶体管通用工具包：从模拟到机器学习

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-05-16 DOI: 10.1109/jeds.2024.3401852

Antonio J. García-Loureiro, Natalia Seoane, Julian G. Fernández, Enrique Comesaña

引用次数: 0

HCMS: A Hybrid Conductance Modulation Scheme Based on Cell-to-Cell Z-Interference for 3D NAND Neuromorphic Computing HCMS：基于细胞间 Z 干涉的混合电导调制方案，用于 3D NAND 神经形态计算

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-05-06 DOI: 10.1109/jeds.2024.3397005

Anyi Zhu, Lei Jin, Jianquan Jia, Tianchun Ye, Ming Zeng, Zongliang Huo

引用次数: 0

Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology 65 纳米 CMOS 技术的低温小尺寸效应和面向设计的可扩展紧凑型建模

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-26 DOI: 10.1109/JEDS.2024.3394167

Alberto Gatti;Filip Tavernier

引用次数: 0

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory 用于可靠无电容存储器的独立双栅 BEOL 晶体管的基于物理的紧凑模型

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-25 DOI: 10.1109/JEDS.2024.3393418

Lihua Xu;Kaifei Chen;Zhi Li;Yue Zhao;Lingfei Wang;Ling Li

{"title":"Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory","authors":"Lihua Xu;Kaifei Chen;Zhi Li;Yue Zhao;Lingfei Wang;Ling Li","doi":"10.1109/JEDS.2024.3393418","DOIUrl":"10.1109/JEDS.2024.3393418","url":null,"abstract":"Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi-gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to \u0000<inline-formula> <tex-math>$sim ~50$ </tex-math></inline-formula>\u0000 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation-resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10508593","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140806832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Heat Generation Mechanisms of Self-Heating Effects in SOI-MOS SOI-MOS 中自热效应的发热机制

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-24 DOI: 10.1109/JEDS.2024.3393019

Zheng-Lai Tang;Bing-Yang Cao

{"title":"Heat Generation Mechanisms of Self-Heating Effects in SOI-MOS","authors":"Zheng-Lai Tang;Bing-Yang Cao","doi":"10.1109/JEDS.2024.3393019","DOIUrl":"10.1109/JEDS.2024.3393019","url":null,"abstract":"The development of microelectronic devices to the nanoscale intensifies self-heating challenges, affecting efficiency and durability. Understanding the mechanisms of heat generation at this scale is crucial, yet research extending beyond Joule heat remains limited. This paper simulates the self-heating effect of Silicon-On-Insulator Metal-Oxide-Semiconductor Field Effect Transistors (SOI-MOS) at the nanoscale and researches the characteristic and influence of different heat generation mechanisms, including the Joule heat, recombination heat and Peltier-Thomson heat. Our results provide a detailed two-dimensional distribution and intensity of various heat generation mechanisms within the silicon channel layer. It is found that Peltier-Thomson heat has the same magnitude as Joule heat at the nanoscale, and exhibits an alternating distribution pattern of hot and cold sources under the gate. But recombination heat is relatively negligible. The analysis of the influence of different heat mechanisms emphasizes the important role of Joule heat. While the offset effect limits the impact of Peltier-Thomson heat, its significance to device thermal performance should not be ignored. More importantly, this study investigates the impact of characteristic size on different heat generation mechanisms, revealing the size dependence of Peltier-Thomson heat.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10508189","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140804707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comparative Study on the Effects of Planarity of Access Region on the Low-Frequency Noise Performance of InAlN/GaN HFETs 接入区平面度对 InAlN/GaN 高频晶体管低频噪声性能影响的比较研究

IF 2.3 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2024-04-22 DOI: 10.1109/JEDS.2024.3392174

Yatexu Patel;Pouya Valizadeh

引用次数: 0