Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology

Abstract

This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of $\Delta $ Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.