IEEE Journal of the Electron Devices Society最新文献_第8页

Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs 了解Si - n- finet在交流正偏置温度不稳定应力下产生陷阱的频率依赖性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-09 DOI: 10.1109/JEDS.2025.3567049

Yunfei Shi;Hao Chang;Hong Yang;Qiangzhu Zhang;Qianqian Liu;Bo Tang;Longda Zhou;Zhigang Ji;Junjie Li;Xiaobin He;Junfeng Li;Huaxiang Yin;Xiaolei Wang;Jun Luo;Wenwu Wang

{"title":"Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs","authors":"Yunfei Shi;Hao Chang;Hong Yang;Qiangzhu Zhang;Qianqian Liu;Bo Tang;Longda Zhou;Zhigang Ji;Junjie Li;Xiaobin He;Junfeng Li;Huaxiang Yin;Xiaolei Wang;Jun Luo;Wenwu Wang","doi":"10.1109/JEDS.2025.3567049","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3567049","url":null,"abstract":"In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and the discharging-based multi-pulse energy profiling (DMP) technique. The experimental results show that both interface trap generation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NIT) and bulk trap generation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NOT) of n-FinFET under AC PBTI stress are almost independent of the AC frequency. However, further analysis shows that <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NOT consists of shallow traps near EC of Si and deep traps near Ev of Si. Moreover, about 22% of deep traps decrease with shallow traps increasing under 1.4V overdrive voltage (Vov) at 125°C with AC bias frequency increasing from 10 Hz to 1 MHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"450-455"},"PeriodicalIF":2.0,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10994476","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Characteristics Enhancement of Drain-Extended FinFETs for System on Chip Applications With Dual High-k Field Plates 双高k场极板用于片上系统应用的漏极扩展finfet的热特性增强

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-06 DOI: 10.1109/JEDS.2025.3548595

Yeonsil Yang;Jongmin Lee;Jang Hyun Kim

{"title":"Thermal Characteristics Enhancement of Drain-Extended FinFETs for System on Chip Applications With Dual High-k Field Plates","authors":"Yeonsil Yang;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2025.3548595","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548595","url":null,"abstract":"In this paper, we analyze the electrical and thermal characteristics through Drain-Extended Fin Field-effect Transistor (DeFinFET) using separated high-k field plates. In this article, we first compare the structure using silicon dioxide (SiO2) as the field plate near the drain with that using aluminum oxide (Al2O3). The maximum lattice temperature (<inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula>) in the hafnium oxide (HfO2)/SiO2 structure is 391.953 K under the same current condition, whereas <inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula> is reduced to 360.941 K in the HfO2/Al2O3 structure, indicating improved thermal management. Similarly, the thermal resistance <inline-formula> <tex-math>$(R_th)$ </tex-math></inline-formula> is reduced by 8.73% in the Al2O3 based structure, indicating improved thermal characteristics. Heat flux analysis results show that 60.1% of the generated heat is dissipated through the extended drain region, which identifies the heat dissipation path of the device. And when the length of the Al2O3 field plate in the HfO2/Al2O3 structure was changed to 20 nm, 40 nm, 60 nm, and 80 nm, the <inline-formula> <tex-math>$R_{mathrm{th}}$ </tex-math></inline-formula> of the 80 nm configuration was found to achieve the best thermal performance with a thermal resistance of 217.091 μm · K/mW. In addition, in this structure, the drain current reduction rate due to SHE was the lowest at 12.1%, and excellent breakdown voltage <inline-formula> <tex-math>$(V_{mathrm{BD}})$ </tex-math></inline-formula> was derived because the electric field was not concentrated at the field plate junction near the drain. Consequently, the proposed device has potential application to high voltage (HV) System on Chip (SoC).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"182-188"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915199","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection 半导体制造环境中基于ESD事件检测芯片的ESD实时监测与控制

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-06 DOI: 10.1109/JEDS.2025.3548886

Chang-Jiun Lai;Ming-Dou Ker

{"title":"Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection","authors":"Chang-Jiun Lai;Ming-Dou Ker","doi":"10.1109/JEDS.2025.3548886","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548886","url":null,"abstract":"Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"252-262"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Prediction of Single Event Effect in Inverter Circuit Based on Deep Learning 基于深度学习的逆变电路单事件效应预测

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-05 DOI: 10.1109/JEDS.2025.3561075

Jin Huang;Rong Zhao;Shulong Wang;Xingyuan Yan;Hao Zhou;Liutao Li;Shupeng Chen;Hongxia Liu

{"title":"Prediction of Single Event Effect in Inverter Circuit Based on Deep Learning","authors":"Jin Huang;Rong Zhao;Shulong Wang;Xingyuan Yan;Hao Zhou;Liutao Li;Shupeng Chen;Hongxia Liu","doi":"10.1109/JEDS.2025.3561075","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3561075","url":null,"abstract":"Fully Depleted Silicon on Insulator (FDSOI) technology can solve the short channel effect very effectively, with low power consumption, and low voltage, and can improve the subthreshold characteristics of the device. In addition, FDSOI devices have good radiation resistance, which has become an important research object in the field of device research. Single event effect (SEE) is an important index of radiation resistance of FDSOI devices. At present, the research on SEE of FDSOI devices typically employs heavy-ion irradiation experiments and TCAD software simulations. Taking FDSOI technology as an example, this paper presents a research method of device modeling and performance prediction based on deep learning. The accuracy of the peak of transient current <inline-formula> <tex-math>$(I_{peak})$ </tex-math></inline-formula> predicted by this method is 96.45%, the accuracy of total collected charge <inline-formula> <tex-math>$(Q_{total})$ </tex-math></inline-formula> is 97.86%, and the determination coefficient of drain transient current pulse (It) is 0.97717. This method can obviously improve the simulation speed and reduce the calculation cost, and provide a new feasible method for the research of FDSOI devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"431-438"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10982521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Corrections to “Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure” 对“GeSn/GeSiSn双势垒结构中空穴共振隧道负差分电阻的出现”的修正

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-05 DOI: 10.1109/JEDS.2025.3542189

Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka

引用次数: 0

Compact Modeling of 3D NAND Flash Memory With Ferroelectric Characteristics: A Comparative Analysis of O/N/O and O/N/F Structures 具有铁电特性的三维NAND闪存的紧凑建模：O/N/O和O/N/F结构的比较分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-05 DOI: 10.1109/JEDS.2025.3567077

Sunghyun Woo;Jihwan Lee;Gyunseok Ryu;Myounggon Kang

引用次数: 0

Channel Length Dependence of Effective Barrier Height Experienced by Charge Carriers in Schottky-Barrier Transistors Based on Si-Nanowire Arrays 基于硅纳米线阵列的肖特基势垒晶体管中载流子所经历的有效势垒高度的沟道长度依赖性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-04 DOI: 10.1109/JEDS.2025.3547860

Dae-Young Jeon;So Jeong Park;Sebastian Pregl;Jens Trommer;André Heinzig;Thomas Mikolajick;Walter M. Weber

引用次数: 0

Advanced Microfluidic Biofuel Cells Using Gold and Silver Leaf on Paper and PDMS Substrates: Toward Implantable Energy Solution 在纸和PDMS衬底上使用金和银叶子的先进微流控生物燃料电池：迈向可植入的能量解决方案

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-04 DOI: 10.1109/JEDS.2025.3547869

S. Vanmathi;Sanket Goel

{"title":"Advanced Microfluidic Biofuel Cells Using Gold and Silver Leaf on Paper and PDMS Substrates: Toward Implantable Energy Solution","authors":"S. Vanmathi;Sanket Goel","doi":"10.1109/JEDS.2025.3547869","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547869","url":null,"abstract":"An exploration of new and simplified electrode materials such as gold leaf (GL), and silver leaf (SL) based approaches to enhance the efficiency and scalability of microfluidic biofuel cell renewable energy sources has generated significant interest. Our research aims to utilize the unique properties of these materials to create advanced biofuel cells, with a specific focus on implantable devices. By employing nanoporous gold and patterned silver leaf, are designing flexible, efficient, and scalable biofuel cells that have the potential to revolutionize energy solutions in medical and wearable technologies. Microfluidic biofuel cells with nanostructured gold and silver leaf devices harvest ultra-low power energy, making them more practical for real-world applications. The gold and silver leaf enzymatic biofuel cell (LEBFC) operates using glucose as fuel, with glucose oxidase functioning at the anode and laccase at the cathode, both coating the GL and SL bioelectrodes. These leaf microfluidic devices, fabricated using polydimethylsiloxane (PDMS) and filter paper, demonstrated a peak open circuit voltage of 197 mV and 448 mV, along with a maximum power density of <inline-formula> <tex-math>$28.7 mu mathrm{~W} / mathrm{cm}^2$ </tex-math></inline-formula> and <inline-formula> <tex-math>$93.6 mu mathrm{~W} / mathrm{cm}^2$ </tex-math></inline-formula>, respectively. Such flexible devices are lightweight, non-toxic, edible, and biodegradable, designed for optimal load connection to ensure stable performance while reducing weight. Please replace with this sentence. It opens new opportunities for sustainable power generation and offers promising applications in wearable, implantable, and portable microelectronic devices, where reliable, low-power energy sources are inexpensive.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"173-181"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909661","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal Stability of Gate Driver Circuits Based on 4H-SiC MOSFETs at 300°C for High-Power Applications 基于4H-SiC mosfet的栅极驱动电路在300°C下的热稳定性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-03 DOI: 10.1109/JEDS.2025.3546959

Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki

{"title":"Thermal Stability of Gate Driver Circuits Based on 4H-SiC MOSFETs at 300°C for High-Power Applications","authors":"Vuong Van Cuong;Tatsuya Meguro;Seiji Ishikawa;Tomonori Maeda;Hiroshi Sezaki;Shin-Ichiro Kuroki","doi":"10.1109/JEDS.2025.3546959","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3546959","url":null,"abstract":"The operation and reliability of gate driver circuits based on 4H-SiC MOSFETs at temperatures up to 300°C were reported. Due to the advantages of 4H-SiC MOSFETs, the driver circuit can overcome limitations in complicated circuit design and power dissipation associated with SiC BJTbased technology. Additionally, the stability of implanted 4H-SiC resistors can address the reliability issues of SiC CMOS-based driver circuits, which are caused by the instability in the threshold voltage of P-channel SiC MOSFETs. In this study, the switching characteristics of the gate driver circuit were improved when the ambient temperature increased. The decrease of threshold voltage and increase of carrier mobility of the 4H-SiC MOSFETs may account for the improvement in switching characteristics of the gate driver circuit. The output signal of the gate driver circuit still showed proper characteristics after 600 min of continuous operation at 300°C in an air ambient. These results indicate that the gate driver circuit based on 4H-SiC MOSFET technology is promising to apply for high power applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"161-167"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10908627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Analysis of Rare-Earth Doped Oxide Thin-Film Transistors Using Neural Network Method 基于神经网络方法的稀土掺杂氧化物薄膜晶体管性能分析

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-03-03 DOI: 10.1109/JEDS.2025.3547646

Zengyi Peng;Xianglan Huang;Yuanyi Shen;Weijing Wu;Min Li;Miao Xu;Lei Wang;Zhenghui Gu;Zhuliang Yu;Junbiao Peng

{"title":"Performance Analysis of Rare-Earth Doped Oxide Thin-Film Transistors Using Neural Network Method","authors":"Zengyi Peng;Xianglan Huang;Yuanyi Shen;Weijing Wu;Min Li;Miao Xu;Lei Wang;Zhenghui Gu;Zhuliang Yu;Junbiao Peng","doi":"10.1109/JEDS.2025.3547646","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547646","url":null,"abstract":"The work analyzes the key impact factors on the performances of rare-earth element doped oxide thin-film transistors (TFTs), which are potentially used for high performance displays, by comparatively using a Bayesian Neural Network (BNN) method and Artificial Neural Network (ANN) method based on published and self-experimental data which was exhaustively collected. Both BNN and ANN methods can effectively identify the primary impact factors among rare-earth element type, doping concentration, thin film thickness, channel length and width, which are key factors to determine the TFTs performances. Comparisons between the BNN and ANN methods, the BNN approach offers more reliable and robust predictions on the dataset. Accordingly, the efficient neural network models tailored to the data features were accurately established. A key outcome from the BNN models is the relative importance ranking of the influence factors and relationship between the carrier mobility and element type, concentration as well. To the TFT mobility, rare-earth element concentration is the most critical factor, suggesting lower concentration exhibited higher mobility, followed by the rare-earth element type. To the sub-threshold swing performance of TFTs, the rare-earth element type is the most significant influence factor, suggesting higher valence rare-earth is superior to lower valence one, followed by the element concentration. The results are basically consistent with experimental tendency. These insights could effectively guide the design of oxide semiconductor materials and TFT device structure, to achieve high-performance (high mobility and high stability) oxide TFT devices for displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"263-269"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909085","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0