IEEE Journal of the Electron Devices Society最新文献_第8页

Electrical and 850 nm Optical Characterization of Back-Gate Controlled 22 nm FDSOI PIN-Diodes Without Front-Gate 无前门的22nm后栅控制FDSOI pin -二极管的电学和850nm光学特性

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-31 DOI: 10.1109/JEDS.2025.3537290

Jelle H. T. Bakker;Marcin Ł. Motycki;Raymond J. E. Hueting;Anne-Johan Annema;Mark S. Oude Alink

{"title":"Electrical and 850 nm Optical Characterization of Back-Gate Controlled 22 nm FDSOI PIN-Diodes Without Front-Gate","authors":"Jelle H. T. Bakker;Marcin Ł. Motycki;Raymond J. E. Hueting;Anne-Johan Annema;Mark S. Oude Alink","doi":"10.1109/JEDS.2025.3537290","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3537290","url":null,"abstract":"We present electrical and optical <inline-formula> <tex-math>$(lambda =rm {850~nm })$ </tex-math></inline-formula> measurement results of back-gate controlled SOI PIN-diodes without a front-gate, with an intrinsic Si film thickness of only <inline-formula> <tex-math>${sim }rm 6nm $ </tex-math></inline-formula>. These ultrathin-body PIN-diodes were fabricated as exploratory devices in a commercially available Fully-Depleted Silicon-On-Insulator (FDSOI) technology, without requiring additional process steps. We show that electrostatic back-gate tuning significantly affects the electrical characteristics and optical responsivity <inline-formula> <tex-math>$({{R_{mathrm { o}}}{}})$ </tex-math></inline-formula>. This leads to a novel method to extract the optimal back-gate bias for maximum <inline-formula> <tex-math>${R_{mathrm { o}}}{}$ </tex-math></inline-formula> from electrical measurements. The maximal measured <inline-formula> <tex-math>${R_{mathrm { o}}}{}$ </tex-math></inline-formula> at 0V bias across the diode and with optimal back-gate bias equals <inline-formula> <tex-math>$62{mu }$ </tex-math></inline-formula>A /W, with a -3dB bandwidth of 5.9GHz, and a -6dB bandwidth of 15GHz. These PIN-diodes potentially open the way to new (THz) circuits, sensors, novel/complementary process control monitoring structures, and optical applications. They also enable interaction between the hybrid (bulk) and SOI devices, which is a unique feature of FDSOI technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"190-199"},"PeriodicalIF":2.0,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10859268","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Call for Nominations for Editor-in-Chief 征集总编辑提名

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3536136

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Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29 宣布IEEE/Optica出版集团光波技术杂志特刊：OFS-29

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528210

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2024 Index IEEE Journal of the Electron Devices Society Vol. 12 电子器件学会杂志第12卷

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IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3536577

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Wide Band Gap Semiconductors for Automotive Applications 汽车用宽带隙半导体

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528208

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Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications 探索令人兴奋的多功能氧化物基电子器件世界：从材料到系统级应用

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-30 DOI: 10.1109/JEDS.2025.3528209

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Transfer-Matrix Modeling of the Access Region Resistance in Graphene Based Dirac-Source FETs 石墨烯基Dirac-Source fet通路电阻的传递矩阵建模

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-24 DOI: 10.1109/JEDS.2025.3533599

Erica Baccichetti;David Esseni

{"title":"Transfer-Matrix Modeling of the Access Region Resistance in Graphene Based Dirac-Source FETs","authors":"Erica Baccichetti;David Esseni","doi":"10.1109/JEDS.2025.3533599","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3533599","url":null,"abstract":"In this paper we first present a model based on the transfer-matrix methodology to describe the ballistic resistance in a graphene <inline-formula> <tex-math>$p$ </tex-math></inline-formula>–<inline-formula> <tex-math>$n$ </tex-math></inline-formula> junction, and employ the model in Dirac-Source FETs. In fact, the access region of a graphene based Dirac-Source FET includes a <inline-formula> <tex-math>$p$ </tex-math></inline-formula>–<inline-formula> <tex-math>$n$ </tex-math></inline-formula> junction, and we show that this has a sizeable impact on the on-state current of these transistors. In particular, we first validate our model by comparing the calculated <inline-formula> <tex-math>$p$ </tex-math></inline-formula>–<inline-formula> <tex-math>$n$ </tex-math></inline-formula> junction resistance with previous experiments and simulations. Then, we exploit the transfer-matrix description into a virtual-source model for nanoscale Dirac-Source FETs, and discuss the influence on the <inline-formula> <tex-math>$textrm {I}_{DS}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$textrm {V}_{GS}$ </tex-math></inline-formula> curves of the <inline-formula> <tex-math>$p$ </tex-math></inline-formula>–<inline-formula> <tex-math>$n$ </tex-math></inline-formula> junction that is embedded in the access region of the device.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"200-209"},"PeriodicalIF":2.0,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852170","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Self-Assembled Multilayer Single-Walled Carbon Nanotube Thin Film Transistors and Doping Regulation 自组装多层单壁碳纳米管薄膜晶体管及掺杂调控

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-22 DOI: 10.1109/JEDS.2025.3532593

Xiangxiang Gao;Zhenhua Lin;Jincheng Zhang;Yue Hao;Jingjing Chang

{"title":"Self-Assembled Multilayer Single-Walled Carbon Nanotube Thin Film Transistors and Doping Regulation","authors":"Xiangxiang Gao;Zhenhua Lin;Jincheng Zhang;Yue Hao;Jingjing Chang","doi":"10.1109/JEDS.2025.3532593","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3532593","url":null,"abstract":"Semiconducting single-walled carbon nanotubes (SWCNTs) have stimulated tremendous research interest in high performance electronics thanks to their impressive mechanical and electronic properties. However, it is still challenging to prepare wafer-scale SWCNTs thin films and fine-tunable device performance. Here, layer-by-layer (LbL) assembly is presented as an effective approach to prepare multilayer SWCNT thin films by coordinating poly(diallyldimethylammonium chloride) (PDDA) with SWCNTs. The thickness of SWCNTs thin film is linearly dependent on the bilayer numbers. Thin film transistors (TFTs) fabricated from SWCNTs thin films showed prominent device performance with a mobility of <inline-formula> <tex-math>$rm 15.3 cm_{2} cdot V_{1}cdot s_{1}$ </tex-math></inline-formula>. Further the molecular dopants bis (trifluoromethane) sulfonimide (TFSI), with strong electro-withdrawing capability and protonating nature, was utilized to functionalize SWCNTs thin films, thereby regulating their electronic performances. The TFSI surface functionalization can remove excess electrons from SWCNT thin films, resulting in improved on-state current, increased carrier mobility and positively shifted threshold voltage. The molecular doping holds great promise for the future realization of large-area, low-power logic circuits and high-performance electronics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"93-97"},"PeriodicalIF":2.0,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10849582","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering 利用源/漏极掺杂技术优化纳米片GAA CMOS晶体管和6T-SRAM电池的性能

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-20 DOI: 10.1109/JEDS.2025.3531432

Xuexiang Zhang;Qingkun Li;Lei Cao;Qingzhu Zhang;Renjie Jiang;Peng Wang;Jiaxin Yao;Huaxiang Yin

{"title":"Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering","authors":"Xuexiang Zhang;Qingkun Li;Lei Cao;Qingzhu Zhang;Renjie Jiang;Peng Wang;Jiaxin Yao;Huaxiang Yin","doi":"10.1109/JEDS.2025.3531432","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3531432","url":null,"abstract":"As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current (<inline-formula> <tex-math>$rm I_{mathrm {off}}$ </tex-math></inline-formula>) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"86-92"},"PeriodicalIF":2.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10845751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure GeSn/GeSiSn双势垒结构空穴共振隧道负差分电阻的产生

IF 2 3区工程技术

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-13 DOI: 10.1109/JEDS.2025.3529079

Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka

{"title":"Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure","authors":"Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka","doi":"10.1109/JEDS.2025.3529079","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3529079","url":null,"abstract":"We examined the fabrication and the operation of GeSn/GeSiSn resonant tunneling diode (RTD) and demonstrated the observation of negative differential resistance (NDR) at a low temperature through the hole resonant tunneling. First, we revealed the possible designed contents of GeSiSn to Si and Sn of 40–60% and ∼10%, respectively to achieve the valence band offset over 0.3 eV with sustaining the biaxial strain value less than 1.0%, which is an important factor for the pseudomorphic growth of GeSn/GeSiSn heterostructure on Ge. Then, we successfully fabricated GeSn/GeSiSn RTD with a double barrier structure composed of ultra-thin GeSiSn barriers and GeSn well, which has the steep heterointerface. The current-density–voltage (J–V) characteristics at 10 K of the fabricated GeSn/GeSiSn RTD showed NDRs at applied voltages of approximately −1.5 and −1.8 V with peak to valley current ratio of 1.06 and 1.14, respectively, and peak current density of ∼3 and ∼5 kA/cm2, respectively. We also demonstrated that the observed NDR is reproducible. The quantum level and J–V simulations suggests that these two NDRs would originate from the hole resonant tunneling current through the first and second quantum levels formed in the GeSn well layer. Furthermore, we also discussed issues newly found in this study and future remarks of GeSn/GeSiSn heterostructures as RTD applications for the terahertz oscillator and the nonvolatile RAM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"79-85"},"PeriodicalIF":2.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839296","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0