一种使用直流电源缓冲器的低功耗LTPO扫描驱动电路

IF 2.4 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
SangWoon Lee;JungSuk Oh;HyeongMin Kim;YiKyoung You;Nack-Hyeon Keum;HeeJu Moon;SangHun Kim;KeeChan Park;Hwarim Im
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引用次数: 0

摘要

本文提出了一种新型低温多晶硅-氧化物(LTPO)扫描驱动电路,该电路集成了p沟道低温多晶硅(LTPS)薄膜晶体管(TFTs)和n沟道金属氧化物(MOx) tft。所提出的电路采用互补金属氧化物半导体逆变器作为输出缓冲器,允许低电平电压从直流电源传递到输出节点,而不依赖于时钟提供的自引导,这在大多数扫描驱动电路中通常需要驱动输出缓冲器。与传统的LTPO扫描驱动电路相比,该设计通过时钟信号减少了缓冲TFT的寄生电容充电/放电的功耗,显著降低了动态功耗高达74%。此外,所提出的电路减少了应用于MOx tft的正偏置,有效地缓解了应力条件。因此,所提出的电路可以通过减轻MOx tft的阈值电压偏移来提高长期可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Low-Power LTPO Scan Driver Circuit Using DC Power Supplied Buffer
This paper proposes a novel low-temperature polycrystalline silicon and oxide (LTPO) scan driver circuit integrating p-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and n-channel metal-oxide (MOx) TFTs. The proposed circuit employs a complementary metal-oxide-semiconductor inverter as an output buffer, allowing low-level voltage to be delivered from a DC power supply to the output node without relying on clock-supplied bootstrapping, which is typically required in most scan driver circuits to drive the output buffer. This design significantly lowers dynamic power consumption by up to 74% by reducing the power consumption due to charging/discharging the parasitic capacitance of the buffer TFT by the clock signals compared with the conventional LTPO scan driver circuits utilizing the clock-supplied bootstrapping method. Additionally, the proposed circuit reduces the positive bias applied to MOx TFTs to alleviate stress conditions effectively. Therefore, the proposed circuit can improve long-term reliability by mitigating the threshold voltage shifts of MOx TFTs.
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来源期刊
IEEE Journal of the Electron Devices Society
IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology
CiteScore
5.20
自引率
4.30%
发文量
124
审稿时长
9 weeks
期刊介绍: The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.
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