Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu
{"title":"应变工程二维 MoTe2 相变晶闸管的性能和可扩展性","authors":"Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu","doi":"10.1109/JEDS.2025.3556316","DOIUrl":null,"url":null,"abstract":"This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math>$\\leq 0.5$ </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math>$\\geq 10{^{{5}}}$ </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math>$\\leq 0.6\\mu $ </tex-math></inline-formula>m and A<inline-formula> <tex-math>$\\leq 0.3\\mu $ </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math>$\\leq 1.2\\mu $ </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math>$\\leq 65{^{\\text {o}}}$ </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"343-349"},"PeriodicalIF":2.0000,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945750","citationCount":"0","resultStr":"{\"title\":\"Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors\",\"authors\":\"Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu\",\"doi\":\"10.1109/JEDS.2025.3556316\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math>$\\\\leq 0.5$ </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math>$\\\\geq 10{^{{5}}}$ </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math>$\\\\leq 0.6\\\\mu $ </tex-math></inline-formula>m and A<inline-formula> <tex-math>$\\\\leq 0.3\\\\mu $ </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math>$\\\\leq 1.2\\\\mu $ </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math>$\\\\leq 65{^{\\\\text {o}}}$ </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.\",\"PeriodicalId\":13210,\"journal\":{\"name\":\"IEEE Journal of the Electron Devices Society\",\"volume\":\"13 \",\"pages\":\"343-349\"},\"PeriodicalIF\":2.0000,\"publicationDate\":\"2025-03-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945750\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of the Electron Devices Society\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10945750/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10945750/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors
This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage ($\leq 0.5$ V) and high on/off ratio $\geq 10{^{{5}}}$ . Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L$\leq 0.6\mu $ m and A$\leq 0.3\mu $ m2). Smaller flake contact perimeters $\leq 1.2\mu $ m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles $\leq 65{^{\text {o}}}$ likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.