IGZO 2T1C DRAM With Low Operation Voltage and High Current Window

Abstract

In this work, we propose and experimentally demonstrate a novel IGZO 2T1C cell. Novel bit-cell applies read-word-line to the capacitor terminal and utilize the coupling effect of the capacitor to achieve storage node (SN) voltage modulation. By this design, a larger current window can be achieved by biasing the read transistor to the region with the steepest subthreshold slope. Through optimizing the gate dielectric thickness, DG IGZO transistor of ${\mathrm { L}}_{\mathrm {CH}}$ =50 nm achieves ultra-low subthreshold slope of 63.9 mV/dec. Based on optimized devices, the implementation of DRAM features an ultra-high current window (Idata‘1’/Idata‘0’) of $\sim {\mathrm {10}}^{\mathrm {3}}$ at ultra-low write voltage of 0.2 V. Furthermore, the proposed novel 2T1C bit-cell provides a more reliable gate-controlled read scheme. This work paves the forward way for low voltage and reliable sensing IGZO DRAM application.