Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)

IF 2 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of the Electron Devices Society Pub Date : 2025-02-27 DOI:10.1109/JEDS.2025.3546314

Sandeep Semwal;Pin Su

{"title":"Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)","authors":"Sandeep Semwal;Pin Su","doi":"10.1109/JEDS.2025.3546314","DOIUrl":null,"url":null,"abstract":"This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configurations through experimentally calibrated Landau-Khalatnikov model for an ultrathin (1.5 nm) single-crystalline HZO ferroelectric (FE). Results show a suppressed improvement with MFMIS topology over the MFIS topology in the subthreshold region if implemented with the CFET architecture due to the CFET-specific common-gate structure. We also propose an alternative MFMIS NC-CFET design with the FE stacked only at the top of the device (~5.3 times lower FE area compared to conventional MFMIS NC-CFET), which can significantly improve the capacitance matching and subthreshold swing provided an FE layer with relatively higher remnant polarization is used. In addition, a design guideline to optimize MFIS NC-CFET is also highlighted. Our study may provide insights into device design for future energy-efficient electronics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"154-160"},"PeriodicalIF":2.0000,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10906432","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10906432/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configurations through experimentally calibrated Landau-Khalatnikov model for an ultrathin (1.5 nm) single-crystalline HZO ferroelectric (FE). Results show a suppressed improvement with MFMIS topology over the MFIS topology in the subthreshold region if implemented with the CFET architecture due to the CFET-specific common-gate structure. We also propose an alternative MFMIS NC-CFET design with the FE stacked only at the top of the device (~5.3 times lower FE area compared to conventional MFMIS NC-CFET), which can significantly improve the capacitance matching and subthreshold swing provided an FE layer with relatively higher remnant polarization is used. In addition, a design guideline to optimize MFIS NC-CFET is also highlighted. Our study may provide insights into device design for future energy-efficient electronics.

查看原文本刊更多论文

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology

CiteScore

5.20

自引率

4.30%

发文量

124

审稿时长

9 weeks

期刊介绍： The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.