IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第6页

A 2-MHz BW 64.5-dB SNDR 0.45-1.05 GHz Direct IF/RF Digitization Subsampling Bandpass DSM Utilizing a Capacitive-Stacking N-Path Filter 基于电容堆叠n路滤波器的2 mhz BW 64.5 db SNDR 0.45-1.05 GHz直接中频/射频数字化子采样带通DSM

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587662

Xiao Wang;Runkun Li;Xin Sun;Kong-Pang Pun

{"title":"A 2-MHz BW 64.5-dB SNDR 0.45-1.05 GHz Direct IF/RF Digitization Subsampling Bandpass DSM Utilizing a Capacitive-Stacking N-Path Filter","authors":"Xiao Wang;Runkun Li;Xin Sun;Kong-Pang Pun","doi":"10.1109/TCSII.2025.3587662","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587662","url":null,"abstract":"This brief presents a novel subsampling bandpass Delta-Sigma modulator (BPDSM) based on transconductor (Gm) - N-path filters (NPF) for direct radio-frequency (RF) / intermediate-frequency (IF) digitization. The proposed architecture introduces two key innovations. First, a subsampling technique is applied that places the input center frequency at <inline-formula> <tex-math>$(3/4) f_{S}$ </tex-math></inline-formula> (versus conventional <inline-formula> <tex-math>$f_{S}/4$ </tex-math></inline-formula> operation), where <inline-formula> <tex-math>$f_{S}$ </tex-math></inline-formula> is the sampling frequency. Second, a capacitive-stacking NPF that provides 6-dB passive gain is utilized for: (1) suppressing the amplifier’s thermal noise when referred to the modulator’s input; (2) improving the quantization noise shaping by eliminating redundant notches at even multiples of <inline-formula> <tex-math>$f_{S}/4$ </tex-math></inline-formula> in the modulator’s noise transfer function. Fabricated in 65-nm CMOS, the modulator prototype occupies 0.11 mm2 and achieves 0.45 - 1.05 GHz tunability, the highest upper frequency reported for Gm-NPF BPDSMs to the best of the authors’ knowledge. When clocked at 800-MHz, it demonstrates a 64.5-dB peak SNDR over 2-MHz bandwidth centered at 601-MHz, consuming 0.37 mW from a 1.2-V supply. The design records state-of-the-art figure of merit (FoM) values of 161.8 dB Schreier’s FoM and 67.4 fJ/conversion-step Walden’s FoM for BPDSMs operating above 450 MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1138-1142"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 26.5–29.5 GHz Doherty Phased-Array Transceiver Front-End With 7-Bit Phase Shifter and 16% Back-Off Drain Efficiency 26.5-29.5 GHz Doherty相控阵收发前端，7位移相器和16%回退漏极效率

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587850

Shaogang Wang;Huiyan Gao;Hang Lu;Yiwei Liu;Nayu Li;Chunyi Song;Zhiwei Xu

引用次数: 0

A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors 用于超大像素阵列CMOS图像传感器的高速双反馈环路列缓冲器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587906

Liu Suiyang;Guo Zhongjie;Xu Ruiming;Yu Ningmei

{"title":"A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors","authors":"Liu Suiyang;Guo Zhongjie;Xu Ruiming;Yu Ningmei","doi":"10.1109/TCSII.2025.3587906","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587906","url":null,"abstract":"With the development of stitching processes, the resolution of CMOS image sensors has significantly improved, especially in applications such as earth observation and deep space exploration. Although the column-parallel, row-serial readout has numerous advantages and is considered the ideal sensor architecture, it still has frame rate issues caused by the long length of the serial output bus, which leads to large parasitic parameters of the metal lines. Therefore, this brief proposes a dual feedback loop column buffer that implements parallel-serial conversion while introducing the switching on-resistance within the loop to reduce the settling time of the output signal and stabilize the phase margin. A chip containing <inline-formula> <tex-math>$12288{times }12288$ </tex-math></inline-formula> pixels was fabricated using CMOS 55nm 1P4M technology. With a 48-channel output, the chip achieves a frame rate of 10.36 fps. Compared to the single feedback loop column buffer, the risetime of the output signal is reduced by 23.4%, the falltime by 21.9%, and the overall frame rate is improved by 29.6%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1143-1147"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs 一个位级双计数器，支持低功耗高带宽vco - adc

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587495

Simon Ooghe;Brendan Saux;Tobias Cromheecke;Johan Raman;Pieter Rombouts

引用次数: 0

An I/Q Imbalance Calibration Scheme for 5G Direct-Conversion Transmitter 一种5G直接转换发射机I/Q不平衡校正方案

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-08 DOI: 10.1109/TCSII.2025.3586873

Seunghoon Lee;Sungbeom Kim;Donghun Lee;Inho Choi;Ho-Jin Song

引用次数: 0

An Ultra-Compact Ka-Band Folded Phased-Array Transceiver Front-End With Bidirectional 20-dB Gain Control 具有双向20db增益控制的超紧凑ka波段折叠相控阵收发器前端

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-08 DOI: 10.1109/TCSII.2025.3586977

Shiwei Wu;Dongfang Pan;Laifu Jin;Lin Cheng

引用次数: 0

An Energy-Efficient Image Deblurring Accelerator With Quad-Base-Quad-Scale Quantized Format and Layer Normalization-Aware Optimization 基于四基四尺度量化格式和层归一化感知优化的节能图像去模糊加速器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-07 DOI: 10.1109/TCSII.2025.3586657

Jinhoon Jo;Jueun Jung;Kyuho Jason Lee

{"title":"An Energy-Efficient Image Deblurring Accelerator With Quad-Base-Quad-Scale Quantized Format and Layer Normalization-Aware Optimization","authors":"Jinhoon Jo;Jueun Jung;Kyuho Jason Lee","doi":"10.1109/TCSII.2025.3586657","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3586657","url":null,"abstract":"This brief proposes a novel data-format-based image deblurring accelerator with layer normalization and UNet architecture optimization for mobile cameras. As the demand for photography in dynamic environments continues to grow and the limitations of physical stabilization are tightening, post-processing methods to restore sharp images have gained increasing attention, notably deblurring methods based on convolutional neural networks. However, their heavy computational cost hinders their integration into mobile computing platforms. The proposed accelerator enables energy-efficient acceleration of deblurring through the following three key features: 1) A Quad-base-Quad-scale Quantized format that maintains image quality with only 8-bit, reducing external memory access (EMA) by 33% and achieving 75.7% higher multiply-and-accumulation (MAC) energy efficiency compared to conventional 12-bit precision; 2) A Layer Normalization-Aware Optimization technique, enabling parallel normalization and fusion of affine transformation; 3) A dual-stationary systolic array architecture that selects the optimal dataflow for each UNet block based on processing element (PE) utilization. As a result, the proposed accelerator achieves 2.49 TOPS/W, which is <inline-formula> <tex-math>$2.23times $ </tex-math></inline-formula> higher than prior work, enabling energy-efficient deblurring for mobile applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1273-1277"},"PeriodicalIF":4.9,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead ZRHDC：一个轻量级的HDC架构，零ROM开销

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-04 DOI: 10.1109/TCSII.2025.3585931

Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao

{"title":"ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead","authors":"Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao","doi":"10.1109/TCSII.2025.3585931","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585931","url":null,"abstract":"Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2-<inline-formula> <tex-math>$8 times $ </tex-math></inline-formula> dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3-<inline-formula> <tex-math>$6 times $ </tex-math></inline-formula> area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1263-1267"},"PeriodicalIF":4.9,"publicationDate":"2025-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Chaotic Nature of Integer Sequences From Primitive Linear Feedback Shift Registers 原始线性反馈移位寄存器中整数序列的混沌性质

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-04 DOI: 10.1109/TCSII.2025.3585913

Hyojeong Choi;Gangsan Kim;Hong-Yeop Song;Hongjun Noh

引用次数: 0

High-Throughput Pseudo-Random Number Generators Over Discrete Chaos 离散混沌上的高吞吐量伪随机数发生器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-03 DOI: 10.1109/TCSII.2025.3585809

Carlos E. C. Souza;Davi Moreno;Matheus H. S. Sousa;Daniel P. B. Chaves;Cecilio Pimentel

引用次数: 0