{"title":"A 2-MHz BW 64.5-dB SNDR 0.45-1.05 GHz Direct IF/RF Digitization Subsampling Bandpass DSM Utilizing a Capacitive-Stacking N-Path Filter","authors":"Xiao Wang;Runkun Li;Xin Sun;Kong-Pang Pun","doi":"10.1109/TCSII.2025.3587662","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587662","url":null,"abstract":"This brief presents a novel subsampling bandpass Delta-Sigma modulator (BPDSM) based on transconductor (Gm) - N-path filters (NPF) for direct radio-frequency (RF) / intermediate-frequency (IF) digitization. The proposed architecture introduces two key innovations. First, a subsampling technique is applied that places the input center frequency at <inline-formula> <tex-math>$(3/4) f_{S}$ </tex-math></inline-formula> (versus conventional <inline-formula> <tex-math>$f_{S}/4$ </tex-math></inline-formula> operation), where <inline-formula> <tex-math>$f_{S}$ </tex-math></inline-formula> is the sampling frequency. Second, a capacitive-stacking NPF that provides 6-dB passive gain is utilized for: (1) suppressing the amplifier’s thermal noise when referred to the modulator’s input; (2) improving the quantization noise shaping by eliminating redundant notches at even multiples of <inline-formula> <tex-math>$f_{S}/4$ </tex-math></inline-formula> in the modulator’s noise transfer function. Fabricated in 65-nm CMOS, the modulator prototype occupies 0.11 mm2 and achieves 0.45 - 1.05 GHz tunability, the highest upper frequency reported for Gm-NPF BPDSMs to the best of the authors’ knowledge. When clocked at 800-MHz, it demonstrates a 64.5-dB peak SNDR over 2-MHz bandwidth centered at 601-MHz, consuming 0.37 mW from a 1.2-V supply. The design records state-of-the-art figure of merit (FoM) values of 161.8 dB Schreier’s FoM and 67.4 fJ/conversion-step Walden’s FoM for BPDSMs operating above 450 MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1138-1142"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors","authors":"Liu Suiyang;Guo Zhongjie;Xu Ruiming;Yu Ningmei","doi":"10.1109/TCSII.2025.3587906","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587906","url":null,"abstract":"With the development of stitching processes, the resolution of CMOS image sensors has significantly improved, especially in applications such as earth observation and deep space exploration. Although the column-parallel, row-serial readout has numerous advantages and is considered the ideal sensor architecture, it still has frame rate issues caused by the long length of the serial output bus, which leads to large parasitic parameters of the metal lines. Therefore, this brief proposes a dual feedback loop column buffer that implements parallel-serial conversion while introducing the switching on-resistance within the loop to reduce the settling time of the output signal and stabilize the phase margin. A chip containing <inline-formula> <tex-math>$12288{times }12288$ </tex-math></inline-formula> pixels was fabricated using CMOS 55nm 1P4M technology. With a 48-channel output, the chip achieves a frame rate of 10.36 fps. Compared to the single feedback loop column buffer, the risetime of the output signal is reduced by 23.4%, the falltime by 21.9%, and the overall frame rate is improved by 29.6%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1143-1147"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Simon Ooghe;Brendan Saux;Tobias Cromheecke;Johan Raman;Pieter Rombouts
{"title":"A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs","authors":"Simon Ooghe;Brendan Saux;Tobias Cromheecke;Johan Raman;Pieter Rombouts","doi":"10.1109/TCSII.2025.3587495","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587495","url":null,"abstract":"In this brief, a counter structure which facilitates the design of a coarse-fine voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) at high bandwidths is presented. A key challenge is the asynchrony between the coarse and fine counters for which it is quantitatively proven that effective ambiguity resolution is necessary to obtain a sufficient performance. To achieve this, a latch-based, bit-level redundant coarse counter featuring fast ambiguity resolution and operating at high VCO frequencies is presented. Using this novel counter structure a power-efficient VCO-ADC with a core area of 0.007 mm2 and a post-layout simulated figure-of-merit of 168 dB at a bandwidth of 100 MHz is demonstrated.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1133-1137"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11075872","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seunghoon Lee;Sungbeom Kim;Donghun Lee;Inho Choi;Ho-Jin Song
{"title":"An I/Q Imbalance Calibration Scheme for 5G Direct-Conversion Transmitter","authors":"Seunghoon Lee;Sungbeom Kim;Donghun Lee;Inho Choi;Ho-Jin Song","doi":"10.1109/TCSII.2025.3586873","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3586873","url":null,"abstract":"This brief presents an I/Q imbalance calibration scheme for a 5G direct-conversion transmitter (TX). By utilizing a simple 1-bit phase-to-digital converter and 9-bit digital-to-analog converter, a quadrature phase error associated with fabrication tolerances can be minimized effectively using a binary search algorithm. This approach implements a continuous, real-time calibration that adaptively adjusts the resistive components of the type-I polyphase filter in response to detected phase errors, thereby ensuring precise phase alignment by dynamically compensating for I/Q imbalance without interrupting the primary signal path. The proposed idea is demonstrated in the LO path of a 5G direct-conversion transmitter in a 65-nm bulk CMOS technology. The measured image rejection ratio and LO feedthrough suppression ratio are maintained less than −52 dBc and −37 dBc, respectively, in the range of 27.5-29.5 GHz. The TX can support a peak data rate of 4.8 Gb/s at 28.5 GHz using 64-QAM and an error vector magnitude of −27.3 dB.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1198-1202"},"PeriodicalIF":4.9,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Ultra-Compact Ka-Band Folded Phased-Array Transceiver Front-End With Bidirectional 20-dB Gain Control","authors":"Shiwei Wu;Dongfang Pan;Laifu Jin;Lin Cheng","doi":"10.1109/TCSII.2025.3586977","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3586977","url":null,"abstract":"This brief presents an ultra-compact Ka-band phased-array transceiver front-end implemented in 65-nm CMOS technology. The proposed design integrates a folded variable gain front-end and a passive variable gain phase shifter. The variable gain front-end achieves a merged receive and transmit channel layout design with stacked 8-shaped transformers. The passive variable gain phase shifter accomplishes bidirectional gain and phase control using the attenuable matching transformer with coupling lines. The transceiver achieves a 20 dB bidirectional gain range, 360° phase control, 0.5 dB gain steps, and 5.625° phase steps, meeting the stringent requirements of phased-array systems. Measurements demonstrate a maximum RMS phase error of 3.6° and an RMS gain error of 0.41 dB over the 32.3-37.7 GHz frequency range. The core occupies just 0.345 mm2, representing a more than 50% reduction in area compared to prior designs, making it highly suitable for large-scale phased-array applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1203-1207"},"PeriodicalIF":4.9,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Energy-Efficient Image Deblurring Accelerator With Quad-Base-Quad-Scale Quantized Format and Layer Normalization-Aware Optimization","authors":"Jinhoon Jo;Jueun Jung;Kyuho Jason Lee","doi":"10.1109/TCSII.2025.3586657","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3586657","url":null,"abstract":"This brief proposes a novel data-format-based image deblurring accelerator with layer normalization and UNet architecture optimization for mobile cameras. As the demand for photography in dynamic environments continues to grow and the limitations of physical stabilization are tightening, post-processing methods to restore sharp images have gained increasing attention, notably deblurring methods based on convolutional neural networks. However, their heavy computational cost hinders their integration into mobile computing platforms. The proposed accelerator enables energy-efficient acceleration of deblurring through the following three key features: 1) A Quad-base-Quad-scale Quantized format that maintains image quality with only 8-bit, reducing external memory access (EMA) by 33% and achieving 75.7% higher multiply-and-accumulation (MAC) energy efficiency compared to conventional 12-bit precision; 2) A Layer Normalization-Aware Optimization technique, enabling parallel normalization and fusion of affine transformation; 3) A dual-stationary systolic array architecture that selects the optimal dataflow for each UNet block based on processing element (PE) utilization. As a result, the proposed accelerator achieves 2.49 TOPS/W, which is <inline-formula> <tex-math>$2.23times $ </tex-math></inline-formula> higher than prior work, enabling energy-efficient deblurring for mobile applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1273-1277"},"PeriodicalIF":4.9,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead","authors":"Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao","doi":"10.1109/TCSII.2025.3585931","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585931","url":null,"abstract":"Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2-<inline-formula> <tex-math>$8 times $ </tex-math></inline-formula> dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3-<inline-formula> <tex-math>$6 times $ </tex-math></inline-formula> area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1263-1267"},"PeriodicalIF":4.9,"publicationDate":"2025-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Chaotic Nature of Integer Sequences From Primitive Linear Feedback Shift Registers","authors":"Hyojeong Choi;Gangsan Kim;Hong-Yeop Song;Hongjun Noh","doi":"10.1109/TCSII.2025.3585913","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585913","url":null,"abstract":"In this brief, we investigate the chaotic characteristics of the integer sequences generated by primitive linear feedback shift registers (LFSRs) by interpreting the internal states as integers. We prove that the discrete Lyapunov exponent (dLE) of the permutations induced by these sequences from an L-stage primitive LFSR approches to the range between <inline-formula> <tex-math>$ln (sqrt {3})$ </tex-math></inline-formula> and <inline-formula> <tex-math>$ln (2)$ </tex-math></inline-formula> as L increases indefinitely and hence the dynamic systems satisfy the definition of discrete chaos. Furthermore, the 0–1 test of the sequences yields statistics close to 1, supporting the conclusion that these sequences exhibit chaotic dynamics under both theoretical and empirical evaluations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1268-1272"},"PeriodicalIF":4.9,"publicationDate":"2025-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Carlos E. C. Souza;Davi Moreno;Matheus H. S. Sousa;Daniel P. B. Chaves;Cecilio Pimentel
{"title":"High-Throughput Pseudo-Random Number Generators Over Discrete Chaos","authors":"Carlos E. C. Souza;Davi Moreno;Matheus H. S. Sousa;Daniel P. B. Chaves;Cecilio Pimentel","doi":"10.1109/TCSII.2025.3585809","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585809","url":null,"abstract":"In this brief we propose two pseudo-random number generators (PRNGs) based on the discrete Arnold cat map (DACM) over the integer ring <inline-formula> <tex-math>$mathbb {Z}_{2^{m}}$ </tex-math></inline-formula>. The first PRNG employs or-exclusive (XOR) and bit permutations, discarding multiplication operations. The second PRNG proposes a methodology to double the number of bits extracted from each chaotic sample, increasing the bit generation rate. The statistical properties of the PRNGs are analyzed with the statistical test suites NIST and TestU01. The proposed PRNGs are implemented in the field-programmable gate array (FPGA) Xilinx Zynq-7000 and their hardware complexity is analyzed. We show that the maximum throughput obtained by one of the proposed PRNGs is 19 Gbps, which outperforms recent approaches.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1303-1307"},"PeriodicalIF":4.9,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}