IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第6页

A Dual-Parasitic-Aware Second-Harmonic Control Method for Continuous Class-J Power Amplifier 连续j类功率放大器双寄生感知二次谐波控制方法

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-04-22 DOI: 10.1109/TCSII.2026.3686453

Xiangran Ni;Xiangcong Zhai;Tianyu Li;Nuo Li;Zexuan Li;Ke Wei;Xinyu Liu;Weijun Luo

{"title":"A Dual-Parasitic-Aware Second-Harmonic Control Method for Continuous Class-J Power Amplifier","authors":"Xiangran Ni;Xiangcong Zhai;Tianyu Li;Nuo Li;Zexuan Li;Ke Wei;Xinyu Liu;Weijun Luo","doi":"10.1109/TCSII.2026.3686453","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3686453","url":null,"abstract":"This brief proposes a dual-parasitic-aware second-harmonic (<inline-formula> <tex-math>$2f_{0}$ </tex-math></inline-formula>) control method for continuous Class-J power amplifier (PA). To systematically investigate the effects of device parasitics, this work jointly considers the <inline-formula> <tex-math>$C_{mathrm {gs}}$ </tex-math></inline-formula>-induced current-shaping effect and the <inline-formula> <tex-math>$C_{mathrm {ds}}$ </tex-math></inline-formula>-induced impedance migration. Based on this analysis, the passive-realizable second-harmonic impedance region at the <inline-formula> <tex-math>$C_{mathrm {ds}}$ </tex-math></inline-formula> de-embedding plane is first derived while accounting for the effect of <inline-formula> <tex-math>$C_{mathrm {gs}}$ </tex-math></inline-formula>. The associated efficiency trend is also obtained, thereby establishing an accurate second-harmonic impedance control method for practical matching-network design. To validate the proposed method, a continuous Class-J GaN MMIC PA is designed and fabricated in a 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaN-on-Si process. The measured results show a drain efficiency of 59.2%–63.3% and a saturated output power of 36.9–37.6 dBm over 2.1–2.9 GHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"633-637"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 16-bit 1-MS/s SAR ADC With Redundant Split Capacitor Array and Parasitic Capacitance Calibration 具有冗余分裂电容阵列和寄生电容校准的16位1 ms /s SAR ADC

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-03-08 DOI: 10.1109/TCSII.2026.3691646

Hua Fan;Yongchang Duan;Qi Wei;Quanyuan Feng

引用次数: 0

PredLM: A Sparse Large Language Model Decoding Accelerator With Hardware-Efficient Zero-Activation Prediction PredLM：一种具有硬件效率零激活预测的稀疏大语言模型解码加速器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-03-05 DOI: 10.1109/TCSII.2026.3690531

Seunghyun Moon;Seowon Ji;Sangwoo Hong;Eunji Kwon

{"title":"PredLM: A Sparse Large Language Model Decoding Accelerator With Hardware-Efficient Zero-Activation Prediction","authors":"Seunghyun Moon;Seowon Ji;Sangwoo Hong;Eunji Kwon","doi":"10.1109/TCSII.2026.3690531","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3690531","url":null,"abstract":"This brief presents PredLM, a hardware-algorithm co-designed accelerator that aggressively reduces external memory access (EMA) to achieve real-time large language model (LLM) decoding. First, we introduce a simple but effective Key-Value (KV) cache management policy so that the size of KV cache is fixed regardless of the context length, significantly reducing the EMA for the KV cache. Second, we propose a dynamic zero-activation prediction scheme for feed-forward networks, allowing the hardware to dynamically skip unnecessary multiply-accumulate operations and weight fetches. To seamlessly support these predictive algorithms, PredLM features a homogeneous processing element array able to support the execution of both structural sparse and dense vector-matrix multiplications. Implemented in a 28-nm CMOS technology and evaluated with the OPT-1.3B and Llama2-7B models, PredLM achieves a time-per-output-token of 1.76 and 9.41 ms/token and an energy efficiency of 19.77 and 105.09 mJ/token with negligible perplexity degradation, delivering up to <inline-formula> <tex-math>$18.1times $ </tex-math></inline-formula> higher throughput and <inline-formula> <tex-math>$4.92times $ </tex-math></inline-formula> better energy efficiency compared to state-of-the-art LLM accelerators.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"653-657"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Adaptive Current Filter Fusion Strategy Based on Indirect Supervised Mechanism in Magnetic Suspension Balances 基于间接监督机制的磁悬浮天平自适应电流滤波器融合策略

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-04-14 DOI: 10.1109/TCSII.2026.3683955

Wei Pang;Qian Zeng;Yibo Wang;Fengqiu Xu;Xianze Xu

引用次数: 0

Hybrid-Polarity Logic Design and an Automated Algorithm for Glitch-Optimized Arithmetic Units 混合极性逻辑设计与故障优化算术单元的自动算法

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-03-05 DOI: 10.1109/TCSII.2026.3690140

Yuxuan Du;Zhangrui Qian;Tuo Li;Changhong Wang;Zhihao Yan;Kaize Zhou;Zhuo Chen;Jun Yin;Yan Lu;Weiwei Shan

{"title":"Hybrid-Polarity Logic Design and an Automated Algorithm for Glitch-Optimized Arithmetic Units","authors":"Yuxuan Du;Zhangrui Qian;Tuo Li;Changhong Wang;Zhihao Yan;Kaize Zhou;Zhuo Chen;Jun Yin;Yan Lu;Weiwei Shan","doi":"10.1109/TCSII.2026.3690140","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3690140","url":null,"abstract":"Artificial Intelligence (AI) processors and Digital Signal Processing (DSP) chips require high-efficiency arithmetic units, while glitch-induced power has become a major obstacle to further efficiency improvement. To address this, a hybrid-polarity logic design method and an automated algorithm are proposed for low-power and glitch-optimized arithmetic units. The output inverters of full/half adders are removed to eliminate redundant switching and alleviate path imbalance. The logical duality of these inverted cells is exploited to enable both conventional logic (positive polarity) and its inverted form (negative polarity) to co-exist and hybrid-propagate in arithmetic units. Then, a glitch-analysis-based inverter re-insertion strategy is used to ensure logic correctness with minimal power cost. The automated algorithm merges partial products from complex computations and explores hybrid-polarity circuit netlists with optimized power efficiency. Simulated in a 28 nm CMOS process, the proposed unsigned and signed multipliers achieve up to 54.40% and 55.92% power gains, 13.67% and 11.43% delay reduction, respectively, compared with their corresponding Design Compiler-generated baselines. When applied to dot-product modules in an AI accelerator, our design achieves up to 57.87% power reduction. The results verify the effectiveness of our hybrid-polarity design in mitigating glitches and enhancing efficiency for large-scale digital systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"648-652"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Infrared and Visible Multimodal Image Registration Based on Multi-Scale Stationary Velocity Field 基于多尺度静止速度场的红外与可见光多模态图像配准

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-04-28 DOI: 10.1109/TCSII.2026.3688506

Yi Liu;Dizheng Li;Yuwen Sun;Hong Sang;Yan Yan

{"title":"Infrared and Visible Multimodal Image Registration Based on Multi-Scale Stationary Velocity Field","authors":"Yi Liu;Dizheng Li;Yuwen Sun;Hong Sang;Yan Yan","doi":"10.1109/TCSII.2026.3688506","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3688506","url":null,"abstract":"Infrared and visible multimodal images play a critical role in autonomous driving and robot navigation. Image registration, as a prerequisite step, directly affects the performance of the subsequent high-level vision tasks. Due to the inherent differences in imaging mechanisms, the infrared images often exhibit complex non-rigid displacements relative to visible images, which makes the precise alignment challenging. To address this issue, a multimodal image registration method based on multi-scale stationary velocity fields is proposed. Firstly, a Coordinate Attention Fusion module (CAF) and a Stationary Velocity Field Deformation Prediction module (SVFDP) are designed to integrate multi-scale features and iteratively refine the deformation field for accurate registration. Secondly, a bidirectional registration framework is employed during training, leveraging the symmetric modality similarity loss to reduce imaging discrepancies between modalities. Finally, the comprehensive experiments on the RoadScene dataset show that the proposed method outperforms existing approaches in MSE, NCC, and PSNR, achieving 0.00212, 0.9786, and 27.33 in low-deformation scenarios, and maintaining superior performance under high deformation, which demonstrates the method’s superiority in cross-modal registration.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"663-667"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Compact Low-Distortion Sinusoidal Current Generator With 2-bit/128-Sample Optimum ΔΣ-Modulated LUT for Bio-Impedance Measurement 一个紧凑的低失真正弦电流发生器，具有2位/128个样本的最佳ΔΣ-Modulated LUT，用于生物阻抗测量

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-03-06 DOI: 10.1109/TCSII.2026.3690154

Aoran Sun;Jiedong Li;Can Dai;Jie Zhang;Hong Zhang

{"title":"A Compact Low-Distortion Sinusoidal Current Generator With 2-bit/128-Sample Optimum ΔΣ-Modulated LUT for Bio-Impedance Measurement","authors":"Aoran Sun;Jiedong Li;Can Dai;Jie Zhang;Hong Zhang","doi":"10.1109/TCSII.2026.3690154","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3690154","url":null,"abstract":"This brief presents a compact sinusoidal current generator (SCG) for bio-impedance (Bio-Z) measurement. To minimize overall circuit overhead and power consumption, the SCG is implemented with only a 2-bit/128-sample <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>-modulated look-up table (<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>M-LUT), a 2-bit resistive digital-to-analog converter (RDAC), a Gm-C filter and a transconductance (TC) stage followed by an output stage. The original 2-bit data stream is generated by an off-chip behavioral model for a 2-bit digital MASH 1-<inline-formula> <tex-math>$1~Delta Sigma $ </tex-math></inline-formula> modulator (<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>M) with a 12-bit/128-sample sinusoidal LUT as its input. Then, a hybrid particle-swarm-simulated-annealing (PSO-SA) algorithm is employed to select an optimum 2-bit/128-sample sequence that ensures the highest linearity for the on-chip LUT of the SCG. Fabricated in a 180-nm CMOS process, the chip occupies 0.154 mm2 and consumes <inline-formula> <tex-math>$112.9~mu $ </tex-math></inline-formula>W under 1.8 V for a typical output current of <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>App at 20 kHz, achieving a total harmonic distortion up to the <inline-formula> <tex-math>$20^{mathrm {th}}$ </tex-math></inline-formula> harmonic (THD20) of 0.0809% and a SFDR of 64.4 dB. Compared to prior similar types of designs, this work achieves area reduction up to 50%, making it suitable for wearable and implantable biomedical devices.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"613-617"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterization of a Realized Bidirectional Spiking Silicon Neuron in 65-nm Technology 实现的65纳米双向脉冲硅神经元的表征

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-04-13 DOI: 10.1109/TCSII.2026.3683297

Tamal Chowdhury;Pradip Mandal

{"title":"Characterization of a Realized Bidirectional Spiking Silicon Neuron in 65-nm Technology","authors":"Tamal Chowdhury;Pradip Mandal","doi":"10.1109/TCSII.2026.3683297","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3683297","url":null,"abstract":"Spiking Neural Networks pose their superiority over any existing Artificial Neural Networks in terms of power and their property of leaning more towards imitating biology while solving cognitive tasks. Conventional spiking neurons react to unipolar input signals only, which makes it inconvenient for bipolar signal processing. Recently, a modified variant of the Silicon Spiking Neuron, known as the Bidirectional Spiking Neuron (BSN), has been proposed to address the limitations of existing silicon neurons. A prototype of the BSN has been implemented in TSMC 65nm technology node. The design takes a silicon area of <inline-formula> <tex-math>$52~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times~ 72~mu $ </tex-math></inline-formula>m. The prototype has been extensively characterized, and the corresponding results are reported in this research. The BSN hardware is capable of sensing a wide range of bipolar input currents from–<inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>A to <inline-formula> <tex-math>$+ 8 mu $ </tex-math></inline-formula>A and producing spikes with a maximum frequency of 3 MHz. Additionally, an SNDR of 20 dB is feasible when using the design as a pulse density modulator. The bipolar signal sensing and spiking response pave the way to find the proposed design’s applications in signal processing and cognitive tasks.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"608-612"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-03-29 DOI: 10.1109/TCSII.2026.3694579

引用次数: 0

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-06-01 Epub Date: 2026-03-29 DOI: 10.1109/TCSII.2026.3694577

引用次数: 0