IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第6页

IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-01 DOI: 10.1109/TCSII.2025.3580983

引用次数: 0

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-01 DOI: 10.1109/TCSII.2025.3580985

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Parallel and Pipelined BRAM-Based Matrix Transposition for 6G 基于并行和流水线bram的6G矩阵转置

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-30 DOI: 10.1109/TCSII.2025.3584052

Jierui Chen;Chuang Yang;Xu Zhou;Mugen Peng

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Bumpless Transfer Control for Discrete Semi-Markov Switching Power System With Cyber Attack 网络攻击下离散半马尔可夫开关电源系统的无颠簸传输控制

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-24 DOI: 10.1109/TCSII.2025.3582648

Zhenhao Li;Wenhai Qi;Ju H. Park;Zheng-Guang Wu

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SPECTRUM1k – 75 μm Pixels Pitch IC With In-Pixel Histogramming for X-Ray Color Imaging SPECTRUM1k - 75 μm像素间距IC与像素内直方图用于x射线彩色成像

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3579856

P. Kmon;R. Kleczek;R. Szczygiel;G. Wegrzyn

{"title":"SPECTRUM1k – 75 μm Pixels Pitch IC With In-Pixel Histogramming for X-Ray Color Imaging","authors":"P. Kmon;R. Kleczek;R. Szczygiel;G. Wegrzyn","doi":"10.1109/TCSII.2025.3579856","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3579856","url":null,"abstract":"A new single photon-counting IC prototype called SPECTRUM1k with pixel matrix <inline-formula> <tex-math>$40times 24$ </tex-math></inline-formula> and pixel pitch <inline-formula> <tex-math>$75~mu $ </tex-math></inline-formula>m is developed by the Microelectronics Group of the AGH University of Krakow as a solution for X-ray color imaging. The chip, produced in CMOS 40nm technology, is made up of 960 individually configured pixels, each composed of an amplifier, an analog-to-digital converter, and <inline-formula> <tex-math>$64times 12$ </tex-math></inline-formula>-bit memory cells that allow one to perform in-pixel energy histogramming. Thanks to the proposed architecture working with the 200 MHz chip clock and 1 Gcps/mm2 multi energy photon intensities up-to about 23 ms exposition time is feasible (<inline-formula> <tex-math>$365~mu $ </tex-math></inline-formula>s exposition time whenever monoenergetic photons are used only). In-pixel offsets (<inline-formula> <tex-math>${=} 3.5$ </tex-math></inline-formula>%) and gain (<inline-formula> <tex-math>${=} 5.8$ </tex-math></inline-formula>%) spread, the amplifier performance (Equivalent Noise Charge <inline-formula> <tex-math>${=} 95$ </tex-math></inline-formula> e-RMS) and the ADC resolution (Effective Number of Bits <inline-formula> <tex-math>${=} 5.4$ </tex-math></inline-formula> b) allow to convert the incoming photons’ energy with FWHM <inline-formula> <tex-math>${=} 3.7$ </tex-math></inline-formula> ke @134.2 keV upon <inline-formula> <tex-math>$81~mu $ </tex-math></inline-formula>W or <inline-formula> <tex-math>$48~mu $ </tex-math></inline-formula>W per pixel power consumption. In this publication, we present a description of the ASIC’s architecture as well as characterization results. The threshold dispersions, gain spread as well as noise and energy measurement performance of the SPECTRUM1k are presented.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1003-1007"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11046196","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Small-Signal Modeling of an S-S Compensated IPT System Under Frequency Modulation 调频下S-S补偿IPT系统的小信号建模

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582261

Tianqi Li;Guangce Zheng;Chaoqun Qi;Haoyu Wang;Yu Liu;Minfan Fu

引用次数: 0

Single-Event Upset Monitor-Based Radiation-Hardened Latch for Multi-Node Upset 基于单事件镦粗监视器的多节点镦粗辐射硬化闩锁

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582493

Zhan Zheyu;Liu Hainan;Li Duoli;Ma Quangang;Zhao Wenxin;Yan Zhenzhen;Li Bo

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Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs 具有高偏置容限的体偏混合感测放大器，用于低压sram

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582549

Minglong Jia;Pengyuan Zhao;Linnan Li;Xiang Li;Zhi Li;Huidong Zhao;Shushan Qiao

引用次数: 0

UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination UniPRE：具有统一最大池预测和冗余消除的SNN-ANN加速器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582265

Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang

{"title":"UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination","authors":"Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang","doi":"10.1109/TCSII.2025.3582265","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3582265","url":null,"abstract":"The integration of Spiking Neural Networks (SNNs) and Artificial Neural Networks (ANNs) for specific tasks has attracted considerable interest due to their potential for high energy efficiency and accuracy. In SNN-ANN fused hardware, many works focus on neuron-level fusion of operators. Though some have explored optimizations at the dataflow level, they are restricted to only one kind of networks. This brief introduces a dataflow-level unified predicting method to eliminate redundant computations resulted from max-pooling operations for both SNN and ANN by exploiting Channel-wise Importance (CI). An accelerator with online sorting of Channel-wise Importance (CI) to support this optimization is also proposed, named as UniPRE. Results show that UniPRE reduces 44.77% and 31.85% overall computations with negligible accuracy loss for SNN and ANN using 37.5% channels for prediction. Implemented in the standard 28-nm CMOS technology, UniPRE can reach an energy efficiency of 19.32 TSOPS/W and 4.26 TOPS/W, with an area efficiency of 370.10 GSOPS/mm2 and 92.52 GOPS/mm2 for SNN and ANN paradigms of 8-bit weight precision, respectively. In layer-wise evaluation of real networks, up to <inline-formula> <tex-math>$1.79times $ </tex-math></inline-formula> energy reduction is achieved with 25% channels used for prediction.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1088-1092"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HIMAM: Hardware Implementation of Multiply-and-Max/Min Layers for Energy-Efficient DNN Inference 高效DNN推理的乘和最大/最小层的硬件实现

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-20 DOI: 10.1109/TCSII.2025.3581784

Fanny Spagnolo;Pasquale Corsonello;Stefania Perri

引用次数: 0