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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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A Low-Power Fully-Static Contention-Free Flip-Flop With Reduced Clock Load
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-14 DOI: 10.1109/TCSII.2024.3499347
Minkyu Ko;Bomin Joo;Bai-Sun Kong
{"title":"A Low-Power Fully-Static Contention-Free Flip-Flop With Reduced Clock Load","authors":"Minkyu Ko;Bomin Joo;Bai-Sun Kong","doi":"10.1109/TCSII.2024.3499347","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3499347","url":null,"abstract":"This brief presents a low-power redundant transition- and contention-free flip-flop with fewer clock transistors. Called reduced clock-load flip-flop (RCLFF), the proposed flip-flop minimizes the clock load by merging clock transistors to reduce the clock power consumption regardless of input switching activity. It also provides completely redundant transition-free operation, further reducing the power consumption. Reliable operation with no floating node and contention can enable further power saving by letting the flip-flop in the near-threshold voltage (NTV) region. Performance evaluation in a 28-nm CMOS process indicates that RCLFF achieves up to 60.9% power reduction compared to conventional flip-flops at 0.1 switching activity. By reducing power consumption with moderate DQ latency, the power-delay product (PDP) of RCLFF is improved by up to 64.5%. The Monte-Carlo simulation result reveals that RCLFF can operate reliably down to a 0.3 V supply voltage regardless of process, voltage, and temperature (PVT) variations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"419-423"},"PeriodicalIF":4.0,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Resilient Frequency Estimation for Renewable Power Generation Against Phasor Measurement Unit and Communication Link Failures 针对相量测量单元和通信链路故障的可再生能源发电弹性频率估计
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-11 DOI: 10.1109/TCSII.2024.3496192
Zhijian Hu;Rong Su;Kai Zhang;Ruiping Wang;Renjie Ma
{"title":"Resilient Frequency Estimation for Renewable Power Generation Against Phasor Measurement Unit and Communication Link Failures","authors":"Zhijian Hu;Rong Su;Kai Zhang;Ruiping Wang;Renjie Ma","doi":"10.1109/TCSII.2024.3496192","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3496192","url":null,"abstract":"The increasing penetration of distributed energy resources aggravates the frequency fluctuation of modern power generation systems. In this context, the brief endeavors to propose a frequency estimation method. By simultaneously considering the phasor measurement unit (PMU) and communication link failures and modeling them as independent Bernoulli process, we formulate some linear matrix inequalities-based sufficient conditions, from which the resilient estimation gains capable to ensure the mean-square stability and robust performance of the estimation error system can be automatically selected. Validation results illustrate the superiority of the proposed method over existing ones under different probabilities of PMU and communication link failures.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"233-237"},"PeriodicalIF":4.0,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
H∞Optimal Load Frequency Control of Power System: A Novel Model-Free Approach 电力系统H∞最优负荷频率控制：一种新的无模型方法
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-11 DOI: 10.1109/TCSII.2024.3495679
Shunwei Hu;Yanhong Luo;Xiangpeng Xie;Huaguang Zhang
{"title":"H∞Optimal Load Frequency Control of Power System: A Novel Model-Free Approach","authors":"Shunwei Hu;Yanhong Luo;Xiangpeng Xie;Huaguang Zhang","doi":"10.1109/TCSII.2024.3495679","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3495679","url":null,"abstract":"This brief addresses the model-free output feedback (OPFB) stability problem in load frequency control (LFC) of power system and proposes an \u0000<inline-formula> <tex-math>$H_{infty } $ </tex-math></inline-formula>\u0000 optimal control scheme considering two-player zero-sum game. Firstly, a novel policy iteration algorithm is developed to determine the optimal control gain. The convergence of this algorithm can be established using Fréchet derivatives. Secondly, a model-free adaptive dynamic programming (ADP) algorithm is introduced, which leverages measured data to learn the optimal gain without relying on model parameters. Finally, simulation results confirm the feasibility of the proposed algorithm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"228-232"},"PeriodicalIF":4.0,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic Self-Triggered Adaptive Control for Voltage Regulation of DC Microgrids 直流微电网电压调节的动态自触发自适应控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-07 DOI: 10.1109/TCSII.2024.3493244
Fan Liu;Hanguang Su;Huaguang Zhang;Ruizhuo Song;Jiawei Wang
{"title":"Dynamic Self-Triggered Adaptive Control for Voltage Regulation of DC Microgrids","authors":"Fan Liu;Hanguang Su;Huaguang Zhang;Ruizhuo Song;Jiawei Wang","doi":"10.1109/TCSII.2024.3493244","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3493244","url":null,"abstract":"In this brief, a novel online near-optimal control scheme is investigated for the voltage tracking control problem of direct current (DC) microgrids under the dynamic self-triggered (DST) mechanism. First, the DC microgrid is modeled as an affine coupled system. The nonzero-sum game issue of the multi-input system is taken into account, where each distributed generator (DG) strives to minimize the individual performance index function and ensure the stability of the whole system. Subsequently, the value function with the non-quadratic utility function is established to seek the optimal constrained control pair. The critic neural network (NN) is devised to approximate the optimal value function. By virtue of experience replay technique, the persistent excitation condition is no more needed. What is more, dynamic event-triggered (DET) control can significantly reduce the waste of computation and communication resources by avoiding the redundant triggers. However, the continuous detection of the DET condition is dependent on dedicated hardware. To overcome the difficulties in hardware realization of DET control, a novel DST method with the dead-zone operation is proposed, in which design the next triggering instant is actively calculated by current data. Besides, the stability of the system and the minimum trigger interval are guaranteed. Finally, a simulation example validates the effectiveness of the algorithm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"223-227"},"PeriodicalIF":4.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Instantaneous Frequency Estimation in Unbalanced Systems Using Affine Differential Geometry 基于仿射微分几何的非平衡系统瞬时频率估计
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-07 DOI: 10.1109/TCSII.2024.3494032
Ali Alshawabkeh;Georgios Tzounas;Ángel Molina-García;Federico Milano
{"title":"Instantaneous Frequency Estimation in Unbalanced Systems Using Affine Differential Geometry","authors":"Ali Alshawabkeh;Georgios Tzounas;Ángel Molina-García;Federico Milano","doi":"10.1109/TCSII.2024.3494032","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3494032","url":null,"abstract":"This brief discusses the relationships between electrical and affine differential geometry quantities, establishing a link between frequency and time derivatives of voltage, through the utilization of affine geometric invariants. Based on this link, a new instantaneous frequency estimation formula is proposed, which is particularly suited for unbalanced and single-phase systems. Several examples as well as measurements based on two real-world events illustrate the findings of this brief.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"343-347"},"PeriodicalIF":4.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 120 GHz gm-boosting Low-Noise Amplifier in 40-nm CMOS 一种采用40nm CMOS的120 GHz提升毫米波低噪声放大器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-06 DOI: 10.1109/TCSII.2024.3493038
In Cheol Yoo;Dong Ouk Cho;Dong-Woo Kang;Bontae Koo;Chul Woo Byeon
{"title":"A 120 GHz gm-boosting Low-Noise Amplifier in 40-nm CMOS","authors":"In Cheol Yoo;Dong Ouk Cho;Dong-Woo Kang;Bontae Koo;Chul Woo Byeon","doi":"10.1109/TCSII.2024.3493038","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3493038","url":null,"abstract":"This brief presents the design of a 120 GHz \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000-boosting low-noise amplifier (LNA) in 40-nm CMOS. The proposed LNA consists of a single-stage differential \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000-boosting common-gate (CG) amplifier and a four-stage differential capacitance-neutralized common-source amplifier. A triple-coupled transformer-based \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000-booting technique in the CG stage enhances gain and noise figure (NF) performances. Implemented in 40 nm CMOS, the proposed LNA achieves a measured power gain of 23.8 dB at 123 GHz with a 3-dB bandwidth of 10 GHz. The lowest NF is 5.0 dB at 123 GHz and the NF is below 6.5 dB from 114 to 128 GHz. The LNA consumes 26 mW from a 1-V supply, with a core chip area of 0.25 mm \u0000<inline-formula> <tex-math>$times 0$ </tex-math></inline-formula>\u0000.70 mm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"153-157"},"PeriodicalIF":4.0,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Time-Elapsed-Reliant Observer-Based Control of Semi-Markov Jump Linear Systems With Bilaterally Bounded Sojourn Time 驻留时间有界的半马尔可夫跳变线性系统的时间依赖观测器控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-04 DOI: 10.1109/TCSII.2024.3491032
Yongxiao Tian;Zepeng Ning;Huaicheng Yan;Yan Peng
{"title":"Time-Elapsed-Reliant Observer-Based Control of Semi-Markov Jump Linear Systems With Bilaterally Bounded Sojourn Time","authors":"Yongxiao Tian;Zepeng Ning;Huaicheng Yan;Yan Peng","doi":"10.1109/TCSII.2024.3491032","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3491032","url":null,"abstract":"This brief focuses on the observer-based output-feedback (OBOF) control of discrete-time semi-Markov jump linear systems (SMJLSs) with bilateral bounds of sojourn time. To lessen the conservatism in OBOF controller design, we develop a decoupling technique that facilitates the simultaneous design of the time-elapsed-reliant observer and controller, which also alleviates the computational burden. Following this approach, mean-square stability analysis and OBOF control synthesis are implemented for SMJLSs by resorting to semi-Markov kernel within an equivalent closed-loop augmented system. The theoretical results are validated through an electromagnetic oscillation circuit to elucidate the efficacy and practical utility of the proposed control methodology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"218-222"},"PeriodicalIF":4.0,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR 片上交流耦合非对称输出级激光雷达
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-04 DOI: 10.1109/TCSII.2024.3489640
Yuye Yang;Hao Feng;Zhenyu Yin;Shuaizhe Ma;Jia Li;Xinyin Shan;Yifei Xia;Ruixuan Yang;Bing Zhang;Li Geng;Dan Li
{"title":"An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR","authors":"Yuye Yang;Hao Feng;Zhenyu Yin;Shuaizhe Ma;Jia Li;Xinyin Shan;Yifei Xia;Ruixuan Yang;Bing Zhang;Li Geng;Dan Li","doi":"10.1109/TCSII.2024.3489640","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3489640","url":null,"abstract":"In this brief, an on-chip AC coupled analog front-end circuit with asymmetric output stage is proposed for a pulsed direct time-of-flight LiDAR receiver. The AFE employs a novel on-chip AC coupled scheme for APD cathode bias voltage tuning in a cost-effective manner. A reverse current cancellation circuit helps the circuit recover rapidly under large input current. A transimpedance amplifier is designed for low noise which is desirable to process weak signals. An asymmetric output stage doubles the output swing under the same bias current compared to conventional current mode logic topology. This prototype chip is fabricated in a standard 180 nm CMOS process and the measurement results shows bandwidth, gain, input-referred noise current of 151 MHz, 102 dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, and 3.51 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000 Hz, respectively. The maximum differential output swing reaches \u0000<inline-formula> <tex-math>$1.8~rm V_{textrm {pp,diff}}$ </tex-math></inline-formula>\u0000 based on both electrical and optical measurement setup.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"148-152"},"PeriodicalIF":4.0,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference MorphBungee-Lite：基于分层事件批处理学习/推理的平衡跨核工作负载的边缘神经形态架构
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-30 DOI: 10.1109/TCSII.2024.3488526
Zhengqing Zhong;Haibing Wang;Mingju Chen;Yingcheng Lin;Min Tian;Tengxiao Wang;Liyuan Liu;Cong Shi
{"title":"MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference","authors":"Zhengqing Zhong;Haibing Wang;Mingju Chen;Yingcheng Lin;Min Tian;Tengxiao Wang;Liyuan Liu;Cong Shi","doi":"10.1109/TCSII.2024.3488526","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3488526","url":null,"abstract":"Neuromorphic processors are promising candidates for energy-constrained intelligent systems, as they emulate cortical computations via spatiotemporally sparse binary spikes. However, achieving high-accuracy, high-throughput and cost-efficient neuromorphic processing remains challenging. To fully utilize hardware resources for performance improvement, we propose a multi-core neuromorphic architecture characteristic of a uniform neuron-core mapping scheme and a layer-wise event-batch-based parallel processing paradigm. These techniques ensure highly balanced cross-core workloads regardless of actual mapped neural network topologies as well as unpredictable input and internally generated spike counts varying from sample to sample. An FPGA prototype of our neuromorphic processor was implemented. It exhibited comparably high on-chip learning accuracies on various visual and non-visual benchmarks, high learning/inference frame rates (low processing latencies), with a moderate amount of logic and memory resource consumptions.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"293-297"},"PeriodicalIF":4.0,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3477193
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3477193","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477193","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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