{"title":"ZRHDC:一个轻量级的HDC架构,零ROM开销","authors":"Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao","doi":"10.1109/TCSII.2025.3585931","DOIUrl":null,"url":null,"abstract":"Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2-<inline-formula> <tex-math>$8 \\times $ </tex-math></inline-formula> dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3-<inline-formula> <tex-math>$6 \\times $ </tex-math></inline-formula> area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1263-1267"},"PeriodicalIF":4.9000,"publicationDate":"2025-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead\",\"authors\":\"Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao\",\"doi\":\"10.1109/TCSII.2025.3585931\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2-<inline-formula> <tex-math>$8 \\\\times $ </tex-math></inline-formula> dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3-<inline-formula> <tex-math>$6 \\\\times $ </tex-math></inline-formula> area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 9\",\"pages\":\"1263-1267\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11071950/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11071950/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead
Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2-$8 \times $ dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3-$6 \times $ area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.