IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

Design and Analysis of a Ka-Band CMOS Power Amplifier Employing a Pseudo-Cascode Output Stage With Dual Multi-Finger Configuration 双多指伪级联输出ka波段CMOS功率放大器的设计与分析

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-16 DOI: 10.1109/TCSII.2026.3704292

Yo-Sheng Lin;Chung-Ta Huang;Yu-Rong He

{"title":"Design and Analysis of a Ka-Band CMOS Power Amplifier Employing a Pseudo-Cascode Output Stage With Dual Multi-Finger Configuration","authors":"Yo-Sheng Lin;Chung-Ta Huang;Yu-Rong He","doi":"10.1109/TCSII.2026.3704292","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3704292","url":null,"abstract":"This paper presents a Ka-band CMOS power amplifier (PA). The proposed PA comprises an input transformer, a common-source (CS) input stage, a pseudo-cascode output stage, and an output transformer. Neutralization capacitors are used in the input and output stages to enhance gain and power-added efficiency (PAE) while ensuring unconditional stability. Coupled-line feedback is incorporated in the input stage to further improve gain and PAE. In addition, the CS transistors in the output stage adopt a dual multi-finger configuration with optimized gate dimensions of <inline-formula> <tex-math>$4.3times 24 ~mu $ </tex-math></inline-formula>m and <inline-formula> <tex-math>$4.3times 26 ~mu $ </tex-math></inline-formula>m connected in parallel. This design increases transconductance and gain, thereby improving PAE and output power (P<inline-formula> <tex-math>${}_{mathrm {out}}$ </tex-math></inline-formula>). To further enhance Pout by 1 dBm and PAE by 4%, while simplifying the biasing scheme, an input-power-dependent dynamic self-biasing technique is applied to the common-gate (CG) transistors in the output stage, referred to as a pseudo-cascode topology. This approach eliminates the need for external gate biasing. The PA occupies a compact area of 0.109 mm2 and attains a gain of <inline-formula> <tex-math>$19.6pm ~1.5$ </tex-math></inline-formula> dB over 26–36.8 GHz, corresponding to a 3 dB bandwidth of 10.6 GHz. At 30 GHz, the PA achieves a Pout of 20.2 dBm, an output 1 dB compression point (OP<inline-formula> <tex-math>${}_{mathrm {1dB}}$ </tex-math></inline-formula>) of 19.4 dBm, and a peak PAE of 35%, resulting in an excellent figure of merit (FoM) of 3.07 W/mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"788-792"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA Deployment of Extremely Quantized Models for Time-to-Lane-Change Prediction 时间到车道变化预测的极量化模型的FPGA部署

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-18 DOI: 10.1109/TCSII.2026.3705103

Ammar Saad;Riccardo Berta;Matteo Fresta;Luca Lazzaroni;Alessandro Pighetti;Ossama Srour;Fabio Tango;Francesco Bellotti

{"title":"FPGA Deployment of Extremely Quantized Models for Time-to-Lane-Change Prediction","authors":"Ammar Saad;Riccardo Berta;Matteo Fresta;Luca Lazzaroni;Alessandro Pighetti;Ossama Srour;Fabio Tango;Francesco Bellotti","doi":"10.1109/TCSII.2026.3705103","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3705103","url":null,"abstract":"Despite the rapid evolution of automated driving, public information about deployability in production vehicles remains limited. We present a Field Programmable Gate Array (FPGA) prototyping study of an AI module for estimating time-to-lane-change (TTLC), focusing on key deployment metrics such as latency, memory footprint, and power/energy consumption. FPGAs enable custom acceleration while providing flexibility to explore multiple design trade-offs. Particularly, we investigate different quantization strategies, given their potential to substantially reduce model size while preserving predictive performance. This brief makes four main contributions that advance the state-of-the-art through an FPGA-based implementation. We present a hardware-aware FPGA design methodology that balances memory efficiency and task accuracy. We provide a comprehensive analysis of the trade-offs achievable by varying AI model type, operating frequency, and quantization precision. We find a set of Pareto-optimal solutions along the power-latency axes, identifying a clear elbow at a co-processor frequency of 25/50 MHz depending on model and quantization type. We implement a Transformer architecture that preserves state-of-the-art TTLC predictive performance while meeting the 10 Hz real-time constraint and reducing total energy consumption by 83% compared to a high-end microcontroller.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"888-892"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11570930","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design Strategy for Novel Structures of Lumped LC Filters Based on 3D Stacking Processes 基于三维叠加工艺的集总LC滤波器新结构设计策略

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-03 DOI: 10.1109/TCSII.2026.3709867

Xinqing Lei;Gang Dong;Changle Zhi;Ziyu Zhou;Xiaoxian Liu;Zhangming Zhu

{"title":"Design Strategy for Novel Structures of Lumped LC Filters Based on 3D Stacking Processes","authors":"Xinqing Lei;Gang Dong;Changle Zhi;Ziyu Zhou;Xiaoxian Liu;Zhangming Zhu","doi":"10.1109/TCSII.2026.3709867","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3709867","url":null,"abstract":"This brief proposes a design method to achieve miniaturization of lumped LC filters. Inductors and capacitors, which are implemented by through silicon vias (TSVs), are arranged across different silicon layers and connected by redistribution layers (RDLs) and micro-bumps. Initial dimensions of the 3D capacitors and inductors required for filters are determined using analytical formulas, with the feasibility verified through EM simulations. Furthermore, parasitic effects are comprehensively analyzed to improve the accuracy of the ideal circuit model in reflecting the transmission characteristics of the practical structure. On the basis of this approach, a design case of a third-order bandpass filter (BPF) is constructed. By fully utilizing the vertical stacking space, this design not only enables footprint reduction of only <inline-formula> <tex-math>$0.34times 0.26$ </tex-math></inline-formula> mm2, but also reuses redundant TSVs and CTSVs introduced by process requirements. The final implemented BPF exhibits a center frequency of 5.45 GHz, achieves an in-band return loss better than -20 dB with an insertion loss of -1.15 dB in the passband of 4.6-6.64 GHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"848-852"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-31 DOI: 10.1109/TCSII.2026.3714262

引用次数: 0

Dynamic Self-Triggered Driven Adaptive Neural Network Command Filtered Backstepping Discrete-Time Control for PMSMs 永磁同步电机动态自触发驱动自适应神经网络命令滤波反步离散时间控制

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-02 DOI: 10.1109/TCSII.2026.3709293

Ziru Zhang;Jiapeng Liu;Xinkai Chen;Jinpeng Yu

{"title":"Dynamic Self-Triggered Driven Adaptive Neural Network Command Filtered Backstepping Discrete-Time Control for PMSMs","authors":"Ziru Zhang;Jiapeng Liu;Xinkai Chen;Jinpeng Yu","doi":"10.1109/TCSII.2026.3709293","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3709293","url":null,"abstract":"This brief proposes an adaptive neural network self-triggered discrete-time control strategy for the permanent magnet synchronous motor (PMSM) speed regulation system. A novel self-triggered mechanism is designed to determine the update instants of neural network weights and control signals. Different from traditional event-triggered intelligent control methods, the proposed algorithm only depends on the system states at the current triggered instant and does not require continuous monitoring of system states, thereby further reducing computation burden of the intelligent control system. Then, the command filtered technique is utilized to address the “explosion of complexity” problem in backstepping design. Finally, the stability of the closed-loop system is analyzed for the two cases of self-triggered instants and instants in self-triggered intervals, respectively. It is rigorously proved that all signals in the closed-loop system are bounded at any instant. Experimental results demonstrate that the proposed method can effectively reduce the number of triggered instants and alleviate the computational burden of the intelligent control system, while achieving a favorable tradeoff between control performance and resource utilization efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"858-862"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power Semi-Digital Spectrum-Balancing Adaptive Equalizer for 8-Gb/s Serial Links 用于8gb /s串行链路的低功耗半数字频谱平衡自适应均衡器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-09 DOI: 10.1109/TCSII.2026.3701424

Young-Ryul Yun;Seung-Jin Yeo;Jae-Hong Ko;Muhammad Abrar Akram;In-Chul Hwang

{"title":"A Low-Power Semi-Digital Spectrum-Balancing Adaptive Equalizer for 8-Gb/s Serial Links","authors":"Young-Ryul Yun;Seung-Jin Yeo;Jae-Hong Ko;Muhammad Abrar Akram;In-Chul Hwang","doi":"10.1109/TCSII.2026.3701424","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3701424","url":null,"abstract":"This brief presents a high-speed semi-digital spectrum balancing adaptive equalizer (SDSB-AEQ) integrated in a receiver (RX) for high-speed display driver ICs (DDIs). The proposed SDSB-AEQ eliminates the need for passive analog filters as compared to typical spectrum balancing adaptive equalizers (SB-AEQ) by implementing an analog–digital (hybrid) processing architecture and significantly shortens the chip area and equalizer (EQ) settling time. The SDSB-AEQ digital block is RTL-synthesized and includes comparators, an FSM, and accumulators to process spectral information from the analog domain. The proposed SDSB-AEQ was designed and fabricated in a 65 nm CMOS process with an active area of <inline-formula> <tex-math>$0.0769~m m^{2}$ </tex-math></inline-formula>. Measurement results show that the proposed SDSB-AEQ reduces peak-to-peak jitter from 53.133 ps to 20.836 ps compared to a non-optimized fixed baseline EQ condition, corresponding to an improvement of 0.26 UI. The proposed SDSB-AEQ consumes 9 mW within a total RX power of 33 mW, and its performance is verified by measurements.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"778-782"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved Neural Network Modeling of Circuit Elements With Biparametric Wave Digital Filters 基于双参数波数字滤波器的电路元件改进神经网络建模

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-08 DOI: 10.1109/TCSII.2026.3701133

Giacomo Longo;Riccardo Giampiccolo;Alessandro Ilic Mezza;Augusto Sarti;Alberto Bernardini

{"title":"Improved Neural Network Modeling of Circuit Elements With Biparametric Wave Digital Filters","authors":"Giacomo Longo;Riccardo Giampiccolo;Alessandro Ilic Mezza;Augusto Sarti;Alberto Bernardini","doi":"10.1109/TCSII.2026.3701133","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3701133","url":null,"abstract":"Recent studies have demonstrated the effectiveness of combining Wave Digital Filters (WDFs) with Neural Networks (NNs) for modeling nonlinear circuits. In this context, an NN is used to approximate the scattering equations of nonlinear elements and is connected to a WDF-based linear network representing the rest of the circuit. However, the adaptation condition required to obtain a fully explicit structure can lead to unfavorable parameter values, which can heavily distort the representation of the nonlinear characteristic in the wave domain. This issue becomes particularly critical when modeling hysteresis (or other nonlinearities exhibiting memory), as the transformed characteristic may hinder accurate learning by collapsing the different branches of the hysteresis loops onto each other. In this work, we propose the use of Biparametric Wave Digital Filters (BWDFs) to overcome these limitations. By exploiting the additional degrees of freedom offered by the biparametric formulation, a more suitable wave domain representation of the nonlinearity can be obtained, thereby easing the NN modeling task. Furthermore, we show that this approach can be integrated into existing WDF structures with minimal modifications, making its adoption straightforward even in the case of complex circuits.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"873-877"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11554089","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TDComp: Energy Efficient Time Domain Bitmap Compression TDComp：节能时域位图压缩

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-22 DOI: 10.1109/TCSII.2026.3705196

Bingxi Pei;Yibai He;Xiaoyang Wang;Yande Jiang;Jian Fang;Huiquan Wang;Guangda Zhang;Xia Zhao;Weifeng He

{"title":"TDComp: Energy Efficient Time Domain Bitmap Compression","authors":"Bingxi Pei;Yibai He;Xiaoyang Wang;Yande Jiang;Jian Fang;Huiquan Wang;Guangda Zhang;Xia Zhao;Weifeng He","doi":"10.1109/TCSII.2026.3705196","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3705196","url":null,"abstract":"Bitmap compression is an essential technique to reduce the memory footprint during on-device training by exploiting activation sparsity. This brief presents a novel time-domain bitmap compression implementation, converts activation compression into activation serialization and pulse compression, eliminating the need for area and power consuming crossbar network or inverse butterfly network commonly used in parallel approaches. First, it utilizes pulses generated by a cascaded buffer delay chain to convert parallel activation into a serialized stream. Then, a pulse compression circuit is introduced to squeeze pulses corresponding to invalid activation and generate time-alignment sampling clock for the serialized stream. Finally, compressed activation is stored in proposed single-phase rising-clocked registers which explore the characteristics of activation and clock to reduce power consumption. Simulated in 28nm CMOS technology, the proposed method achieves a 68% reduction in circuit area for 128 8-bit activation compression compared to existing parallel approaches, and reduces energy per operation by 31.3%, 43.5%, 46.6%, and 24.3% for activation lengths of 16, 32, 64, and 128, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"868-872"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SACIM: A Synapse-Inspired Asynchronous CIM With Discharging Feedback, Dynamic Delay, and Parallelism Extension for CNN Inference SACIM：基于放电反馈、动态延迟和CNN推理并行扩展的突触启发异步CIM

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-03-14 DOI: 10.1109/TCSII.2026.3693271

Tingran Chen;XiaoYa Wang;Yuxuan Ran;Kaiying Yang;Yi Zhao;Kexun Cheng;Chen Li;He Zhang;Xueyan Wang;Biao Pan

引用次数: 0

Flexible Parallel Radix-4 MDC NTT for FHE 用于FHE的柔性并行Radix-4 MDC NTT

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-08 DOI: 10.1109/TCSII.2026.3700928

Tobias Stelzer;Patrick Karl;Andreas Zankl

{"title":"Flexible Parallel Radix-4 MDC NTT for FHE","authors":"Tobias Stelzer;Patrick Karl;Andreas Zankl","doi":"10.1109/TCSII.2026.3700928","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3700928","url":null,"abstract":"Fully Homomorphic Encryption (FHE) is a promising technology that allows calculations to be performed on encrypted data. However, its widespread adoption is hindered by high computational requirements. In this brief, we present a design-time flexible FPGA accelerator that aims to speed up the Number Theoretic Transform (NTT), the most crucial bottleneck in FHE schemes. Our accelerator is throughput-oriented and implements a Multipath Delay Commutator (MDC) approach. While previous works focus on radix-2 implementations, we implement a parallel radix-4 NTT architecture. We exploit constants within radix-4 structures and reduce DSP slice utilization by more than 25%. We achieve that by using a recent constant modular multiplication technique by Bertels et al. and leverage special properties of goldilock primes. The polynomial degree, modulus and number of parallel compute cores are design-time configurable. Due to its configurability, our design allows for the evaluation of different area and speed trade-offs and targets various parameter sets and requirements. To demonstrate the applicability of our approach, we conduct a case study and evaluate different configurations and parameters that are applicable to FHE schemes such as CGGI or CKKS. All implementations are done on the AMD Alveo U55C. Compared to our reference software implementation based on OpenFHE, we achieve a speed-up of up to <inline-formula> <tex-math>$23.75times $ </tex-math></inline-formula>. Compared to related works, with the same bandwidth requirements, we achieve up to <inline-formula> <tex-math>$3.81times $ </tex-math></inline-formula> lower ATP and up to <inline-formula> <tex-math>$4.33times $ </tex-math></inline-formula> higher TPS.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"863-867"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11553462","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0