IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

A 16-to-24.9 GHz Dual-Core Dual-Mode Noise-Circulating VCO Using Single-Phase Switch With FOMT of 209.0 dBc/Hz 采用单相开关的16 ~ 24.9 GHz双核双模噪声循环压控振荡器，fomo为209.0 dBc/Hz

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-02 DOI: 10.1109/TCSII.2026.3669392

Wanqing Wu;Xinyi Zhang;Ning Zhang;Ruiyong Xiang;Haigang Feng;Zhihua Wang

{"title":"A 16-to-24.9 GHz Dual-Core Dual-Mode Noise-Circulating VCO Using Single-Phase Switch With FOMT of 209.0 dBc/Hz","authors":"Wanqing Wu;Xinyi Zhang;Ning Zhang;Ruiyong Xiang;Haigang Feng;Zhihua Wang","doi":"10.1109/TCSII.2026.3669392","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3669392","url":null,"abstract":"This brief presents a dual-core dual-mode noise-circulating voltage-controlled oscillator (VCO) with a wide frequency tuning range (FTR) and low phase noise (PN) for K-band applications. Specifically, the VCO employs an optimized capacitively coupled noise-circulating structure to operate in the K-band while suppressing the thermal noise contribution of the transistors. A low-noise dual-mode inductor is proposed. By utilizing a single-phase switch network, it achieves a wide FTR without degrading the phase noise performance, eliminating the detrimental effects of mode-switching. Fabricated in a 65-nm CMOS process, the VCO occupies an active core area of 0.096 mm2. When operating at 16.32 GHz, the VCO achieves -148.4 dBc/Hz at 10 MHz offset frequency after the frequency is divided by three. While the power consumption is 4.9 mW from a 0.9 V supply, the resulting figure-of-merit (FOM) is 196.2 dBc/Hz. With a FTR from 16 GHz to 24.9 GHz (43.5%), the VCO achieves a FOM with tuning range (FOM<inline-formula> <tex-math>${}_{mathrm {T}}$ </tex-math></inline-formula>) of 209.0 dBc/Hz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"508-512"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 9-b 3–7.5-GHz 2.53-LSB-INL High-Linearity Phase Interpolator With CMOS-Signal-Targeted Calibration in 65-nm for High-Speed Data Links 用于高速数据链路的9-b 3- 7.5 ghz 2.53-LSB-INL高线性相位插补器，65纳米cmos信号定向校准

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-30 DOI: 10.1109/TCSII.2026.3678518

Zexin Su;Junyan Zhu;Chang Liu;Tao Hu;Yao Liu;Jixin Chen;Franco Maloberti;Bo Li

{"title":"A 9-b 3–7.5-GHz 2.53-LSB-INL High-Linearity Phase Interpolator With CMOS-Signal-Targeted Calibration in 65-nm for High-Speed Data Links","authors":"Zexin Su;Junyan Zhu;Chang Liu;Tao Hu;Yao Liu;Jixin Chen;Franco Maloberti;Bo Li","doi":"10.1109/TCSII.2026.3678518","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3678518","url":null,"abstract":"In this work, a high-linearity 8-phase CMOS-targeted-calibration phase interpolator (PI) is proposed. In classical current-mode logic (CML) PIs, improvement efforts primarily focus on correcting the CML signal phase error, while neglecting a significant transfer phase error that occurs when converting the CML signal to the CMOS signal, resulting from the amplitude differences of CML phases and the threshold variation of the transfer circuit. To address this problem, a CMOS-signal-targeted calibration technique is proposed, which considers both error sources: the CML inherent phase error and the transfer error from CML to CMOS. The phase error will be extracted directly from the final CMOS signal, and the calibration will be implemented according to this total phase error. In the proposed calibration scheme, the specific CMOS phases (22.5° phase group) are adopted as phase references, which have identical CML amplitudes before CMOS to avoid the transfer error; and other CMOS phases will be calibrated based on the references. Fabricated in a 65nm CMOS process, the chip achieves an integral non-linearity (INL) of less than 2.53 LSB and a differential non-linearity (DNL) of less than 0.77 LSB with 9 bits resolution across a frequency range of 3 to 7.5 GHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"523-527"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Optimized Dead-Time for Soft-Switching in CCM of Current-Fed Interleaved Boost Converter 电流馈电交错升压变换器CCM软开关死区优化

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-26 DOI: 10.1109/TCSII.2026.3677874

Dinh Phuc Nguyen;Weize Xu;Chun-Jen Yao;Huang-Jen Chiu

引用次数: 0

A 0.95-ppm/°C Voltage Reference With Second-Order Core-Injection Sub-Ranging Compensation 一个0.95 ppm/°C电压基准与二阶堆芯注入子量程补偿

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-04-06 DOI: 10.1109/TCSII.2026.3681102

Wenzhao Lv;Pengxu Ren;Dan Ye;Chao Jiang;Zhuojun Chen

引用次数: 0

A 2-to-18 GHz Power Amplifier With 31-dB Gain and ±0.5 dB In-Band Ripple Using Segmented Matching in 0.18-μm SiGe BiCMOS 基于0.18 μm SiGe BiCMOS的31 dB增益和±0.5 dB带内纹波的2 ~ 18 GHz功率放大器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-06 DOI: 10.1109/TCSII.2026.3671329

Jianbing Liu;Fanyi Meng

{"title":"A 2-to-18 GHz Power Amplifier With 31-dB Gain and ±0.5 dB In-Band Ripple Using Segmented Matching in 0.18-μm SiGe BiCMOS","authors":"Jianbing Liu;Fanyi Meng","doi":"10.1109/TCSII.2026.3671329","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3671329","url":null,"abstract":"This brief proposes an ultra-wideband power amplifier (PA) covering the <italic>S-C-X-Ku <bold>bands, realized in the HHGRACE 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula><bold>m SiGe BiCMOS process. A frequency-domain characteristic-based segmented matching strategy is adopted, which leverages the substantial frequency-dependent variation of inductive/capacitive reactance within the operating band—particularly the inductive reactance of choke coils—to separately construct targeted low- and high-frequency impedance matching networks. Measurement results show that the PA achieves an ultra-wide bandwidth of 2–18 GHz (160% fractional bandwidth) with a gain of 31 dB at 10 GHz and a small gain ripple of ±0.5 dB. It maintains <inline-formula> <tex-math>$S$ </tex-math></inline-formula><inline-formula> <tex-math>${}_{mathbf {11}}$ </tex-math></inline-formula><-<bold>10 dB and <inline-formula> <tex-math>$S$ </tex-math></inline-formula><inline-formula> <tex-math>${}_{mathbf {22}}$ </tex-math></inline-formula>< -<bold>8.5 dB across the band, with a 1-dB compression point (<italic>OP<inline-formula> <tex-math>${}_{mathbf {1dB}}$ </tex-math></inline-formula>) of 14.7 dBm, a maximum saturated output power (<inline-formula> <tex-math>${P} _{mathbf {SAT}}$ </tex-math></inline-formula>) of 15.7 dBm and a peak power-added efficiency (<italic>PAE) of 14.88% at 8 GHz. The PA features a compact core area of 0.245 mm2. Compared to state-of-the-art designs, the proposed PA realizes ultra-wide bandwidth, high gain, flat gain response, and compact size, making it suitable for modern ultra-wideband communication systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"548-552"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Quiescent-Current Output-Capacitorless Low-Dropout Regulator With a Dual-Path Adaptive-Biasing Technique 基于双路自适应偏置技术的低静态电流输出无电容低压差稳压器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-06 DOI: 10.1109/TCSII.2026.3671470

Jiatao Chen;Jing Wang;Xu Han;Minghao Shang;Xiaoyu Guo;Xuefei Bai;Lin Cheng

引用次数: 0

A 4-GHz Ring-VCO-Based Wideband Double-Sampling PLL With −88.2-dBc Reference Spur, 119-fsRMS Jitter and −244.1-dB FOM 基于4ghz环形vco的宽带双采样锁相环，参考杂散为−88.2 dbc，抖动为119 fsrms， FOM为−244.1 db

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-04-03 DOI: 10.1109/TCSII.2026.3680570

Longbiao Wang;Ming Che;Tianyuan Zhang;Guanghui Zhao;Pengcheng He;Na Yan;Yu Zhao;Hao Xu;Peng Chen;Xiongchuan Huang

引用次数: 0

A Hardware/Software Co-Optimization of HQC Using Tightly-Coupled Accelerators on a 32-bit Ibex Core 基于32位Ibex内核的紧耦合加速器HQC软硬件协同优化

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-02-26 DOI: 10.1109/TCSII.2026.3668482

Seog Chung Seo;YoungBeom Kim

引用次数: 0

Dual Objective Model Predictive Current Control Method for PMSM Drives 永磁同步电机驱动双目标模型预测电流控制方法

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-26 DOI: 10.1109/TCSII.2026.3678100

Chenguang Zhang;Tianyu Yuan;Xiaoguang Zhang;Niko Nevaranta;Pasi Peltoniemi

引用次数: 0

Sliding-Block DFE Error Propagation Correction Under Uncertainty With Reverse-Decision Evaluation for High-Speed Wireline Receiver on FPGA 基于FPGA的高速有线接收机不确定条件下滑动块DFE误差传播校正

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-31 DOI: 10.1109/TCSII.2026.3679301

Se-Ung Park;Junyeong Lee;Jaemin Choi;Jung-Hoon Chun

{"title":"Sliding-Block DFE Error Propagation Correction Under Uncertainty With Reverse-Decision Evaluation for High-Speed Wireline Receiver on FPGA","authors":"Se-Ung Park;Junyeong Lee;Jaemin Choi;Jung-Hoon Chun","doi":"10.1109/TCSII.2026.3679301","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3679301","url":null,"abstract":"This brief presents a PAM-4 sliding-block decision feedback equalizer (SB-DFE) employing the correction under uncertainty with reverse-decision evaluation (CURE) scheme. Conventional SB-DFE resolves timing bottlenecks in high-tap DFE by breaking the feedback loop, but remains vulnerable to intra-block error propagation. To address this, the CURE scheme is integrated for localized sequence estimation, which conditionally evaluates candidate sequences prompted by unreliable decisions to suppress error propagation with minimal complexity. Leveraging the SB-DFE structure to compensate for long-tail post-cursor intersymbol interference enables the use of a shortened feed-forward equalizer (FFE). This provides a higher signal-to-noise ratio for CURE than 4-state maximum likelihood sequence detection (MLSD), as the latter suffers from noise amplification in its longer FFE. Field-programmable gate array-based link emulation confirms the proposed architecture outperforms 4-state MLSD across various noise conditions. ASIC synthesis in a 28-nm FD-SOI technology further confirms that the design reduces area and power by <inline-formula> <tex-math>$2.90times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$4.05times $ </tex-math></inline-formula>, respectively, relative to the MLSD benchmark.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"563-567"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0