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IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-01 DOI: 10.1109/TCSII.2025.3580983
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引用次数: 0
IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-01 DOI: 10.1109/TCSII.2025.3580985
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3580985","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580985","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11061369","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector 一种1.58 pJ/b 9gbps无参考时钟和数据恢复电路与Sigma距离检测器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-09 DOI: 10.1109/TCSII.2025.3577785
Jongchan An;Seung-Myeong Yu;Gwangmyeong An;Songi Cheon;Hyunsu Jang;Junyoung Song
{"title":"A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector","authors":"Jongchan An;Seung-Myeong Yu;Gwangmyeong An;Songi Cheon;Hyunsu Jang;Junyoung Song","doi":"10.1109/TCSII.2025.3577785","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3577785","url":null,"abstract":"A 1.58 pJ/b 9 Gbps half-rate reference-less clock and data recovery (CDR) circuit with a sigma range detector (SRD) is presented. The SRD detects the standard deviation of the reference clock frequency error extracted from random data when the stochastic divider ratio is set to 256. The proposed SRD-based CDR mitigates the trade-off between the divider ratio induced by the randomness of the PRBS and the frequency error. This approach enhances the calculation speed of the frequency loop and improves the accuracy of the extracted frequency by eliminating additional compensation stages, resulting in reduced power consumption. The proposed CDR was fabricated in a 65-nm CMOS technology. The lock-time for PRBS11 is <inline-formula> <tex-math>$2.7~mu $ </tex-math></inline-formula>s, with a rms jitter of 1.1 ps and a peak-to-peak jitter of 16 ps. The active area of the design is 0.0636 mm2, with a power efficiency of 1.58 pJ/b.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"888-892"},"PeriodicalIF":4.0,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Ku-Band Broadband 8-Channel 8-Beam Phased-Array Receiver With Polarization Agility and Beam Reconfiguration for SATCOM Applications 一种具有极化敏捷性和波束重构的ku波段宽带8通道8波束相控阵接收机
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-09 DOI: 10.1109/TCSII.2025.3578020
Zhuoheng Xie;Yue Feng;Bo Huang;Zihan Zhang;Heng Zhao;Lan Liu;Zhihao Liu;Zhigang Li;Xiulong Wu
{"title":"A Ku-Band Broadband 8-Channel 8-Beam Phased-Array Receiver With Polarization Agility and Beam Reconfiguration for SATCOM Applications","authors":"Zhuoheng Xie;Yue Feng;Bo Huang;Zihan Zhang;Heng Zhao;Lan Liu;Zhihao Liu;Zhigang Li;Xiulong Wu","doi":"10.1109/TCSII.2025.3578020","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578020","url":null,"abstract":"This brief presents a Ku-band broadband 8-channel 8-beam phased-array receiver with polarization agility and dynamic beam reconfiguration, addressing the growing demand for Low Earth Orbit (LEO) and high-throughput satellite communications (SATCOM). The receiver chip integrates 32 independently controlled amplitude and phase channels, utilizing an innovatively designed reconfigurable power divider network to flexibly support single-beam, dual-beam, four-beam, and eight-beam modes, while enabling dynamic selection between horizontal and vertical polarization. Furthermore, the receiver system adopts a hybrid architecture combining a 6-bit active vector-modulated phase shifter and a 6-bit passive attenuator to achieve high-precision amplitude and phase control. Measurement results demonstrate a wide operational frequency range from 10 GHz to 15 GHz, achieving a remarkable channel gain of 24.5 dB and an input 1-dB gain compression point (IP1dB) exceeding 15.8 dBm. The root mean square (RMS) phase and amplitude errors are below 5.19° and 0.24 dB, respectively. Fabricated using a 0.18 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe Bi-CMOS process, the chip features a compact area of <inline-formula> <tex-math>$6.7 times 5.3,text {mm}^{2}$ </tex-math></inline-formula> and a total power consumption of less than 465 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"893-897"},"PeriodicalIF":4.0,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory Optimized, High Signal Quality Direct Digital Frequency Synthesizer on an FPGA 基于FPGA的内存优化、高信号质量直接数字频率合成器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-03 DOI: 10.1109/TCSII.2025.3576310
Kalle I. Palomäki;Jari Nurmi
{"title":"Memory Optimized, High Signal Quality Direct Digital Frequency Synthesizer on an FPGA","authors":"Kalle I. Palomäki;Jari Nurmi","doi":"10.1109/TCSII.2025.3576310","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3576310","url":null,"abstract":"Direct digital frequency synthesis is a method for generating digital samples of periodic analog signals. It has been broadly used for decades in applications such as digital radios and radars. The common approaches utilize read-only memory (ROM) for creating amplitude values, and a lot of research focus has been put into reducing the required ROM size. In this brief, we are presenting a memory optimized Direct Digital Frequency Synthesizer (DDFS) architecture that applies the <inline-formula> <tex-math>$3{^{text {rd}}}$ </tex-math></inline-formula> order Taylor series approximation for amplitude computation. To evaluate the architecture performance, also traditional ROM-based architecture is introduced. Both approaches are implemented using VHDL code on a field programmable gate array (FPGA). The FPGA resource utilization, memory consumption, and signal quality are analyzed and compared with other recently published DDFS approaches. Based on the simulation and implementation results, the proposed new architecture consumes only 270 bits of memory and has the output signal spurious free dynamic range (SFDR) of –103.6 dBc.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"958-962"},"PeriodicalIF":4.0,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11022740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Reconfigurable Wireless Charging System Achieving Constant Current and Constant Voltage Conversion by a Single Secondary-Side Switch 一种利用单次侧开关实现恒流恒压转换的新型可重构无线充电系统
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-03 DOI: 10.1109/TCSII.2025.3576132
Tao Li;Yijie Wang;Yang Li;Jianwei Mai;Zhichao Sun;Jian Cui;Ao Yang;Dianguo Xu
{"title":"A Novel Reconfigurable Wireless Charging System Achieving Constant Current and Constant Voltage Conversion by a Single Secondary-Side Switch","authors":"Tao Li;Yijie Wang;Yang Li;Jianwei Mai;Zhichao Sun;Jian Cui;Ao Yang;Dianguo Xu","doi":"10.1109/TCSII.2025.3576132","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3576132","url":null,"abstract":"The wireless charging process for lithium batteries involves two key phases: constant current (CC) mode and constant voltage (CV) mode. This brief introduces a novel method for topology reconfiguration, simplifying the CC and CV conversion with the control of a single secondary-side switch. The system leverages a three-coil structure for CC output and employs a single switch to reconstruct the two secondary coils, achieving CV output. This approach stands out from previous solutions that required primary control and multiple switches. Using a single switch on the secondary side significantly simplifies the system control and eliminates the necessity for communication with the primary side. These improvements contribute to heightened system reliability. To validate this concept, a prototype with a maximum output of 1.2 kW was developed and tested.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"973-977"},"PeriodicalIF":4.0,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clock Edge Triggering Control in Topology-Based Logic Dynamic Systems Using Matrix Approaches 基于矩阵方法的拓扑逻辑动态系统时钟边触发控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-29 DOI: 10.1109/TCSII.2025.3565551
Yingzhe Jia;Jiayu Hu;Yiliang Li;Peng Guo;Qianming Xu;An Luo;Abdelhamid Tayebi
{"title":"Clock Edge Triggering Control in Topology-Based Logic Dynamic Systems Using Matrix Approaches","authors":"Yingzhe Jia;Jiayu Hu;Yiliang Li;Peng Guo;Qianming Xu;An Luo;Abdelhamid Tayebi","doi":"10.1109/TCSII.2025.3565551","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3565551","url":null,"abstract":"In this brief, we depict the clock edge triggering control of topology-based logic dynamic systems (TLDSs) often seen in nowadays digital circuits and electronics chips. The state-space equations (SSEs) of TLDSs are firstly derived, and the necessary and sufficient conditions are given for determining the existence of a clock edge triggering control in TLDSs using the properties of the matrices in the SSEs. The effectiveness of the proposed method is then validated in the equivalent TLDS of a practical engineering chip.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"833-837"},"PeriodicalIF":4.0,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Neural-Learning-Based Adaptive Sliding Mode Impedance Force Control of Robotic Microinjection Systems Interacting With Viscoelastic Cells 基于神经学习的机器人微注射系统粘弹性单元相互作用的自适应滑模阻抗力控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-25 DOI: 10.1109/TCSII.2025.3564463
Shengzheng Kang;Tao Li;Xiaolong Yang;Yao Li;Mingyang Xie
{"title":"Neural-Learning-Based Adaptive Sliding Mode Impedance Force Control of Robotic Microinjection Systems Interacting With Viscoelastic Cells","authors":"Shengzheng Kang;Tao Li;Xiaolong Yang;Yao Li;Mingyang Xie","doi":"10.1109/TCSII.2025.3564463","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3564463","url":null,"abstract":"Robotic microinjection has been widely applied in biomedical engineering, but faces a great challenge on the precise force interaction with cells due to their inherently deformable, fragile, and nonlinear viscoelastic properties. This brief proposes a new neural-learning based adaptive sliding mode impedance force control scheme for the robotic microinjection system to improve the interaction performance. The key features of the developed method are as follows: i) Target impedance is derived by utilizing the nonlinear Hunt-Crossley model to match the microscale interaction with environmental cells; ii) An integral terminal sliding mode manifold based on the impedance error is designed to achieve finite-time convergence and accurate force tracking; iii) The proposed scheme relieves the burden of environmental model dependence by estimating the uncertain bound of external disturbances through an adaptive neural network compensator. The control system stability is analyzed by the Lyapunov theory, and the force tracking performance is also verified via a series of experiments.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"828-832"},"PeriodicalIF":4.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SSPP Transmission System With Negative Group Delay and Power Compensation 具有负群延迟和功率补偿的SSPP传输系统
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-25 DOI: 10.1109/TCSII.2025.3564569
Guodong Lu;Qi Kang;Weiwen Li
{"title":"SSPP Transmission System With Negative Group Delay and Power Compensation","authors":"Guodong Lu;Qi Kang;Weiwen Li","doi":"10.1109/TCSII.2025.3564569","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3564569","url":null,"abstract":"The advanced signal output based on negative group delay (NGD) plays a pivotal role in real-time communication and sensing applications. However, the implementation of NGD often results in significant signal attenuation. Spoof surface plasmon polariton (SSPP) units with tightly coupled structures are capable of generating NGD near the sidebands. Building on this principle, an NGD SSPP unit is proposed in this brief by utilizing tightly folded structures. The NGD SSPP unit is integrated into the classical SSPP waveguide with an H-shaped unit to control the transmission group delay. This waveguide configuration facilitates the advanced output of double-sideband modulation signals. Nevertheless, the generation of negative group delay is also typically accompanied by considerable transmission losses. To address this challenge, a low-noise amplifier is designed for power compensation. The SSPP waveguide with the NGD unit is then cascaded with the low-noise amplifier, resulting in an SSPP transmission system with power compensation for the NGD signal.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"868-872"},"PeriodicalIF":4.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 22.5~28.5 -GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS 基于平面度增强技术的22.5~28.5 ghz低振幅变化低相位误差混合移相器，用于40nm CMOS下的5G NR
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-23 DOI: 10.1109/TCSII.2025.3563519
Shiping Zheng;Yun Wang;Ziyang Deng;Chen Jiang;Hongtao Xu
{"title":"A 22.5~28.5 -GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS","authors":"Shiping Zheng;Yun Wang;Ziyang Deng;Chen Jiang;Hongtao Xu","doi":"10.1109/TCSII.2025.3563519","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3563519","url":null,"abstract":"This brief presents a hybrid phase shifter (PS) that integrates a three-stage switch-type phase shifter (STPS) and a one-stage reflect-type phase shifter (RTPS). The STPS utilizes a flatness-enhanced <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-network topology to reduce phase error and insertion loss (IL) variation by eliminating feedback and resonant capacitors. The RTPS enables continuous phase shifting with a 4-bit capacitor array and varactor. The proposed hybrid PS achieves an IL variation of ±0.7 dB and an RMS phase error of 0.3° to 1.2° in the <inline-formula> <tex-math>$22.5sim 28$ </tex-math></inline-formula>.5 GHz range. Compared to existing designs, the hybrid PS offers superior performance in phase accuracy, IL variation, and area efficiency, with a compact area of <inline-formula> <tex-math>$151times 342~mathrm {mu } m^{2}$ </tex-math></inline-formula>, fabricated using standard 40nm CMOS technology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"813-817"},"PeriodicalIF":4.0,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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