IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-09-25 DOI: 10.1109/TCSII.2025.3607550

引用次数: 0

IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-09-25 DOI: 10.1109/TCSII.2025.3607552

引用次数: 0

Performance Bounds for a Maxima-Sampling Envelope Detector 最大采样包络检测器的性能边界

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-09-02 DOI: 10.1109/TCSII.2025.3605161

Swagat Bhattacharyya

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Timestep-Parallel 4D Neuromorphic Computing Array Enabling High Computing Power Density and High Energy Efficiency 时间步进并行4D神经形态计算阵列，实现高计算能力密度和高能效

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-29 DOI: 10.1109/TCSII.2025.3603624

Pujun Zhou;Changhui Xiao;Liwei Meng;Qi Yu;Ning Ning;Yang Liu;Shaogang Hu;Guanchao Qiao

{"title":"Timestep-Parallel 4D Neuromorphic Computing Array Enabling High Computing Power Density and High Energy Efficiency","authors":"Pujun Zhou;Changhui Xiao;Liwei Meng;Qi Yu;Ning Ning;Yang Liu;Shaogang Hu;Guanchao Qiao","doi":"10.1109/TCSII.2025.3603624","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3603624","url":null,"abstract":"The timestep-based inference process of spiking neural networks (SNNs) presents two challenges for neuromorphic chip design: 1) additional storage overhead for membrane potentials, and 2) significant power consumption resulting from repeated access to computational data. To address this challenge, this work proposes a timestep-parallel 4D neuromorphic computing array of size <inline-formula> <tex-math>$N_{T}times N_{Z}times N_{X}times N_{Y}$ </tex-math></inline-formula>, simultaneously enabling parallel computing in temporal and spatial dimensions. The <inline-formula> <tex-math>$N_{T}$ </tex-math></inline-formula> dimension supports timestep-parallel computing, the <inline-formula> <tex-math>$N_{Z}$ </tex-math></inline-formula> dimension supports neuron-parallel computing, and the <inline-formula> <tex-math>$N_{X}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$N_{Y}$ </tex-math></inline-formula> dimensions are used for synapse-parallel computing. The architecture facilitates flexible data reuse across different dimensions (with weights reuse along different timesteps and spikes reuse along different neurons), significantly reducing storage access. Meanwhile, it treats the membrane potential as a short-term computational variable that can be stored in a small buffer, thereby eliminating large-scale membrane potential storage overhead and access. The reduction in data access and storage costs is beneficial for lowering system power consumption and enhancing synaptic energy efficiency. Ultimately, the architecture is evaluated using a 28 nm process library and demonstrates a high computing power density of 1160 GSOP/s/mm2 and a high synaptic energy efficiency of 0.36 pJ/SOP, surpassing related state-of-the-art works. This work significantly reduces the hardware cost of neuromorphic computing and is expected to enhance the competitiveness of neuromorphic hardware in contemporary artificial intelligence applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1448-1452"},"PeriodicalIF":4.9,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-28 DOI: 10.1109/TCSII.2025.3600134

引用次数: 0

Optimal Control for Power System Signal Processing: A Joint Edge Collaboration and Relay Assistance Framework 电力系统信号处理的最优控制：一个联合边缘协作和继电器辅助框架

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-21 DOI: 10.1109/TCSII.2025.3601095

Mingrui Zhang;Xuguang Hu;Jingyu Wang

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Hysteresis-Estimator-Based Adaptive Fuzzy Control for Piezoelectric Micro-Positioning Stage With Time-Varying Output Constraints 基于迟滞估计的时变输出约束压电微定位台自适应模糊控制

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-21 DOI: 10.1109/TCSII.2025.3601156

Linlin Nie;Yewei Yu;Miaolei Zhou;Xiuyu Zhang;Chun-Yi Su

{"title":"Hysteresis-Estimator-Based Adaptive Fuzzy Control for Piezoelectric Micro-Positioning Stage With Time-Varying Output Constraints","authors":"Linlin Nie;Yewei Yu;Miaolei Zhou;Xiuyu Zhang;Chun-Yi Su","doi":"10.1109/TCSII.2025.3601156","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3601156","url":null,"abstract":"This brief addresses the high-precision motion control of piezoelectric micro-positioning stages (PMPSs) subject to time-varying output constraints, input hysteresis nonlinearity, and system uncertainties. The key features of the developed hysteresis-estimator-based adaptive fuzzy control (HEAFC) method are as follows. First, an asymmetric rate-dependent hysteresis operator is used to construct an extended fuzzy input space, enabling a fuzzy dynamic hysteresis estimator (FDHE) for real-time hysteresis estimation via adaptive fuzzy logic. Second, auxiliary functions are embedded into a backstepping-like control framework to explicitly handle time-varying output constraints. Moreover, by leveraging the structural characteristics of fuzzy systems, the HEAFC scheme avoids repeated differentiation or filtering of virtual control laws. This feature can substantially simplify the control structure. The HEAFC method guarantees prespecified constraint satisfaction and high-accuracy trajectory tracking. Lyapunov-based analysis ensures closed-loop stability, and experimental results on a PMPS demonstrate the effectiveness of the HEAFC strategy.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1418-1422"},"PeriodicalIF":4.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reinforcement Learning for Dynamic Event-Driven Control of Multi-Machine Power Systems 多机电力系统动态事件驱动控制的强化学习

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-19 DOI: 10.1109/TCSII.2025.3600432

Xiong Yang;Ding Wang

引用次数: 0

A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis 一种电容性过中和抑制冻结诱发迟滞的低温cmos三尾比较器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-07 DOI: 10.1109/TCSII.2025.3596708

Bram Veraverbeke;Filip Tavernier

{"title":"A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis","authors":"Bram Veraverbeke;Filip Tavernier","doi":"10.1109/TCSII.2025.3596708","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3596708","url":null,"abstract":"Dopant freeze-out severely increases the bulk resistance of cryogenic bulk CMOS transistors by up to <inline-formula> <tex-math>$10{^{{6}}} {times }$ </tex-math></inline-formula> at 4.2K compared to room temperature. This brief describes, for the first time in the literature, how this increased bulk resistance introduces a memory effect in the latch of dynamic comparators, which leads to hysteresis. To measure this hysteresis reliably in the presence of noise, a statistical characterization procedure is developed. For a 40nm bulk CMOS strongARM comparator with an input-referred noise voltage of 348<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> VRMS, a hysteresis voltage >898<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> V is measured at 6K, substantially deteriorating the precision. Therefore, this brief introduces a triple tail comparator with capacitive over-neutralization to increase the preamplification gain, suppressing the hysteresis ><inline-formula> <tex-math>$6{times }$ </tex-math></inline-formula> to only 141<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> V.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1358-1362"},"PeriodicalIF":4.9,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Integrated Configurable FMCW Radar Baseband SoC in 40-nm CMOS 集成可配置FMCW雷达基带SoC在40nm CMOS

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-07 DOI: 10.1109/TCSII.2025.3596605

Peng Zhang;Bo Wang;Ning Zhang;Pengfei Diao;Qisong Wu;Dixian Zhao

{"title":"An Integrated Configurable FMCW Radar Baseband SoC in 40-nm CMOS","authors":"Peng Zhang;Bo Wang;Ning Zhang;Pengfei Diao;Qisong Wu;Dixian Zhao","doi":"10.1109/TCSII.2025.3596605","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3596605","url":null,"abstract":"This brief introduces an integrated configurable frequency-modulated continuous wave (FMCW) radar baseband SoC, which integrates a baseband accelerator in 40-nm CMOS technology. This brief exhibits notable advantages in terms of miniaturization, configurability, and real-time performance. To enhance the real-time performance of baseband signal processing, the baseband accelerator employs a pipeline architecture that incorporates specifically designed parallel computation structures for each submodule. Furthermore, this design enables the accelerator to support diverse application scenarios by offering configurable dimensions for fast Fourier transform (FFT), constant false alarm rate (CFAR), and digital beamforming (DBF), along with adjustable parameters for time-frequency domain processing. Board-level testing results indicate that the chip can accurately distinguish targets with varying distances, speeds, and angles. Operating at a system clock frequency of 200 MHz, the processor achieves a frame processing time of 2.79 ms and a power consumption of 492 mW, under the maximum CFAR window configuration and 256 targets.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1438-1442"},"PeriodicalIF":4.9,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0