IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

{"title":"Offset-Tolerant Body-Biased Sense Amplifier With Rise-Time Control Technique for SRAM","authors":"Jaehwan Kim;Mingu Han;Bayartulga Ishdorj;Taehui Na","doi":"10.1109/TCSII.2025.3558562","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3558562","url":null,"abstract":"In this brief, we propose an Offset-Tolerant Body-biased sense amplifier (OTB-SA) with a rise-time <inline-formula> <tex-math>$(T_{mathrm { RISE}})$ </tex-math></inline-formula> control technique to address the sensing failure issue that occurs when the input voltage difference <inline-formula> <tex-math>$({Delta }V_{mathrm { BL}})$ </tex-math></inline-formula> of a latch-type SA is smaller than the offset voltage <inline-formula> <tex-math>$(V_{mathrm { OS}})$ </tex-math></inline-formula>. The OTB-SA with <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> leverages body biasing and <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> control to enhance the differential signal injection (DSI) effect, thereby reducing both <inline-formula> <tex-math>$V_{mathrm { OS}}$ </tex-math></inline-formula> and energy consumption. Post-layout HSPICE simulation results using a 28 nm technology model indicate that, when target <inline-formula> <tex-math>$V_{mathrm { OS}}$ </tex-math></inline-formula> standard deviation <inline-formula> <tex-math>$({sigma }_{mathrm { OS}})$ </tex-math></inline-formula> is 5 mV, the OTB-SA with <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> achieves a 49.6% reduction in area and a 60.1% decrease in energy consumption compared to a voltage-latched SA (VLSA) without <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula>. Moreover, compared to previous SAs, the OTB-SA with <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> showed up to 69.1% area reduction and up to 91.2% energy consumption reduction. Measurements from a 28 nm test chip confirmed that <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> control is effective, showing a trend where <inline-formula> <tex-math>${sigma }_{mathrm { OS}}$ </tex-math></inline-formula> decreases as <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> increases for OTB-SA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"773-777"},"PeriodicalIF":4.0,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS","authors":"Boyang Zhang;Tianchen Ye;Zhifei Wang;Xin Liu;Tianyuan Zhong;Ruixu Wang;Weixin Gai","doi":"10.1109/TCSII.2025.3557793","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3557793","url":null,"abstract":"Optical transmission has been widely employed in data-centers, but the complex impairments including the non-linearity induced by the laser modulator degrade the signal. Conventional optical modules use DSP-based transceivers to address these impairments, but they rely on advanced technology, consuming much power and area as well. A 4x106Gb/s mixed-signal PAM-4 transceivers fabricated in 28nm CMOS are proposed in this brief to reduce cost, area and power consumption. The transceiver supports adaptive linearity compensation with analog PAM4 level pre-distortion technique in TX. 4-tap FFE and 7-tap DFE including 4 floating taps are implemented in RX to take DFE’s advantage of not amplifying noise thanks to the mixed-signal structure. The transceiver achieves an optical sensitivity of -8.7dBm, which is 0.7dBm better than the DSP-based equalization methods under the same optical test environment. The energy efficiency and single-channel area are 4.42pJ/bit and 0.28mm2 respectively, both of which are better than reported 100Gb/s counterparts.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"728-732"},"PeriodicalIF":4.0,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Self-Learning Tracking Control for Switched Systems: A Triggered-Learning Model Predictive Control Method","authors":"Tianxiang Dong;Yiwen Qi;Shitong Guo","doi":"10.1109/TCSII.2025.3557419","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3557419","url":null,"abstract":"Existing model predictive control (MPC) methods lack online learning capability in complex environments. Reinforcement learning (RL) requires a lot of data and computing resources to obtain optimal control. This brief uses efficient self-learning to solve this problem. “Efficient” refers to the use of triggered-learning mechanism (TLM) to manage computing resources on demand. This brief proposes a triggered-learning model predictive control (TL-MPC) method for switched systems. The proposed TL-MPC endows MPC with learning capabilities through the TLM. TLM includes a Deep Deterministic Policy Gradient (DDPG) based control incremental self-learning tuning strategy and a performance-driven event-triggering strategy. The first strategy is to give the MPC controller a control increment to optimize control effect. The second strategy is to realize the on-demand learning and reduce computational resources by comparing two cost functions that characterize the system performance. In addition, the stability of switched systems under TL-MPC is analyzed using the Lyapunov function and the average dwell time technique. Finally, the effectiveness of the proposed method is verified by simulation.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"748-752"},"PeriodicalIF":4.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3550045","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550045","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945817","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3550043","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550043","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945880","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Bypass Architecture for RB-COT Buck Converters","authors":"Francesco Gabriele;Samuele Gisonno;Filippo Fiori;Davide Lena;Salvatore Rosario Musumeci;Fabio Pareschi;Gianluca Setti","doi":"10.1109/TCSII.2025.3555695","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3555695","url":null,"abstract":"In this brief we propose a novel ByPass (BP) circuit that overcomes the voltage regulation limit in the Ripple Based Constant On-Time (RB-COT) Buck converters due to intrinsic presence of a minimum achievable OFF time. The BP stage is conceived to be embedded in the RB-COT modulator located within the converter feedback loop, and only intervening when the minimum OFF time condition is reached. The latter implies that the COT modulator saturates, and consequently, the output voltage regulation of the converter is no longer guaranteed. Conversely, the BP stage does not affect the behavior of the circuit when it operates in normal regulating condition. The effectiveness of the proposed BP stage is confirmed through both transistor-level simulation results derived from the SPICE platform and experimental measurements on a integrated circuit prototype implemented in a 0.18 um Bipolar-CMOS-DMOS process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"793-797"},"PeriodicalIF":4.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A D-Band Low-Noise Amplifier With Gm-Boosting Technique Based on Asymmetric Coupling","authors":"Yun Qian;Yizhu Shen;Yifan Ding;Sanming Hu","doi":"10.1109/TCSII.2025.3555310","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3555310","url":null,"abstract":"This brief presents a D-band low noise amplifier (LNA) in a 40 nm bulk CMOS process. The proposed LNA includes five stages of single-ended common-gate amplifiers. The input and interstage matching networks are realized by asymmetric transformers, which effectively enhance the equivalent transconductance <inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula> of the subsequent transistor. The asymmetric transformer features the segmented structure, offering enhanced design flexibility, and exhibits characteristics of low loss and low parasitic parameters, enabling broadband matching. Leveraging the asymmetric transformer, the LNA achieves simultaneous matching of impedance and noise. The measured power gain is 18.4 dB, with a 3-dB bandwidth of 26.8 GHz from 139.9 to 166.7 GHz. Within the effective bandwidth, the measured minimum noise figure is 5.7 dB. The LNA operates with a power consumption of 17.3 mW under a 0.9 V supply, featuring a total area of <inline-formula> <tex-math>$0.184~{mathrm {mm}}^{2}$ </tex-math></inline-formula> and a core area of 0.062 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"708-712"},"PeriodicalIF":4.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs","authors":"Xing Wang;Chaoyang Xing;Yi Zhong;Lu Jie;Nan Sun","doi":"10.1109/TCSII.2025.3554617","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3554617","url":null,"abstract":"Data weighted averaging (DWA) is a frequently used dynamic element matching (DEM) technique to shape the mismatch error in <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADCs. However, DWA faces a weak noise-shaping capability issue and introduces harmonic distortion under small signal inputs. By contrast, 2nd-order DEM solves these problems but suffers from the high hardware complexity issue. To address these issues, this brief presents a first-in-last-out DWA (FILO-DWA) technique for multi-bit <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADCs. This technique combines the merits of DWA and 2nd-order DEM. Compared with DWA, it introduces no harmonics and enhances the mismatch shaping ability. In contrast to the 2nd-order vector-quantizer-based (VQ-based) DEM scheme, it achieves more than 10 times hardware cost reduction with negligible shaping ability loss. This technique offers a feasible DWA alternative for high-accuracy <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADC design.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"703-707"},"PeriodicalIF":4.0,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 10-Bit 500-MS/s Pipelined SAR ADC With Feedback Factor Compensation in 6-nm FinFET","authors":"Yigi Kwon;Jongyoon Won;Byounghan Min;Dooyeoun Kim;Jihyun Kim;Jeong-Hyu Yang;Youngcheol Chae","doi":"10.1109/TCSII.2025.3554297","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3554297","url":null,"abstract":"This brief introduces an energy-efficient 10-bit 500-MS/s pipelined SAR ADC that uses feedback factor compensation in 6-nm FinFET technology. The design challenges of residue amplifier in FinFET technology are adequately addressed by incorporating feedback factor compensation. This includes a dynamic negative capacitance circuit at the virtual ground that compensates for the feedback factor and relaxes the requirements of the residue amplifier. This enables the use of an inverter-based residue amplifier that can achieve a high-speed operation of 500-MS/s at a low supply voltage of 0.9 V. The prototype ADC is fabricated in a 6-nm FinFET and occupies 0.014 <inline-formula> <tex-math>$text {mm}^{{2}}$ </tex-math></inline-formula>. With a Nyquist input signal, it achieves an SNR of 54.2 dB and an SNDR of 53.6 dB, while consuming 2.7 mW from a 0.9 V supply voltage. This brief achieves a competitive Walden figure of merit (FoM) of 13.8 fJ/conv.-step.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"698-702"},"PeriodicalIF":4.0,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cooperative Resilient Secondary Control for AC/DC Microgrid Under Cyber Attacks","authors":"Kejie Wang;Sha Fan;Mengmeng Chen;Chao Deng","doi":"10.1109/TCSII.2025.3554348","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3554348","url":null,"abstract":"In this brief, the distributed resilient secondary control problems under hybrid attacks involving false data injection (FDI) and denial-of-service (DoS) attacks in hybrid AC/DC microgrids (MGs) are investigated. To address these issues, a distributed iterative observer is first designed to accurately estimate the FDI attack signal as well as the AC bus frequency, the AC main bus voltage, active power, and reactive power of each BIC under hybrid attacks. Then, based on the iterative mean estimation, a distributed resilient secondary controller is designed to compensate for the hybrid attacks, achieving the accurate recovery of AC bus frequency and AC main bus voltage as well as active/reactive power sharing among BICs under hybrid attacks. Compared with existing results, the proposed distributed resilient control strategy enhances the transient performance of AC/DC hybrid MGs during both the injection and disappearance of FDI attacks against hybrid attacks. Finally, through theoretical analysis and a real-time experiment in OPAL-RT, the effectiveness and plug-and-play performance of the proposed method is verified.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"743-747"},"PeriodicalIF":4.0,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}