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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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Clock Edge Triggering Control in Topology-Based Logic Dynamic Systems Using Matrix Approaches 基于矩阵方法的拓扑逻辑动态系统时钟边触发控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-29 DOI: 10.1109/TCSII.2025.3565551
Yingzhe Jia;Jiayu Hu;Yiliang Li;Peng Guo;Qianming Xu;An Luo;Abdelhamid Tayebi
{"title":"Clock Edge Triggering Control in Topology-Based Logic Dynamic Systems Using Matrix Approaches","authors":"Yingzhe Jia;Jiayu Hu;Yiliang Li;Peng Guo;Qianming Xu;An Luo;Abdelhamid Tayebi","doi":"10.1109/TCSII.2025.3565551","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3565551","url":null,"abstract":"In this brief, we depict the clock edge triggering control of topology-based logic dynamic systems (TLDSs) often seen in nowadays digital circuits and electronics chips. The state-space equations (SSEs) of TLDSs are firstly derived, and the necessary and sufficient conditions are given for determining the existence of a clock edge triggering control in TLDSs using the properties of the matrices in the SSEs. The effectiveness of the proposed method is then validated in the equivalent TLDS of a practical engineering chip.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"833-837"},"PeriodicalIF":4.0,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Neural-Learning-Based Adaptive Sliding Mode Impedance Force Control of Robotic Microinjection Systems Interacting With Viscoelastic Cells 基于神经学习的机器人微注射系统粘弹性单元相互作用的自适应滑模阻抗力控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-25 DOI: 10.1109/TCSII.2025.3564463
Shengzheng Kang;Tao Li;Xiaolong Yang;Yao Li;Mingyang Xie
{"title":"Neural-Learning-Based Adaptive Sliding Mode Impedance Force Control of Robotic Microinjection Systems Interacting With Viscoelastic Cells","authors":"Shengzheng Kang;Tao Li;Xiaolong Yang;Yao Li;Mingyang Xie","doi":"10.1109/TCSII.2025.3564463","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3564463","url":null,"abstract":"Robotic microinjection has been widely applied in biomedical engineering, but faces a great challenge on the precise force interaction with cells due to their inherently deformable, fragile, and nonlinear viscoelastic properties. This brief proposes a new neural-learning based adaptive sliding mode impedance force control scheme for the robotic microinjection system to improve the interaction performance. The key features of the developed method are as follows: i) Target impedance is derived by utilizing the nonlinear Hunt-Crossley model to match the microscale interaction with environmental cells; ii) An integral terminal sliding mode manifold based on the impedance error is designed to achieve finite-time convergence and accurate force tracking; iii) The proposed scheme relieves the burden of environmental model dependence by estimating the uncertain bound of external disturbances through an adaptive neural network compensator. The control system stability is analyzed by the Lyapunov theory, and the force tracking performance is also verified via a series of experiments.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"828-832"},"PeriodicalIF":4.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SSPP Transmission System With Negative Group Delay and Power Compensation 具有负群延迟和功率补偿的SSPP传输系统
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-25 DOI: 10.1109/TCSII.2025.3564569
Guodong Lu;Qi Kang;Weiwen Li
{"title":"SSPP Transmission System With Negative Group Delay and Power Compensation","authors":"Guodong Lu;Qi Kang;Weiwen Li","doi":"10.1109/TCSII.2025.3564569","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3564569","url":null,"abstract":"The advanced signal output based on negative group delay (NGD) plays a pivotal role in real-time communication and sensing applications. However, the implementation of NGD often results in significant signal attenuation. Spoof surface plasmon polariton (SSPP) units with tightly coupled structures are capable of generating NGD near the sidebands. Building on this principle, an NGD SSPP unit is proposed in this brief by utilizing tightly folded structures. The NGD SSPP unit is integrated into the classical SSPP waveguide with an H-shaped unit to control the transmission group delay. This waveguide configuration facilitates the advanced output of double-sideband modulation signals. Nevertheless, the generation of negative group delay is also typically accompanied by considerable transmission losses. To address this challenge, a low-noise amplifier is designed for power compensation. The SSPP waveguide with the NGD unit is then cascaded with the low-noise amplifier, resulting in an SSPP transmission system with power compensation for the NGD signal.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"868-872"},"PeriodicalIF":4.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 22.5~28.5 -GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS 基于平面度增强技术的22.5~28.5 ghz低振幅变化低相位误差混合移相器，用于40nm CMOS下的5G NR
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-23 DOI: 10.1109/TCSII.2025.3563519
Shiping Zheng;Yun Wang;Ziyang Deng;Chen Jiang;Hongtao Xu
{"title":"A 22.5~28.5 -GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS","authors":"Shiping Zheng;Yun Wang;Ziyang Deng;Chen Jiang;Hongtao Xu","doi":"10.1109/TCSII.2025.3563519","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3563519","url":null,"abstract":"This brief presents a hybrid phase shifter (PS) that integrates a three-stage switch-type phase shifter (STPS) and a one-stage reflect-type phase shifter (RTPS). The STPS utilizes a flatness-enhanced <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-network topology to reduce phase error and insertion loss (IL) variation by eliminating feedback and resonant capacitors. The RTPS enables continuous phase shifting with a 4-bit capacitor array and varactor. The proposed hybrid PS achieves an IL variation of ±0.7 dB and an RMS phase error of 0.3° to 1.2° in the <inline-formula> <tex-math>$22.5sim 28$ </tex-math></inline-formula>.5 GHz range. Compared to existing designs, the hybrid PS offers superior performance in phase accuracy, IL variation, and area efficiency, with a compact area of <inline-formula> <tex-math>$151times 342~mathrm {mu } m^{2}$ </tex-math></inline-formula>, fabricated using standard 40nm CMOS technology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"813-817"},"PeriodicalIF":4.0,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 40 TOPS Single-Chip Accelerator Enabling Low-Latency Inference for Deep Neural Networks 一种支持深度神经网络低延迟推理的40 TOPS单芯片加速器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-21 DOI: 10.1109/TCSII.2025.3563062
Xun He;Tao Cao;Youjiang Liu;Le Zhong;Guoping Xiao;Cong Yu
{"title":"A 40 TOPS Single-Chip Accelerator Enabling Low-Latency Inference for Deep Neural Networks","authors":"Xun He;Tao Cao;Youjiang Liu;Le Zhong;Guoping Xiao;Cong Yu","doi":"10.1109/TCSII.2025.3563062","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3563062","url":null,"abstract":"To achieve low latency for edge applications, a single-chip sparse accelerator is proposed, which can conduct deep neural network (DNN) inference only using limited on-chip memory. Private memory is eliminated, and all memories are shared to reduce power and chip area. An adaptive and variable-length compression algorithm is proposed to store sparse DNNs. A weak-constrained pruning algorithm is proposed to resolve load balance issue in kernel level, which can achieve almost the same sparsity as unconstrained pruning schemes (UCP). Based on these works, a low latency inference accelerator is fabricated in 28-nm CMOS with 8256 MACs and 9.4 MB on-chip SRAM, which can achieve a latency of 0.44 ms for YOLO3 tiny. For high-sparsity layers, our chip can achieve <inline-formula> <tex-math>$6.1times $ </tex-math></inline-formula> speedup and a throughput of 40 TOPS. With a pruned YOLO model, our accelerator achieves <inline-formula> <tex-math>$6.7times $ </tex-math></inline-formula> lower latency and <inline-formula> <tex-math>$21.7times $ </tex-math></inline-formula> better energy efficiency than Jetson Orin. A high-speed evaluation platform is built to demonstrate real-time object detection at a throughput of 600 frames per second (fps) with a power of 1.34 W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"848-852"},"PeriodicalIF":4.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Area-Cost VLSI Architecture of Fault-Aware High-Reliability Triple-Mode Polar Decoder Chip Reconfiguring SC and SCL Decoding 重构SC和SCL译码的故障感知高可靠性三模极性译码芯片的低面积成本VLSI架构
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-16 DOI: 10.1109/TCSII.2025.3561211
Xin-Yu Shih;Dong-Lin Wu;Wei-Lun Chang
{"title":"Low-Area-Cost VLSI Architecture of Fault-Aware High-Reliability Triple-Mode Polar Decoder Chip Reconfiguring SC and SCL Decoding","authors":"Xin-Yu Shih;Dong-Lin Wu;Wei-Lun Chang","doi":"10.1109/TCSII.2025.3561211","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3561211","url":null,"abstract":"In this brief, we propose a low-area-cost fault-aware high-reliability Polar decoder VLSI architecture, resisting the unexpected faults randomly occurring in the internal storage elements. As for 2048-bit codeword length, our developed triple-mode chip can be well-reconfigured to perform SC decoding and SCL decoding with the list size (L) of 2 or 4. In the ASIC implementation with TSMC 40-nm multi-Vt CMOS technology, the total core area of our work only occupies 0.769 mm2 in chip layout, operating at a maximum frequency of 666.67 MHz. As compared with other state-of-the-arts, only our chip work can support high-reliability capability under 7.4% area overhead only.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"843-847"},"PeriodicalIF":4.0,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A New Variant of Turns-Ratio Independent Shoot-Through Current-Based Magnetically-Coupled Z-Source Inverter With Smooth DC-Link Voltage and Enhanced High-Gain 一种基于圆滑直流链路电压和增强高增益的磁耦合z源逆变器的新型匝比无关击穿电流
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-15 DOI: 10.1109/TCSII.2025.3560895
S. Konar;P. K. Gayen;S. S. Saha
{"title":"A New Variant of Turns-Ratio Independent Shoot-Through Current-Based Magnetically-Coupled Z-Source Inverter With Smooth DC-Link Voltage and Enhanced High-Gain","authors":"S. Konar;P. K. Gayen;S. S. Saha","doi":"10.1109/TCSII.2025.3560895","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3560895","url":null,"abstract":"In a magnetically coupled impedance-source (MCIS) inverter, the low value of shoot-through (ST) current is desired to reduce the ratings and losses of the power converter. In this regard, turns-ratio-independent ST current is an important requirement. Very few inverters (active-switched Y-source MCIS inverters) are found in a recent article, which claims turns-ratio-independent ST current as a figure of merit. But it is observed that the voltage gain of the turn-ratio-independent ST current-based configuration is lesser than the turns-ratio-dependent ST current-based inverters. Therefore, this brief proposes a new variant of an active-switched MCIS inverter with a smooth DC-link voltage, which simultaneously exhibits enhanced voltage gain and a turns ratio-independent ST current. The voltage gain of the suggested network is higher than that of the recent equivalent MCIS inverters for the same magnitude and duration of shoot-through current, i.e., the voltage gains per shoot-through current (combined figure of merit) are significantly improved in the proposed inverter. The switching device power (SDP) is also reduced in the suggested inverter. Its desired operation is experimentally verified.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"858-862"},"PeriodicalIF":4.0,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.62-pJ/Bit 60-GHz OOK Receiver With Supply Interference Tolerance for Short-Range Interconnects 面向短距离互连的0.62 pj /Bit 60ghz OOK接收机
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-15 DOI: 10.1109/TCSII.2025.3560305
Junhong Liu;Yi Wu;Guangyin Feng;Rongbin Liu;Shaoxian Li;Chuan Hu;Xiuyin Zhang
{"title":"A 0.62-pJ/Bit 60-GHz OOK Receiver With Supply Interference Tolerance for Short-Range Interconnects","authors":"Junhong Liu;Yi Wu;Guangyin Feng;Rongbin Liu;Shaoxian Li;Chuan Hu;Xiuyin Zhang","doi":"10.1109/TCSII.2025.3560305","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3560305","url":null,"abstract":"This brief presents an energy-efficient 60-GHz OOK receiver for massive short-range interconnects, addressing two key issues including interference in power distribution network and trade-off between sensitivity and energy efficiency. Variable gain low-noise amplifier with custom-designed bias-supply strategy is proposed to improve sensitivity and energy efficiency. Low-Q decoupling technique is proposed to improve supply interference tolerance, resulting in 2.6 times eye-opening in the eye diagram compared to the traditional one without low-Q decoupling. By co-designing the low-noise amplifier, envelope detector, and baseband amplifier, a prototype with proposed techniques was fabricated in a 65-nm LP CMOS process. Measurement results show that it achieves a maximum data rate of 16 Gbps with an energy efficiency of 0.62 pJ/bit and a sensitivity of -21.8 dBm, providing a high dynamic range, energy-efficient and interference robust solution for massive short-range interconnects.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"818-822"},"PeriodicalIF":4.0,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Application of Mean and Square Root Circuits for Stochastic Computing 随机计算中均方根电路的设计与应用
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-15 DOI: 10.1109/TCSII.2025.3560332
Shaowei Wang;Kai Shi;Yaohua Xu;Yi Wang;Yongqiang Zhang
{"title":"Design and Application of Mean and Square Root Circuits for Stochastic Computing","authors":"Shaowei Wang;Kai Shi;Yaohua Xu;Yi Wang;Yongqiang Zhang","doi":"10.1109/TCSII.2025.3560332","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3560332","url":null,"abstract":"Stochastic computing (SC) is an unconventional computing paradigm that represents values using probabilities. This representation enables simple logic gates to perform complex arithmetic operations. This brief proposes two low hardware-cost stochastic mean circuits for even and odd inputs, respectively, along with a high-accuracy stochastic square root circuit. The circuits are designed by considering correlation technique and achieve excellent performance. Experimental results demonstrate that the proposed mean circuits surpass previous counterparts in computing accuracy and hardware cost. For instance, the proposed 9-input mean circuit can achieve at least an 86.7% reduction in mean square error (MSE) and a 28.6% reduction in area. For the square root circuit, the proposed design achieves a reduction in MSE of at least 19.6%. The proposed circuits are further demonstrated with the Niblack binarization algorithm, which shows superior performance of accuracy.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"838-842"},"PeriodicalIF":4.0,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dual-Core Dual-Mode DCO for S/C-Band Radar 一种用于S/ c波段雷达的双核双模DCO
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-11 DOI: 10.1109/TCSII.2025.3559922
Cao Wan;Xiongyao Luo;Shuai Deng;Boyi Dong;Zhongzhiguang Lu;Yan’ge Wang;Shiquan Wang;Quan Xue;Yuanjin Zheng
{"title":"A Dual-Core Dual-Mode DCO for S/C-Band Radar","authors":"Cao Wan;Xiongyao Luo;Shuai Deng;Boyi Dong;Zhongzhiguang Lu;Yan’ge Wang;Shiquan Wang;Quan Xue;Yuanjin Zheng","doi":"10.1109/TCSII.2025.3559922","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3559922","url":null,"abstract":"This brief presents a dual-core, dual-mode digital-controlled oscillator (DCO) featuring a novel transformer-based resonator that minimizes parasitics in the switch connection lines and enhances the design flexibility of the resonator. Fabricated using 65-nm CMOS technology, the DCO occupies a die area of 0.76 mm2. Powered by a 1.2-V supply, it consumes between 6.6 and 10.8 mW of DC power. The DCO, utilizing a 127-bit thermometer-code switched varactor array (SVA), achieves a total bandwidth of 63.89%, spanning from 2.52 to 4.88 GHz. Over the entire frequency range, phase noise is measured between −116.14 and −119.34 dBc/Hz, resulting in a FoM ranging from −178.3 to −182.0 dBc/Hz, and a <inline-formula> <tex-math>$mathbf {FoM}_{mathbf {T}}$ </tex-math></inline-formula> varying from −194.4 to −198.1 dBc/Hz. This DCO is well-suited as the frequency source for S-band and C-band radar applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"808-812"},"PeriodicalIF":4.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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