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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-09-25 DOI: 10.1109/TCSII.2025.3607550
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引用次数: 0
Performance Bounds for a Maxima-Sampling Envelope Detector 最大采样包络检测器的性能边界
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-09-02 DOI: 10.1109/TCSII.2025.3605161
Swagat Bhattacharyya
{"title":"Performance Bounds for a Maxima-Sampling Envelope Detector","authors":"Swagat Bhattacharyya","doi":"10.1109/TCSII.2025.3605161","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3605161","url":null,"abstract":"Envelope detectors in automatic gain control systems must achieve both low tracking latency and low output ripple for feedback stability. Conventional non-sampled envelope detectors intrinsically trade off latency and ripple. Maxima-sampling envelope detectors (MSEDs), which demodulate by sampling signal peaks, circumvent this latency-ripple trade-off, enabling control loops that remain stable over several frequency decades. However, MSED nonlinearity causes an intricate, previously uncharacterized interplay between input spectral properties and performance. This work analytically derives and numerically verifies input-dependent performance bounds for MSEDs. By formulating practical “rules-of-thumb” for mixed-signal circuit designers, we pave the way for the broader adoption of MSEDs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1473-1477"},"PeriodicalIF":4.9,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-28 DOI: 10.1109/TCSII.2025.3600132
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引用次数: 0
IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-28 DOI: 10.1109/TCSII.2025.3600134
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引用次数: 0
Gradient-Based Optimization of MEMS Loudspeaker Equivalent Circuit Models via Automatic Differentiation 基于自动微分的MEMS扬声器等效电路模型梯度优化
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-28 DOI: 10.1109/TCSII.2025.3603686
Oliviero Massi;Alessandro Ilic Mezza;Riccardo Giampiccolo;Lelio Casale;Alberto Bernardini
{"title":"Gradient-Based Optimization of MEMS Loudspeaker Equivalent Circuit Models via Automatic Differentiation","authors":"Oliviero Massi;Alessandro Ilic Mezza;Riccardo Giampiccolo;Lelio Casale;Alberto Bernardini","doi":"10.1109/TCSII.2025.3603686","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3603686","url":null,"abstract":"Micro-Electro-Mechanical Systems (MEMS) loudspeakers represent a promising solution to meet the growing demand for compact, portable consumer audio devices with integrated sound reproduction capabilities. In this context, the availability of accurate and computationally efficient Lumped-Element Models (LEMs) can greatly accelerate MEMS loudspeaker design and support the development of digital signal processing techniques aimed at enhancing audio performance. In this work, we propose a framework based on Automatic Differentiation (AD) to optimize the parameters of differentiable LEMs in a fully data-driven manner using standard gradient-based optimization methods. Specifically, we focus on tuning the parameters of an ad hoc linear equivalent circuit model for a commercially available MEMS loudspeaker intended for free-field applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1468-1472"},"PeriodicalIF":4.9,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal Control for Power System Signal Processing: A Joint Edge Collaboration and Relay Assistance Framework 电力系统信号处理的最优控制：一个联合边缘协作和继电器辅助框架
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-21 DOI: 10.1109/TCSII.2025.3601095
Mingrui Zhang;Xuguang Hu;Jingyu Wang
{"title":"Optimal Control for Power System Signal Processing: A Joint Edge Collaboration and Relay Assistance Framework","authors":"Mingrui Zhang;Xuguang Hu;Jingyu Wang","doi":"10.1109/TCSII.2025.3601095","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3601095","url":null,"abstract":"This brief presents a signal processing system and its optimize control strategy for power systems. The proposed approach addresses the challenges of increased computational energy consumption and unbalanced processing task allocation. Firstly, a joint edge collaboration and relay assistance signal processing system architecture for power systems is proposed to address the issue of uneven signal processing task allocation. Secondly, a five-slot signal transmission architecture based on non-orthogonal multiple access technology is proposed, along with a method for representing signal processing costs, which solves the problem of signal processing cost quantification. Thirdly, a collaboration assistance computing and resource allocation algorithm is proposed to minimize signal processing costs. Finally, the proposed signal processing system is tested on a power system in China. The results demonstrate that it effectively mitigates the uneven resource allocation issue while significantly reducing signal processing costs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1463-1467"},"PeriodicalIF":4.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A State-Switching Digital LDO for PWM Thermo-Optic Tuning in Silicon Photonics 一种用于硅光子学中PWM热光调谐的状态切换数字LDO
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-14 DOI: 10.1109/TCSII.2025.3598759
Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan
{"title":"A State-Switching Digital LDO for PWM Thermo-Optic Tuning in Silicon Photonics","authors":"Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan","doi":"10.1109/TCSII.2025.3598759","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3598759","url":null,"abstract":"Pulse-width-modulated (PWM) thermo-optic tuning in silicon photonics calls for a power supply featuring high-speed PWM power output with short settling time, high efficiency, and a compact size. However, the transient response of the traditional digital low-dropout regulators (DLDOs) is limited by the closed-loop response, which makes it difficult to meet the speed requirements of the PWM power output. This brief presents a State-Switching DLDO (SS-DLDO), specially optimized for PWM thermo-optic tuning. Two state selectors, controlled by a PWM signal, are inserted into the SS-DLDO structure to control the connections and operational states of the DLDO asynchronously. This enables the speed of PWM tuning to be decoupled from the feedback loop of the DLDO. The proposed design is fabricated in a 65nm CMOS process with an active area of 0.00634 mm2. Measurement results show that the rising-edge settling time and falling-edge settling time of the PWM power output are 16.3 ns and 14 ns, respectively, which effectively reduces the limit of the edge settling time to the achievable PWM duty cycle range. Under a 2 MHz PWM frequency, this design can achieve PWM duty cycles ranging from 5.92% to 97.2%, corresponding to output power ranging from 1.47 mW to 24.12 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1458-1462"},"PeriodicalIF":4.9,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145134918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault Tolerant Control of Switched Affine Systems With Application to Boost Converter: The Transition-Dependent Bumpless Transfer Approach 应用于升压变换器的切换仿射系统容错控制：过渡相关的无颠簸传输方法
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-07 DOI: 10.1109/TCSII.2025.3596833
Fang Liao;Yanzheng Zhu;Rongni Yang;Jian Zhang;Donghua Zhou
{"title":"Fault Tolerant Control of Switched Affine Systems With Application to Boost Converter: The Transition-Dependent Bumpless Transfer Approach","authors":"Fang Liao;Yanzheng Zhu;Rongni Yang;Jian Zhang;Donghua Zhou","doi":"10.1109/TCSII.2025.3596833","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3596833","url":null,"abstract":"The <inline-formula> <tex-math>${mathcal {L}}_{infty }$ </tex-math></inline-formula> bumpless transfer fault-tolerant control problem is addressed for continuous-time switched affine systems with actuator faults and bounded disturbances. A novel piecewise transition-dependent fault-tolerant controller is designed, by enforcing the specified bumps limitation constraints, sufficient conditions for the existence of the fault-tolerant controller are derived satisfying a new average dwell time constraint, which guarantees the practical stability of the closed-loop system and the bumpless transfer as switching and faults occur. Finally, both practicability and validity of the developed methods are illustrated through a case study of DC-DC boost converter.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1328-1332"},"PeriodicalIF":4.9,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Compact Size CMOS VCO Using Dual-Primary Transformer With Dual-Core for Wide Tuning-Range 采用双芯双初级变压器实现宽调谐范围的紧凑CMOS压控振荡器设计
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-05 DOI: 10.1109/TCSII.2025.3595599
Joonseok Park;Jaeyong Lee;Changkun Park
{"title":"Design of Compact Size CMOS VCO Using Dual-Primary Transformer With Dual-Core for Wide Tuning-Range","authors":"Joonseok Park;Jaeyong Lee;Changkun Park","doi":"10.1109/TCSII.2025.3595599","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3595599","url":null,"abstract":"In this brief, we design a CMOS-based dual-core voltage-controlled oscillator (VCO) to extend the frequency tuning range. To mitigate the increase in integrated circuit area caused by the LC tanks required for dual-core operation, a dual-primary transformer structure is proposed. The proposed transformer consists of two primary windings and one secondary winding. The primary winding corresponding to the core supporting lower frequencies is designed with two turns to secure sufficient inductance. Thanks to the proposed dual-primary transformer, a compact size is achieved despite the dual-core VCO configuration. To validate the effectiveness of the proposed structure, the VCO is fabricated using a 65-nm RFCMOS process. The fabricated VCO core, including the output buffer, occupies an area of <inline-formula> <tex-math>$0.39times 0.11$ </tex-math></inline-formula> mm2. The measured frequency tuning range spans from 17.8 GHz to 26.9 GHz, with phase noise at 1-MHz offset and output power measured to be lower than −89.6 dBc/Hz and higher than −15.3 dBm, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1213-1217"},"PeriodicalIF":4.9,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Voltage Charge Pump With Pseudo-Continuous Output Regulation Using Dynamic Clock Voltage Scaling 基于动态时钟电压缩放的伪连续输出调节高压电荷泵
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-08-01 DOI: 10.1109/TCSII.2025.3594876
Ziliang Zhou;Min Tan
{"title":"A High-Voltage Charge Pump With Pseudo-Continuous Output Regulation Using Dynamic Clock Voltage Scaling","authors":"Ziliang Zhou;Min Tan","doi":"10.1109/TCSII.2025.3594876","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594876","url":null,"abstract":"This brief presents a high-voltage charge pump with pseudo-continuous regulation using dynamic clock voltage scaling. We propose a small-signal model of the charge pump to facilitate co-simulation of the linear amplifier and the capacitive switching converter, and it shows good agreement with the time-domain ac simulation results. A novel lead compensation is proposed in the amplifier using current-mirror Miller compensation, which ensures loop stability without a large load capacitor at the charge pump’s output. The proposed regulated charge pump has been implemented in a 65-nm CMOS process, and the chip area is <inline-formula> <tex-math>$280~{mu }$ </tex-math></inline-formula>m <inline-formula> <tex-math>${times } 300~{mu }$ </tex-math></inline-formula>m. Operating at a 2.5-V supply, it maintains < 21 mV ripple voltage at 9.6 V output for different load currents and pumping frequencies. The undershoot for the load transient current of 0 to <inline-formula> <tex-math>$50~{mu }$ </tex-math></inline-formula>A with a 160-ns edge time is 58 mV with around <inline-formula> <tex-math>$0.8~{mu }$ </tex-math></inline-formula>s recovery time.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1323-1327"},"PeriodicalIF":4.9,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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