IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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Preassigned-Time Sliding-Mode Control of Chaotic Memristive Neural Networks With Time-Varying Delays 时变时滞混沌记忆神经网络的预分配时间滑模控制
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-10 DOI: 10.1109/TCSII.2025.3559558
Guoqing Gao;Hailong Ge;Gaohua Wang;Leimin Wang
{"title":"Preassigned-Time Sliding-Mode Control of Chaotic Memristive Neural Networks With Time-Varying Delays","authors":"Guoqing Gao;Hailong Ge;Gaohua Wang;Leimin Wang","doi":"10.1109/TCSII.2025.3559558","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3559558","url":null,"abstract":"Preassigned-time (PASST) control of memrisitive neural networks has been a hot research point recently. Different from the finite-time control with stable time dependent on the initial condition of the system, this brief studies the PASST control, and the stable time of which is uncorrelated with the initial condition and can be set in advance. For a class of chaotic memristive neural networks with time delays, a sliding-mode based approach is designed to realize the PASST stability. Different from the finite-time stability, the upper bound of stable time is not related to or constricted by the initial condition, and it can be arbitrarily defined for practical requirement. Moreover, as the special cases, the exponential stability and fixed-time stability are also presented via the same framework of the sliding-mode based approach. Finally, a chaotic numerical example with several comparative cases are given to verify the validity of the control method of PASST stability results.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"823-827"},"PeriodicalIF":4.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Virtual-Synchronizer-Based Current Sharing Scheme in m-Phase Resonant DC-DC Converters System 基于虚拟同步器的m相谐振DC-DC变换器系统电流共享方案
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-09 DOI: 10.1109/TCSII.2025.3559142
Kangli Liu;Tianao Xiao;Peng Chen;Wenzhe Chen;Jianfeng Zhao
{"title":"Virtual-Synchronizer-Based Current Sharing Scheme in m-Phase Resonant DC-DC Converters System","authors":"Kangli Liu;Tianao Xiao;Peng Chen;Wenzhe Chen;Jianfeng Zhao","doi":"10.1109/TCSII.2025.3559142","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3559142","url":null,"abstract":"The m-phase LLC resonant converter serves as an effective solution for reducing current stress and enabling high-power DC-DC conversion applications. However, variations in component parameters within the resonant tanks can lead to discrepancies in voltage gain, causing imbalanced output currents and thereby compromising the safe and reliable operation of the system. This brief delves into the underlying mechanism of current imbalance and elucidates the dynamic process through state-plane trajectory analysis. Consequently, a virtual-synchronizer based online current sharing scheme is proposed for m-phase resonant converters, which facilitates rapid online current balancing and ensures excellent synchronization performance. Moreover, it eliminates the need to designate a master phase, thereby enhancing the control flexibility, and the addition or removal of any phase does not disrupt the control process. The proposed method achieves synchronization and current sharing by constructing a virtual phase, without requiring additional hardware such as circuits and sensors. Results validate the effectiveness of the proposed method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"853-857"},"PeriodicalIF":4.0,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Offset-Tolerant Body-Biased Sense Amplifier With Rise-Time Control Technique for SRAM 基于上升时间控制技术的SRAM容偏体偏感放大器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-07 DOI: 10.1109/TCSII.2025.3558562
Jaehwan Kim;Mingu Han;Bayartulga Ishdorj;Taehui Na
{"title":"Offset-Tolerant Body-Biased Sense Amplifier With Rise-Time Control Technique for SRAM","authors":"Jaehwan Kim;Mingu Han;Bayartulga Ishdorj;Taehui Na","doi":"10.1109/TCSII.2025.3558562","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3558562","url":null,"abstract":"In this brief, we propose an Offset-Tolerant Body-biased sense amplifier (OTB-SA) with a rise-time <inline-formula> <tex-math>$(T_{mathrm { RISE}})$ </tex-math></inline-formula> control technique to address the sensing failure issue that occurs when the input voltage difference <inline-formula> <tex-math>$({Delta }V_{mathrm { BL}})$ </tex-math></inline-formula> of a latch-type SA is smaller than the offset voltage <inline-formula> <tex-math>$(V_{mathrm { OS}})$ </tex-math></inline-formula>. The OTB-SA with <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> leverages body biasing and <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> control to enhance the differential signal injection (DSI) effect, thereby reducing both <inline-formula> <tex-math>$V_{mathrm { OS}}$ </tex-math></inline-formula> and energy consumption. Post-layout HSPICE simulation results using a 28 nm technology model indicate that, when target <inline-formula> <tex-math>$V_{mathrm { OS}}$ </tex-math></inline-formula> standard deviation <inline-formula> <tex-math>$({sigma }_{mathrm { OS}})$ </tex-math></inline-formula> is 5 mV, the OTB-SA with <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> achieves a 49.6% reduction in area and a 60.1% decrease in energy consumption compared to a voltage-latched SA (VLSA) without <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula>. Moreover, compared to previous SAs, the OTB-SA with <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> showed up to 69.1% area reduction and up to 91.2% energy consumption reduction. Measurements from a 28 nm test chip confirmed that <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> control is effective, showing a trend where <inline-formula> <tex-math>${sigma }_{mathrm { OS}}$ </tex-math></inline-formula> decreases as <inline-formula> <tex-math>$T_{mathrm { RISE}}$ </tex-math></inline-formula> increases for OTB-SA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"773-777"},"PeriodicalIF":4.0,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS 用于光直接检测应用的4×106 Gb/s混合信号PAM-4自适应线性补偿28纳米CMOS收发器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-04 DOI: 10.1109/TCSII.2025.3557793
Boyang Zhang;Tianchen Ye;Zhifei Wang;Xin Liu;Tianyuan Zhong;Ruixu Wang;Weixin Gai
{"title":"A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS","authors":"Boyang Zhang;Tianchen Ye;Zhifei Wang;Xin Liu;Tianyuan Zhong;Ruixu Wang;Weixin Gai","doi":"10.1109/TCSII.2025.3557793","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3557793","url":null,"abstract":"Optical transmission has been widely employed in data-centers, but the complex impairments including the non-linearity induced by the laser modulator degrade the signal. Conventional optical modules use DSP-based transceivers to address these impairments, but they rely on advanced technology, consuming much power and area as well. A 4x106Gb/s mixed-signal PAM-4 transceivers fabricated in 28nm CMOS are proposed in this brief to reduce cost, area and power consumption. The transceiver supports adaptive linearity compensation with analog PAM4 level pre-distortion technique in TX. 4-tap FFE and 7-tap DFE including 4 floating taps are implemented in RX to take DFE’s advantage of not amplifying noise thanks to the mixed-signal structure. The transceiver achieves an optical sensitivity of -8.7dBm, which is 0.7dBm better than the DSP-based equalization methods under the same optical test environment. The energy efficiency and single-channel area are 4.42pJ/bit and 0.28mm2 respectively, both of which are better than reported 100Gb/s counterparts.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"728-732"},"PeriodicalIF":4.0,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Self-Learning Tracking Control for Switched Systems: A Triggered-Learning Model Predictive Control Method 切换系统的高效自学习跟踪控制:一种触发学习模型预测控制方法
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-03 DOI: 10.1109/TCSII.2025.3557419
Tianxiang Dong;Yiwen Qi;Shitong Guo
{"title":"Efficient Self-Learning Tracking Control for Switched Systems: A Triggered-Learning Model Predictive Control Method","authors":"Tianxiang Dong;Yiwen Qi;Shitong Guo","doi":"10.1109/TCSII.2025.3557419","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3557419","url":null,"abstract":"Existing model predictive control (MPC) methods lack online learning capability in complex environments. Reinforcement learning (RL) requires a lot of data and computing resources to obtain optimal control. This brief uses efficient self-learning to solve this problem. “Efficient” refers to the use of triggered-learning mechanism (TLM) to manage computing resources on demand. This brief proposes a triggered-learning model predictive control (TL-MPC) method for switched systems. The proposed TL-MPC endows MPC with learning capabilities through the TLM. TLM includes a Deep Deterministic Policy Gradient (DDPG) based control incremental self-learning tuning strategy and a performance-driven event-triggering strategy. The first strategy is to give the MPC controller a control increment to optimize control effect. The second strategy is to realize the on-demand learning and reduce computational resources by comparing two cost functions that characterize the system performance. In addition, the stability of switched systems under TL-MPC is analyzed using the Lyapunov function and the average dwell time technique. Finally, the effectiveness of the proposed method is verified by simulation.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"748-752"},"PeriodicalIF":4.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-31 DOI: 10.1109/TCSII.2025.3550045
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3550045","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550045","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945817","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II:快报简报出版信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-31 DOI: 10.1109/TCSII.2025.3550043
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3550043","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550043","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945880","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II:快报简报出版信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-29 DOI: 10.1109/TCSII.2025.3570138
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3570138","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3570138","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017591","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-29 DOI: 10.1109/TCSII.2025.3570140
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3570140","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3570140","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017589","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Bypass Architecture for RB-COT Buck Converters 一种新的RB-COT降压变换器旁路结构
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-28 DOI: 10.1109/TCSII.2025.3555695
Francesco Gabriele;Samuele Gisonno;Filippo Fiori;Davide Lena;Salvatore Rosario Musumeci;Fabio Pareschi;Gianluca Setti
{"title":"A Novel Bypass Architecture for RB-COT Buck Converters","authors":"Francesco Gabriele;Samuele Gisonno;Filippo Fiori;Davide Lena;Salvatore Rosario Musumeci;Fabio Pareschi;Gianluca Setti","doi":"10.1109/TCSII.2025.3555695","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3555695","url":null,"abstract":"In this brief we propose a novel ByPass (BP) circuit that overcomes the voltage regulation limit in the Ripple Based Constant On-Time (RB-COT) Buck converters due to intrinsic presence of a minimum achievable OFF time. The BP stage is conceived to be embedded in the RB-COT modulator located within the converter feedback loop, and only intervening when the minimum OFF time condition is reached. The latter implies that the COT modulator saturates, and consequently, the output voltage regulation of the converter is no longer guaranteed. Conversely, the BP stage does not affect the behavior of the circuit when it operates in normal regulating condition. The effectiveness of the proposed BP stage is confirmed through both transistor-level simulation results derived from the SPICE platform and experimental measurements on a integrated circuit prototype implemented in a 0.18 um Bipolar-CMOS-DMOS process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"793-797"},"PeriodicalIF":4.0,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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