发布求助
文献互助 智能选刊 最新文献

IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

筛选
英文 中文
Automatic Design of Multi-Fold Hyperchaotic System Using Parallel Fractal Algorithm 基于并行分形算法的多重超混沌系统自动设计
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-31 DOI: 10.1109/TCSII.2025.3594405
Ning Wang;Mengkai Cui;Muhammad Marwan;Yan Yang;Han Bao;Herbert Ho-Ching Iu;Quan Xu
{"title":"Automatic Design of Multi-Fold Hyperchaotic System Using Parallel Fractal Algorithm","authors":"Ning Wang;Mengkai Cui;Muhammad Marwan;Yan Yang;Han Bao;Herbert Ho-Ching Iu;Quan Xu","doi":"10.1109/TCSII.2025.3594405","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594405","url":null,"abstract":"This brief presents a simple one-step parallel fractal algorithm for automatic design of multi-fold hyperchaotic system from scroll/wing-type seed system. It is shown that the desired number of folds can be generated via a simple parametric control. Two representative application cases of four-dimensional and six-dimensional multi-fold no-equilibrium hyperchaotic systems are presented. For a double-wing seed attractor, the method will generate <inline-formula> <tex-math>$2^{m}$ </tex-math></inline-formula> wings under each pair of m-fold transformation. In contrast with existing designs, the proposed algorithm is automatic and has wide applicability in generating various numbers of folds in multiple directions. Simulation studies and hardware implementations are conducted to verify the feasibility of the proposed algorithm.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1313-1317"},"PeriodicalIF":4.9,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-31 DOI: 10.1109/TCSII.2025.3589810
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3589810","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3589810","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106323","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces 一种2.5 ~ 48gb /s 16.6 ns开埠时间NRZ/PAM4脉冲快速开/关波特率话单技术
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-31 DOI: 10.1109/TCSII.2025.3594475
Jihee Kim;Yunhee Lee;Hyun-Seok Choi;Yoona Lee;Sanghee Lee;Woo-Seok Choi
{"title":"A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces","authors":"Jihee Kim;Yunhee Lee;Hyun-Seok Choi;Yoona Lee;Sanghee Lee;Woo-Seok Choi","doi":"10.1109/TCSII.2025.3594475","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594475","url":null,"abstract":"This brief presents an NRZ/PAM4 rapid-on/off baud-rate clock and data recovery (CDR) for mobile interfaces, featuring power-efficient bandwidth scaling. To minimize power overhead due to large turn-on time, a pulse-based rapid clock recovery method is proposed. This method estimates and immediately compensates for initial phase error based on a pre-trained look-up table, significantly reducing the CDR’s turn-on time. In addition, a background PAM4 eye-climbing algorithm (ECA) addresses the sub-optimal lock point issue of conventional baud-rate phase detectors by adjusting the lock point to maximize the vertical eye margin (VEM). The prototype receiver fabricated in a 28 nm CMOS supports data rates from 2.5 to 48Gb/s, accommodating both legacy and next-generation mobile interfaces. It achieves an energy efficiency of 1.43 pJ/b at 48 Gb/s while demonstrating a fast turn-on time of 16.6 ns, enabling superior energy efficiency across various effective data rates. Moreover, the PAM4 ECA increases VEM of the PAM4 middle eye by 18 mV, ensuring error-free operation.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1193-1197"},"PeriodicalIF":4.9,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.54 Gbps, 1.22 pJ/Bit, IR-UWB Transmitter With a Power-Gating Technique 基于功率门控技术的2.54 Gbps， 1.22 pJ/Bit IR-UWB发射机
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-30 DOI: 10.1109/TCSII.2025.3594199
Kyoungseok Song;Donggun Lee;Geunhaeng Lee;Yonghui Li;Tae Wook Kim
{"title":"A 2.54 Gbps, 1.22 pJ/Bit, IR-UWB Transmitter With a Power-Gating Technique","authors":"Kyoungseok Song;Donggun Lee;Geunhaeng Lee;Yonghui Li;Tae Wook Kim","doi":"10.1109/TCSII.2025.3594199","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594199","url":null,"abstract":"This brief presents an impulse radio-ultrawideband (IR-UWB) transmitter (Tx) that achieves high energy efficiency and data rate through a power-gating (PG) technique and hybrid modulation scheme. PG minimizes static power consumption by activating the digitally controlled oscillator (DCO) only during transmission. A hybrid modulation scheme combines frequency- shift keying (FSK) with digitalized multi pulse position modulation (D-MPPM) and pulse width modulation (PWM) to increase modulation order. Implemented in 6.5-8.5 GHz, the proposed PG-DCO Tx achieves a data rate of 2.54 Gbps with an energy efficiency of 1.22 pJ/bit, approaching the 1 pJ/bit energy-efficiency barrier for UWB transmitters.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1208-1212"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving −80.7dBc Fractional Spur 一种6.8-14.4GHz免校准分数阶n- ro混频合成器，实现−80.7dBc分数阶杂散
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-30 DOI: 10.1109/TCSII.2025.3594027
Zonglin Ye;Hongyang Zhang;Yuxuan Sun;Xinlin Geng;Qian Xie;Shiheng Yang;Zheng Wang
{"title":"A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving −80.7dBc Fractional Spur","authors":"Zonglin Ye;Hongyang Zhang;Yuxuan Sun;Xinlin Geng;Qian Xie;Shiheng Yang;Zheng Wang","doi":"10.1109/TCSII.2025.3594027","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3594027","url":null,"abstract":"A calibration-free fractional-N synthesizer is presented with octave tuning capability and low fractional spurs, which is fabricated using a 65-nm bulk CMOS process. The synthesizer is based on the harmonic-mixing (HM) architecture, featuring a unity gain for the quantization error transfer to achieve low fractional spur without any calibration. To support octave-tuning, a ring-oscilator(RO)-based first stage is utilized to save area with negligible jitter deterioration. Moreover, a variable sub-sampling ratio technique is employed to relax the tuning range requirement for the RO. The measurements demonstrate an octave-tuning synthesizer with −80.7 dBc fractional spur, 71.7% tuning range and −254.6 dB FoMT.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1183-1187"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 91.7% Peak-Efficiency 48V-to-1V Pseudo Two-Stage Two-Phase Hybrid Buck Converter 91.7%峰值效率48v - 1v伪两级两相混合降压变换器
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-30 DOI: 10.1109/TCSII.2025.3593898
Young-Ju Oh;Chan-Ho Lee;Jeong-Hun Kim;Hyeonho Park;Dowon Jeong;Sung-Wan Hong
{"title":"A 91.7% Peak-Efficiency 48V-to-1V Pseudo Two-Stage Two-Phase Hybrid Buck Converter","authors":"Young-Ju Oh;Chan-Ho Lee;Jeong-Hun Kim;Hyeonho Park;Dowon Jeong;Sung-Wan Hong","doi":"10.1109/TCSII.2025.3593898","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593898","url":null,"abstract":"This brief proposes a pseudo two-stage two-phase (P2S-2P) buck converter that enhances power efficiency by reducing current in the high-voltage (HV) domain, which has large parasitic components. In contrast, the low-voltage (LV) domain, which has small parasitic components, supplies the majority of the output current (IO) through two inductors that automatically balance their currents. The proposed converter achieves a peak efficiency of 91.7% at an input voltage (VIN) of 48V, an output voltage (VO) of 1V, and the IO of 1.5A. The chip was fabricated using a 180-nm BCD process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1318-1322"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-30 DOI: 10.1109/TCSII.2025.3589808
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3589808","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3589808","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11104808","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bifurcation Analysis of Slow-Scale Oscillation in SIDO Boost PFC Converter Using Time-Frequency Characteristic Representation Method 基于时频特性表示法的SIDO升压PFC变换器慢尺度振荡分岔分析
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-29 DOI: 10.1109/TCSII.2025.3593639
Xiao Yang;Hao Zhang;Guohua Zhou
{"title":"Bifurcation Analysis of Slow-Scale Oscillation in SIDO Boost PFC Converter Using Time-Frequency Characteristic Representation Method","authors":"Xiao Yang;Hao Zhang;Guohua Zhou","doi":"10.1109/TCSII.2025.3593639","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593639","url":null,"abstract":"Besides line frequency excitation, strong nonlinear crossing effect amongst three input/output ports exists in single-inductor dual-output (SIDO) boost power factor correction (PFC) converters, which leads to the occurrence of complex behaviors including slow-scale oscillation. In this brief, a nonlinear averaged model is derived to describe the nonlinear time-periodic coupling (NTPC) effect of the SIDO PFC converter, and importantly time-frequency characteristic representation method is proposed to obtain the analytical expression of periodic equilibrium solutions. Furthermore, two types of slow-scale oscillations are identified with the help of the loci movement of Floquet multipliers. It is shown that period-doubling bifurcation and Hopf bifurcation are responsible for type I alternating peak oscillation and type II discontinuous trajectory oscillation, respectively. Especially, Hopf bifurcation results in one incommensurable frequency component with respect to the line frequency, which explains the reason why the system enters one quasi-periodic orbit. Finally, these experimental results are given to verify the theoretical analysis. These above results are beneficial to guide circuit optimal design.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1308-1312"},"PeriodicalIF":4.9,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Ka-Band Fully Integrated CMOS 1T3R Transceiver for Monopulse Radar Applications 用于单脉冲雷达的ka波段全集成CMOS 1T3R收发器
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-28 DOI: 10.1109/TCSII.2025.3593382
Peng Gu;Enqi Zheng;Xiaofei Liao;Hengzhi Wan;Chenyu Xu;Pengfei Diao;Huiqi Liu;Dixian Zhao
{"title":"A Ka-Band Fully Integrated CMOS 1T3R Transceiver for Monopulse Radar Applications","authors":"Peng Gu;Enqi Zheng;Xiaofei Liao;Hengzhi Wan;Chenyu Xu;Pengfei Diao;Huiqi Liu;Dixian Zhao","doi":"10.1109/TCSII.2025.3593382","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593382","url":null,"abstract":"Emerging low-altitude airspace economy has driven the development of high-resolution wireless sensors. Dedicated for the Ka-band monopulse radar applications, the design of a highly integrated 1T3R transceiver is detailed in this brief. The heterodyne transceiver incorporates full radio frequency (RF), intermediate frequency (IF) and local oscillator (LO) building blocks, supporting complete monopulse detection in azimuth and elevation. The calibration mode is introduced to enable system-level instant calibrations for enhanced detection accuracy. Dual injection style of the LO source facilitates the cascade of multiple chips for large-scale sensing systems. Fabricated in 65-nm CMOS technology and packaged with the wafer-level chip-scale packaging, the transceiver achieves the peak RX/TX gain of 18.4/33.2 dB across 32–36 GHz, with a minimum RX NF of 5.7 dB and peak saturated TX power of 15.6 dBm. The high integration level and flexible configuration of the transceiver make it suitable for Ka-band monopulse radar applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1178-1182"},"PeriodicalIF":4.9,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A New Two-Tiered ECC Configuration Method for Cluster Error Correction in HBM Architecture HBM体系结构中两层ECC纠错新方法
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-28 DOI: 10.1109/TCSII.2025.3593226
Jaeil Lim;Jaewon Chung;Donghun Jeong;Daegeun Jee;Euicheol Lim
{"title":"A New Two-Tiered ECC Configuration Method for Cluster Error Correction in HBM Architecture","authors":"Jaeil Lim;Jaewon Chung;Donghun Jeong;Daegeun Jee;Euicheol Lim","doi":"10.1109/TCSII.2025.3593226","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3593226","url":null,"abstract":"HBM (high bandwidth memory) is an emerging technology for high performance computing, but it has a different structure from traditional memory, and thus a new solution is needed. In this brief, we present an ECC (error correcting code) configuration method for SWD (sub-wordline driver) fault correction in the two-tiered ECC structure of HBM. Existing method does not have the correction capability to cover the entire range of a SWD cluster fault. In this brief, the SWD fault correction capability of the proposed method is presented through mathematical inference. And the simulation results also showed the same correction capability as the inference. And it shows the result of reducing the overhead and latency of encoder and decoder hardware when compared to the existing method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1293-1297"},"PeriodicalIF":4.9,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信