IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第2页

A 3.2 mW 2.35-dB NF Noise-Cancelling Balun-LNA Using Current-Reuse-Enhanced Local-Feedback for Improved Power Efficiency 基于电流复用增强局部反馈的3.2 mW 2.35 db NF balon - lna降噪电路

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-04-01 DOI: 10.1109/TCSII.2026.3679788

Seungyeon Kim;Donggu Lee;Sukju Yun;Kuduck Kwon

{"title":"A 3.2 mW 2.35-dB NF Noise-Cancelling Balun-LNA Using Current-Reuse-Enhanced Local-Feedback for Improved Power Efficiency","authors":"Seungyeon Kim;Donggu Lee;Sukju Yun;Kuduck Kwon","doi":"10.1109/TCSII.2026.3679788","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3679788","url":null,"abstract":"In this article, a 0.1–1.2 GHz broadband balun low-noise amplifier (LNA) achieving low-power operation and balanced output loads using a current-reuse-enhanced local-feedback architecture is presented. The proposed topology employs a current-reuse inverter-based common-source (CS) stage to increase the effective transconductance without additional DC current, thereby strengthening the loop gain of the local-feedback common-gate (CG) stage and relaxing the intrinsic CG <inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula> requirement for wideband input matching. As a result, an improved gain–noise–power trade-off is achieved while maintaining balanced differential output. Fabricated in a 65-nm CMOS process, the proposed balun-LNA achieves a minimum noise figure of 2.35 dB, a maximum voltage gain of 28.9 dB, and S <inline-formula> <tex-math>${}_{11} lt -10$ </tex-math></inline-formula> dB over a 1.2 GHz bandwidth. The measured peak IIP3 and OIP3 are –5.6 dBm and 23.3 dBm, respectively. The LNA consumes 3.2 mA from a 1 V supply and occupies an active area of 0.027 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"568-572"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An E-Band Blocker-Tolerant Receiver in 0.18-μm SiGe BiCMOS 0.18 μm SiGe BiCMOS的e波段容错接收机

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-19 DOI: 10.1109/TCSII.2026.3675571

Erez Zolkov;Emanuel Cohen

引用次数: 0

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 DOI: 10.1109/TCSII.2026.3684869

引用次数: 0

Frequency-Dimension Virtual Array Expansion in MIMO Radars for Improved Angular Resolution MIMO雷达中提高角分辨率的频维虚拟阵列扩展

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-04-03 DOI: 10.1109/TCSII.2026.3680724

Ruilin Liao;Haoran Wang;Jingzhi Zhang;Yue Song;Hongyang An;Huihua Liu;Kai Kang

{"title":"Frequency-Dimension Virtual Array Expansion in MIMO Radars for Improved Angular Resolution","authors":"Ruilin Liao;Haoran Wang;Jingzhi Zhang;Yue Song;Hongyang An;Huihua Liu;Kai Kang","doi":"10.1109/TCSII.2026.3680724","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3680724","url":null,"abstract":"Poor angular resolution is a major problem in modern radar systems. The multiple input and multiple output (MIMO) radar uses <inline-formula> <tex-math>$bf N$ </tex-math></inline-formula> transmitters and <inline-formula> <tex-math>$bf N$ </tex-math></inline-formula> receivers to equivalently form <inline-formula> <tex-math>$bf N^{2}$ </tex-math></inline-formula> virtual elements to expand the aperture. However, this level of virtual array expansion is not enough to further improve the angular resolution and reduce the number of transceiver elements. In this work, we use an additional dimension to further expand the virtual array. By stimulating the array with <inline-formula> <tex-math>$bf k$ </tex-math></inline-formula> different frequencies, we can expand the virtual elements to <inline-formula> <tex-math>$bf N^{2k}$ </tex-math></inline-formula> in addition to MIMO operation. The simulation results show that with 4 transmitters and 4 receivers, we can achieve 0.35° angular resolution when exciting the array with 1-GHz and 4-GHz signals. Furthermore, we set up a proof-of-concept frequency-modulated continuous-wave (FMCW) radar experiment with 1 transmitter and 4 receivers to achieve 12.3° angular resolution. Our proposed virtual array expansion technique can significantly reduce the number of transceivers and antenna elements in MIMO radars and improve angular resolution.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"538-542"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CORDIC-Based Computation of Arcsine/Arccosine Integrated With Prefix Binary Tree Mapping 基于cordic的arcsin / arccos与前缀二叉树映射集成计算

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-23 DOI: 10.1109/TCSII.2026.3676718

Chengyang Han;Jifeng Luo;Qianjian Xing;Feng Yu

{"title":"CORDIC-Based Computation of Arcsine/Arccosine Integrated With Prefix Binary Tree Mapping","authors":"Chengyang Han;Jifeng Luo;Qianjian Xing;Feng Yu","doi":"10.1109/TCSII.2026.3676718","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3676718","url":null,"abstract":"The hardware-based computation of arcsine and arccosine functions is predominantly realized through the vectoring-mode CORDIC algorithm. However, existing approaches necessitate computationally intensive calculations or suffer from approximation-induced errors. This brief proposes a hybrid architecture that replaces the sequentially dependent early iterations with an efficient table-based mapping. By reinterpreting the initial convergence process as a non-uniform domain segmentation problem, the proposed Prefix Binary Tree Mapping (PBTM) achieves algorithmic look-ahead through direct indexing of pre-computed intermediate states, thereby bypassing the coarse-grained decision stages. Experimental results demonstrate that by substituting the early iterations with precise state mapping, the PBTM-CORDIC method suppresses approximate gain error below the quantization noise floor and reduces the worst-case error by 76.02%. Furthermore, hardware implementation confirms a 22.77% reduction in area and a 56.08% enhancement in energy efficiency compared to state-of-the-art pipelined designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"593-597"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Phase Switching Fractional Output Divider With Split-DTC-Based Nonlinear Calibration 基于分路dtc非线性定标的相开关分数输出分压器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-26 DOI: 10.1109/TCSII.2026.3677836

Xin Hong;Ang Hu;Shengxiang Liu;Dongsheng Liu;Deng Luo;Xuecheng Zou;Ke Sun

引用次数: 0

A 28-nm 4.87 TOPS/W 3-D Sparse Convolution Accelerator for Voxel-Based Point Cloud Neural Networks in Edge Applications 基于体素的点云神经网络的28纳米4.87 TOPS/W三维稀疏卷积加速器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-11 DOI: 10.1109/TCSII.2026.3673120

Zekun Zhou;Shengjie Wang;Yuchen Tan;Chunyi Song;Zhiwei Xu

{"title":"A 28-nm 4.87 TOPS/W 3-D Sparse Convolution Accelerator for Voxel-Based Point Cloud Neural Networks in Edge Applications","authors":"Zekun Zhou;Shengjie Wang;Yuchen Tan;Chunyi Song;Zhiwei Xu","doi":"10.1109/TCSII.2026.3673120","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3673120","url":null,"abstract":"This brief presents a 28 nm 3D sparse convolution accelerator for voxel-based point cloud neural networks targeting edge perception applications. To efficiently handle the sparsity and irregularity of point clouds while minimizing power consumption and chip area, we introduce a unified mapping generator that supports both submanifold (S-SCONV) and non-submanifold (N-SCONV) sparse convolutions. The mapping-centric design decouples feature maps and coordinates, enabling parallelism and optimizing on-chip memory traffic. A reconfigurable computing array executes SCONVs with different dataflows, and a lightweight Reuse LUT improves data reuse under sparse workloads. Fabricated in 28 nm CMOS, the core chip occupies 1.04 mm2 and operates at 225–360 MHz. Measurements show a peak energy efficiency of 4.87 TOPS/W at 275 MHz, demonstrating superior efficiency versus prior ASIC accelerators, while it can achieve 8.8 FPS on widely used benchmarks. These results indicate that the proposed architecture can satisfy the stringent latency and power constraints for edge 3D perception.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"588-592"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Fully Integrated N-P Source Follower Domino Buffer FVF LDO With Fast Transient Response 具有快速瞬态响应的全集成N-P源从动器多米诺缓冲FVF LDO

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-05 DOI: 10.1109/TCSII.2026.3670841

Fengyuan Zuo;Xu Han;Shi Tao;Yuyang Chen;Chi Zhang;Chao Luo;Guoping Guo

引用次数: 0

Hardware-Efficient QC-LDPC Decoding Architecture With Reduced Bit-Width and Saturation Management 具有降低位宽和饱和管理的硬件高效QC-LDPC解码架构

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-16 DOI: 10.1109/TCSII.2026.3674508

Hyeongseok Moon;In-Cheol Park

{"title":"Hardware-Efficient QC-LDPC Decoding Architecture With Reduced Bit-Width and Saturation Management","authors":"Hyeongseok Moon;In-Cheol Park","doi":"10.1109/TCSII.2026.3674508","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3674508","url":null,"abstract":"In quantized layered low-density parity-check (LDPC) decoding, the saturated a posteriori probability (APP) value prevents extrinsic information from being correctly accumulated and overemphasizes certain error paths, making it necessary to use a larger APP representation. The proposed method compensates for the information loss caused by such saturation and eliminates the need for a larger APP bitwidth, reducing the APP bitwidth to the level of the check-to-variable message while preserving the decoding performance. This compensation is achieved by disabling APP updates when saturation occurs, starting from the iteration identified by the shortest cycles in the parity-check matrix. The proposed control preserves correct message passing and prevents the accumulation of error-path weights in the APP. In the prototype LDPC decoder, the proposed method requires only a lightweight circuit to detect saturation, incurring a negligible area overhead and almost no degradation of processing delay. As a result, the proposed architecture reduces area and power by 15% and 25%, respectively, and achieves a throughput-to-area ratio of 25.08 Gbps/itr/mm2, while maintaining the FER performance of the 7-bit APP representation.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"553-557"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-02-27 DOI: 10.1109/TCSII.2026.3664628

引用次数: 0