IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第2页

A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA 一种0.0019 mm²lc环振荡器，带超紧凑变压器，实现175.2 dBc/Hz FoM@1MHz和202.4 dBc/Hz FoMA

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-21 DOI: 10.1109/TCSII.2025.3553716

Ya Zhao;Lingao Huang;Runchen Wang;Jun Yin;Pui-In Mak;Li Geng;Chao Fan

{"title":"A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA","authors":"Ya Zhao;Lingao Huang;Runchen Wang;Jun Yin;Pui-In Mak;Li Geng;Chao Fan","doi":"10.1109/TCSII.2025.3553716","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3553716","url":null,"abstract":"This brief describes an area-efficient LC-ring oscillator featuring an ultra-compact transformer resonator. The series inverters could be equivalent to the negative resistors providing gain compensation. The involved inverters and switched-capacitor banks are fully integrated underneath the transformer resonator. Thus, with a comparable area of the typical ring oscillators, our oscillator shows significantly improved phase noise (PN) and figure-of-merit (FoM). Besides, we implemented the stacked-coupling and distributed-coupling transformer-based LC-ring oscillators for the PN and FoM comparison. The stacked-coupling LC-ring oscillator can lower the PN with the same frequency and power budget. Fabricated in 40-nm CMOS, our stacked-coupling LC-ring oscillator scores a <inline-formula> <tex-math>${mathrm { PN}}_{unicode {0x0040}1{mathrm { MHz}}}$ </tex-math></inline-formula> of -110.4 dBc/Hz across the frequency tuning range from 3.7 to 5.1 GHz with an active area of 0.0019 mm2, corresponding to a superior FoM (FoMA)<inline-formula> <tex-math>${}_{text {@1MHz}}$ </tex-math></inline-formula> of 175.2 dBc/Hz (202.4 dBc/Hz) that is 4.2 dB (6 dB) higher than the distributed-coupling LC-ring oscillator.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"693-697"},"PeriodicalIF":4.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm 具有转移训练算法的28纳米无mfcc关键字可切换关键字定位系统

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-19 DOI: 10.1109/TCSII.2025.3552970

Fei Tan;Yujia Wang;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak

{"title":"A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm","authors":"Fei Tan;Yujia Wang;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3552970","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552970","url":null,"abstract":"In this brief, we propose an ultra-low-power mel frequency cepstral coefficients (MFCCs)-free keyword switchable KWS system that supports ten sub-classifiers (2 keywords each, 20 keywords in total) through a time-domain transferred training convolutional neural network (TT-CNN). The proposed TT-CNN reduces the model size by sharing the first two convolutional layers with all the keywords with a transferred training approach. Hence, the power budget for memory and computation is largely reduced. The TT-CNN supports flexible keyword demand in different scenes by selecting different kernels in the custom-designed 5T-SRAM. The time-domain feature of the proposed TT-CNN avoids the power-hungry feature extractor (FEx), further reducing the overall power consumption. To benchmark with the state-of-the-art, we demonstrated the proposed system with two cascaded scalable 10-Class KWS chips in 28nm CMOS. Our design achieves a high accuracy of 92.8% on 20 keywords from the Google speech command dataset (GSCD). It also shows that the memory overhead for each keyword can be reduced by 20% with the lowest reported 20-class KWS power consumption of <inline-formula> <tex-math>$1.2~mu $ </tex-math></inline-formula> W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"803-807"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Reduced Capacitance H-9 Five-Level Switched Boost Capacitor Transformerless Inverter 小电容H-9五电平开关升压电容无变压器逆变器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-19 DOI: 10.1109/TCSII.2025.3552764

Md Sartaj Ahmed;Ravi Raushan;Md Waseem Ahmad

{"title":"A Reduced Capacitance H-9 Five-Level Switched Boost Capacitor Transformerless Inverter","authors":"Md Sartaj Ahmed;Ravi Raushan;Md Waseem Ahmad","doi":"10.1109/TCSII.2025.3552764","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552764","url":null,"abstract":"Transformerless switched capacitor-based multi-level inverters are well-known for their applications in industrial and renewable energy systems. The primary features of a switched capacitor-based transformerless inverter should be minimizing leakage current for safety and minimizing ripple current for efficiency and reliability. This brief proposes a new single-stage, single-phase, five-level H-9-based transformerless inverter for standalone PV systems. This H-9 inverter, utilizes nine switches to produce the desired output voltage levels. It achieves boost functionalities by combining the switched capacitor (SC) unit with the switched boost (SB) unit in a single design. This topology effectively mitigates the leakage current by virtually grounding the load terminal through the filter capacitor. Furthermore, the ripple current of the capacitors in the switched-capacitor unit is minimized, and it is inherently balanced. To this end, the feasibility of utilizing the modulation technique for control is demonstrated, and the relevant results are experimentally validated using a laboratory prototype of the proposed converter.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"788-792"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Single-XO Dual-Output Frequency Reference Featuring Adaptive RTC Calibration Achieving 0.63 ppm/°C Temperature Coefficient From –40 °C to 125 °C 单xo双输出频率基准具有自适应RTC校准实现0.63 ppm/°C温度系数从-40°C到125°C

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-18 DOI: 10.1109/TCSII.2025.3552650

Rui Luo;Ka-Meng Lei;Rui P. Martins;Pui-In Mak

{"title":"A Single-XO Dual-Output Frequency Reference Featuring Adaptive RTC Calibration Achieving 0.63 ppm/°C Temperature Coefficient From –40 °C to 125 °C","authors":"Rui Luo;Ka-Meng Lei;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3552650","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552650","url":null,"abstract":"This brief presents a trimming-free single-crystal dual-output (SXDO) frequency reference featuring adaptive binary-search (ABS)-based real-time clock (RTC) calibration. The on-demand 16-MHz crystal oscillator (XO) can serve as a frequency reference to calibrate the always-on 1-MHz on-chip RTC. To suppress the inaccurate calibration in the wake of the oscillator’s jitter, we propose the ABS-based calibration to adjust the accumulation cycles depending on the frequency difference between the XO and RTC to enhance the comparison accuracy. Further, we reuse the accurately calibrated RTC signal as a reference to generate a 16-MHz pulse train and inject it into the crystal to expedite the XO startup. We implemented the proposed SXDO frequency reference in a 65-nm CMOS process. The RTC achieves a temperature coefficient of 0.63 ppm/°C across -40 to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C. The calibration takes <inline-formula> <tex-math>$720~mu $ </tex-math></inline-formula>s while consuming 40.3 nJ of energy. The XO, benefitting from the RTC-assisted constant injection with improved accuracy, can exert injection of <inline-formula> <tex-math>$60~mu $ </tex-math></inline-formula>s and attain a startup time of <inline-formula> <tex-math>$145~mu $ </tex-math></inline-formula>s, with a startup energy of 9.9 nJ.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"688-692"},"PeriodicalIF":4.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 4 × 4 Fully Integrated RF Transceiver in 6 GHz Frequency Band With Single-Channel Bandwidth of 400 MHz and PHY Data-Rate of 8.8 Gbps 6ghz频段4 × 4全集成射频收发器，单通道带宽400mhz， PHY数据速率8.8 Gbps

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-18 DOI: 10.1109/TCSII.2025.3552472

Youming Zhang;Fengyi Huang;Xusheng Tang;Junjie Li;Zhennan Wei;Yunqi Cao

{"title":"A 4 × 4 Fully Integrated RF Transceiver in 6 GHz Frequency Band With Single-Channel Bandwidth of 400 MHz and PHY Data-Rate of 8.8 Gbps","authors":"Youming Zhang;Fengyi Huang;Xusheng Tang;Junjie Li;Zhennan Wei;Yunqi Cao","doi":"10.1109/TCSII.2025.3552472","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552472","url":null,"abstract":"This brief presents a fully integrated CMOS <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> MIMO RF transceiver (TRX) with single-channel bandwidth (BW) of 400 MHz in the 6 GHz band (5.925-7.125 GHz). In the receiver (RX) frontend, an improved noise-canceling low noise amplifier (LNA) and a cross-coupled transconductance <inline-formula> <tex-math>$(G_{M})$ </tex-math></inline-formula> with IIP2 enhancement is implemented. In the transmitter (TX) frontend, a power amplifier driver (PAD) is integrated with cascade AM-PM distortion compensation to eliminate the AM-PM distortion. A hierarchical LO distribution network is employed in the 1-to-4 LO distribution chain to enhance the consistency among the LO branches. The single-chip TRX is reconfigurable for TDD/FDD operation, with the RX exhibiting a noise figure of 3.5-4.1 dB, a gain control range of 45 dB with 1 dB step and ±0.2 dB gain flatness. The TX output spectrum exhibits >32 dBc signal to noise ratio (SNR). The RX and TX error vector magnitudes (EVMs) are −30.2 dB and −30.5 dB, respectively, with 160 MHz BW 256QAM. A TX-to-RX PHY data-rate of 8.8 Gbps based on <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> MIMO is achieved, with other major parameters comparable to the prior arts without resorting to digital calibration circuits.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"723-727"},"PeriodicalIF":4.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy Efficient On-Chip Memory for Next Generation MCU 用于下一代MCU的节能片上存储器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-17 DOI: 10.1109/TCSII.2025.3551733

Longning Qi;Jinqi Fan;Tongheng Rao;Meiyan Lv;Jingu Ma;Hao Cai

{"title":"Energy Efficient On-Chip Memory for Next Generation MCU","authors":"Longning Qi;Jinqi Fan;Tongheng Rao;Meiyan Lv;Jingu Ma;Hao Cai","doi":"10.1109/TCSII.2025.3551733","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3551733","url":null,"abstract":"Microcontroller units (MCUs) are increasingly required to be energy-conserving for IoT applications. Emerging devices, such as magnetic tunnel junctions and tunnel field-effect transistors (TFETs), present innovative solutions for ultra-low-power embedded memories. This brief demonstrates MRAM and TFET-SRAM as alternatives to embedded Flash and retention SRAM in MCUs, respectively. A specially designed sense amplifier capable of bidirectional voltage differential amplification enables two readouts during the charge/discharge phase of bit lines. Furthermore, a mismatch-aware latch amplifier is proposed to yield considerable read accuracy of MRAM. The bidirectional read strategy, named Ri-Fa, efficiently eliminates unnecessary error correction process. Under 28-nm CMOS technology, the 512Kb MRAM achieves <15ns> <tex-math>$2.23{mu }$ </tex-math></inline-formula>A/MHz. Furthermore, the TFET/CMOS hybrid bit-cell introduces an extra n-type TFET to gate the supply of SRAM in retention mode, suppressing the leakage current of 1Kb macro to 6nA. The 55-nm MCU with TFET-SRAM presents a record ultra-low standby power of 75nA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"768-772"},"PeriodicalIF":4.0,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Adaptive Body Tuned Sense Amplifier for Energy Efficient In-Memory Computing 一种用于节能内存计算的自适应体调谐感测放大器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-17 DOI: 10.1109/TCSII.2025.3551822

Bibhudutta Satapathy;Karan Jadhav;Amandeep Kaur

引用次数: 0

A 59.2–83.3 GHz CMOS LNA With 18.1 dB Gain and 5.1 dB NF Using Gate-Drain Transformer 一种增益为18.1 dB、NF为5.1 dB的59.2-83.3 GHz CMOS LNA

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-17 DOI: 10.1109/TCSII.2025.3551910

Zhuming Li;Yinhan Lin;Haoshen Zhu;Xiang Yi;Wenquan Che;Quan Xue

引用次数: 0

An Energy-Efficient Capacitance-to-Digital Converter With Top and Bottom Plate Sampling for Pressure Sensors 一种具有顶底板采样的压力传感器高效电容-数字转换器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-14 DOI: 10.1109/TCSII.2025.3551361

Qingjiang Xia;Fei Zhou;Yuze Niu;Mingzhong He;Wengao Lu;Yacong Zhang;Zhongjian Chen

{"title":"An Energy-Efficient Capacitance-to-Digital Converter With Top and Bottom Plate Sampling for Pressure Sensors","authors":"Qingjiang Xia;Fei Zhou;Yuze Niu;Mingzhong He;Wengao Lu;Yacong Zhang;Zhongjian Chen","doi":"10.1109/TCSII.2025.3551361","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3551361","url":null,"abstract":"This brief presents a 12-bit low-power successive-approximation-register (SAR) capacitance-to-digital converter (CDC) for capacitive pressure sensors. It adopts a capacitance-to-voltage front-end (CVFE) scheme to decouple the capacitive digital-to-analog converter (CDAC) from the sensor capacitor, enabling a large swing of the SAR analog-to-digital converter (ADC) and a wide capacitance sensing range. To improve power efficiency, this brief proposed a top and bottom sampling (TBS) for CVFE circuit to achieve a single-ended sampling while differential conversion. The TBS includes only one sampling phase, which relaxes the amplifier’s bandwidth requirements, thereby reducing the power consumption of the CVFE. The prototype chip was fabricated using a 180-nm CMOS process. The measured capacitance resolution is 1.76 fF and the measurement capacitance range is from 0.63 pF to 38.37 pF. The proposed CDC consumes <inline-formula> <tex-math>$3.90~mu $ </tex-math></inline-formula>W with a <inline-formula> <tex-math>$128~mu $ </tex-math></inline-formula>s conversion time, bringing a power efficiency of 80.6 fJ/conversion-step.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"678-682"},"PeriodicalIF":4.0,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area-Efficient High-Precision Analog Front End for Battery Management System 一种用于电池管理系统的面积高效高精度模拟前端

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-13 DOI: 10.1109/TCSII.2025.3551150

Kuan Deng;Jie Ding;Jingnan Zheng;Yongzhen Chen;Jiangfeng Wu

引用次数: 0