IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第2页

Estimated Position Error Suppression Using Frequency-Domain Shaped Nonlinear Layered Observer for PMSM Speed-Sensorless Control 基于频域非线性分层观测器的PMSM无速度传感器控制估计位置误差抑制

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-12 DOI: 10.1109/TCSII.2026.3703192

Wenjie Li;Yongting Deng;Chuanlong Zhai;He Wang;Jia Fu;Xiufeng Liu;Haiyang Cao;Christopher H. T. Lee

{"title":"Estimated Position Error Suppression Using Frequency-Domain Shaped Nonlinear Layered Observer for PMSM Speed-Sensorless Control","authors":"Wenjie Li;Yongting Deng;Chuanlong Zhai;He Wang;Jia Fu;Xiufeng Liu;Haiyang Cao;Christopher H. T. Lee","doi":"10.1109/TCSII.2026.3703192","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3703192","url":null,"abstract":"To suppress position estimation errors inherent in speed-sensorless PMSM control, a frequency-domain shaped nonlinear layered observer is proposed in this brief. The proposed method leverages a smooth gating function to naturally establish a layered mechanism: the outer layer exploits high-order nonlinearity to accelerate back electromotive force convergence, while the inner layer transitions into a linear kernel integrated with an internal model term. Through precise frequency-domain shaping, the observer guarantees zero phase lag and unity gain in BEMF estimation, alongside robust DC-bias suppression. Unlike existing linear or nonlinear methods, the FSNLO simultaneously achieves superior dynamic response and uncompromised frequency-domain shaping capabilities. Rigorous stability analyses prove uniform ultimate boundedness. Comparative experiments validate the superiority of the proposed method, demonstrating remarkable enhancements in both steady-state and dynamic estimation precision.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"853-857"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Coupled-Line-Based Modeling and Design of Symmetric T-Coil Structures 基于耦合线的对称t形线圈结构建模与设计

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-06 DOI: 10.1109/TCSII.2026.3710230

Junyeop Kim;Sungjun Lee;Kyubin Choi;Wooyeol Choi

引用次数: 0

A Timing-Relaxed Split-Phase Decision-Feedback Equalizer With Overlap-Free Boundary Handling 具有无重叠边界处理的时间松弛分相决策反馈均衡器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-06 DOI: 10.1109/TCSII.2026.3710186

Jin-Seok Heo;Yoona Lee;Kahyun Kim;Woo-Seok Choi

{"title":"A Timing-Relaxed Split-Phase Decision-Feedback Equalizer With Overlap-Free Boundary Handling","authors":"Jin-Seok Heo;Yoona Lee;Kahyun Kim;Woo-Seok Choi","doi":"10.1109/TCSII.2026.3710186","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3710186","url":null,"abstract":"This brief proposes a split-phase decision-feedback equalizer (SP-DFE) for block-parallel ADC-DSP-based wireline receivers. The proposed architecture achieves overlap-free boundary handling—avoiding the explicit history region required by sliding-block DFE (SB-DFE)—by partitioning DFE operation into two time-separated phases: block-wise decoding first proceeds from current-block observations, and only the prefix is later corrected using delayed final tail decisions from the preceding block while the forward-phase suffix is retained. By reusing a precomputed candidate set, the added implementation overhead is localized to the seed-generation and prefix-correction paths, and prefix correction is processed in parallel with the forward-decision pipeline without a dedicated correction cycle. The proposed architecture also avoids the segmented seed-expanded speculative burden of loop-break DFE. FPGA validation on a ZCU102 board across input SNR from 20 to 28 dB under a 40-dB-loss channel confirms BER performance equivalent to a baseline 2-tap SB-DFE. Synthesis and P&R results in 28-nm CMOS show that the proposed SP-DFE achieves 25.2 %/24.7 % DFE-backend area/power reductions relative to the re-implemented 2-tap SB-DFE baseline. Moreover, the added split-phase logic accounts for only about 2.7 % of the total DSP area compared to an unmodified 2-tap loop-unrolled DFE core, demonstrating timing relaxation with limited implementation overhead.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"843-847"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-31 DOI: 10.1109/TCSII.2026.3714260

引用次数: 0

An Ultra-Compact 64–98-GHz Power-Combining Frequency Doubler With Magnetic-Enhanced Harmonic Reflectors 带磁增强谐波反射器的超紧凑型64 - 98 ghz功率组合倍频器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-01 DOI: 10.1109/TCSII.2026.3698679

Zesen Chen;Tingting Yuan;Zhiwei Xu

引用次数: 0

A 0.055-mm2 250–750 MHz, 1.5-pJ/Cycle FLL-Based On-Chip Clock Generator With Second-Order Compensation and Reference Trimming Achieving ±0.156% Inaccuracy From –40 °C to 105 °C in 55-nm CMOS 一种0.055-mm2 250-750 MHz， 1.5 pj /Cycle基于fll的片上时钟发生器，具有二阶补偿和基准微调，在55纳米CMOS中，在-40°C至105°C范围内实现±0.156%的误差

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-01 DOI: 10.1109/TCSII.2026.3708470

Hongtao Huang;Chenchong Yuan;Tong Chen;Peng Tang;Lu Ning;Xinnuo Zhang;Pengcheng He;Longbiao Wang;Peng Xu;Chao Song;Cheng Wu;Warren Feng;Xiongchuan Huang

{"title":"A 0.055-mm2 250–750 MHz, 1.5-pJ/Cycle FLL-Based On-Chip Clock Generator With Second-Order Compensation and Reference Trimming Achieving ±0.156% Inaccuracy From –40 °C to 105 °C in 55-nm CMOS","authors":"Hongtao Huang;Chenchong Yuan;Tong Chen;Peng Tang;Lu Ning;Xinnuo Zhang;Pengcheng He;Longbiao Wang;Peng Xu;Chao Song;Cheng Wu;Warren Feng;Xiongchuan Huang","doi":"10.1109/TCSII.2026.3708470","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3708470","url":null,"abstract":"This brief presents the analysis and implementation of a wide-range frequency-locked loop (FLL)-based on-chip clock generator. Leveraging a 2nd-order temperature-compensated R-RC network, this work systematically optimizes a reference voltage with a tailored temperature coefficient to cancel both 1st- and 2nd-order temperature dependencies. A mathematical model is developed to optimize the frequency stability across a wide temperature range. Furthermore, a digitally assisted loop architecture is employed to enhance area efficiency and eliminate the impact of comparator delay, ensuring the output frequency is defined solely by the R-RC time constant. Fabricated in a 55-nm CMOS process, the prototype occupies an active area of 0.055 mm2. Measurement results show that the FLL covers a frequency range of 250 to 750 MHz. At 400 MHz, it achieves an energy efficiency of 1.5 pJ/cycle and a worst-case temperature coefficient (TC) of 21.5 ppm/°C from <inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$105~^{circ }$ </tex-math></inline-formula>C, along with a period jitter of 3 ps and a supply sensitivity of 166 ppm/V enabled by an integrated low-dropout regulator (LDO).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"813-817"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LLC Resonant Converter-Based Embedded EIS Measurement Method for Lithium-Ion Battery 基于LLC谐振变换器的锂离子电池嵌入式EIS测量方法

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-22 DOI: 10.1109/TCSII.2026.3705900

Yi Jiang;Chuhan Chen;Yuanhang Liu;Tingyao Cai;Yifan Fu;Jin Sha

{"title":"LLC Resonant Converter-Based Embedded EIS Measurement Method for Lithium-Ion Battery","authors":"Yi Jiang;Chuhan Chen;Yuanhang Liu;Tingyao Cai;Yifan Fu;Jin Sha","doi":"10.1109/TCSII.2026.3705900","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3705900","url":null,"abstract":"An embedded electrochemical impedance spectroscopy (EIS) measurement method is proposed for lithium-ion batteries based on an LLC resonant converter. By superimposing a small-signal sinusoidal perturbation onto the constant-current reference and exploiting the frequency-dependent gain characteristics of the LLC resonant converter under pulse-frequency modulation (PFM), the battery impedance is extracted through synchronous voltage and current sampling. To ensure stable perturbation injection and measurement accuracy, the small-signal behavior of the LLC resonant converter under battery load is analyzed, where the lithium battery is modeled as a second-order RC equivalent model. The influence of load-impedance magnitude and phase on the converter gain characteristics is clarified, and the effective operating range for EIS excitation is identified. A PI-regulated current loop is also designed to confine the switching frequency within the resonant region, achieving non-destructive measurement without additional analog front-end hardware. Experimental results shows that the proposed method can achieve accurate EIS measurement from 0.1Hz to 2kHz with a low normalized root-mean-square error (NRMSE) of 2.24% under different states of charge (SOCs).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"878-882"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Power Second-Order ΔΣ Modulator With a Single Current-Starving FIA 具有单电流饥饿FIA的低功率二阶ΔΣ调制器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-26 DOI: 10.1109/TCSII.2026.3707609

Zhiyao Pan;Jing Wang;Shasha Liu;Jiayu Liu;Wen Sun;Qiang Li;Lin Cheng

引用次数: 0

A Q-Band High-Power SiGe HBT Doherty Power Amplifier Leveraging 8-Shaped Inductor-Embedded Ultra Compact Doherty Passive Network 一种利用8形电感嵌入式超紧凑型多尔蒂无源网络的q波段大功率sighbt多尔蒂功率放大器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-03 DOI: 10.1109/TCSII.2026.3709987

Byeongcheol Yoon;Seung-Pyo Han;Junghyun Kim;Inchan Ju

{"title":"A Q-Band High-Power SiGe HBT Doherty Power Amplifier Leveraging 8-Shaped Inductor-Embedded Ultra Compact Doherty Passive Network","authors":"Byeongcheol Yoon;Seung-Pyo Han;Junghyun Kim;Inchan Ju","doi":"10.1109/TCSII.2026.3709987","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3709987","url":null,"abstract":"This brief presents a compact, high power <inline-formula> <tex-math>$Q$ </tex-math></inline-formula>-band SiGe HBT Doherty power amplifier (PA) for very low earth orbit (VLEO) satellite communication (SATCOM). An 8-shaped inductor-based <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/4 impedance inverter, embedded into an output transformer (TF) balun, results in magnetic coupling cancellation (MCC) between the two, enabling to implement compact Doherty network in a single footprint. Also, an adaptive bias circuit (ABC) helps abruptly turn on and off a peaking (PK) amplifier, leading to true Doherty operation as evidenced by clear PAE peaking at 6-dB power back-off (PBO). A prototype is fabricated in 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe HBT BiCMOS, with an active area of 0.46 mm2. It attains peak output power (P<inline-formula> <tex-math>${}_{mathrm {OUT}}$ </tex-math></inline-formula>) and power added efficiency (PAE) of 24.5 dBm and 23.9% at 38 GHz. At a 6-dB PBO, the PA achieves a PAE of 22.7%. The PA was also evaluated by a 200 MHz 5G NR FR2 64-QAM CP-OFDM with 9.7 dB peak-to-average power ratio (PAPR) signals, achieving 13.1 dBm average POUT (P<inline-formula> <tex-math>${}_{mathrm {avg}}$ </tex-math></inline-formula>) with 13.8% average PAE (PAE<inline-formula> <tex-math>${}_{mathrm {avg}}$ </tex-math></inline-formula>) at EVM of −25.0 dB.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"838-842"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2-Vpp 106-dB SFDR Artifact-Tolerant Gm-C CT-DSM ADC With Residue-Compression and Gm-Boosting Technique 基于残留压缩和gm增强技术的2-Vpp 106db SFDR伪影容错Gm-C CT-DSM ADC

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-10 DOI: 10.1109/TCSII.2026.3702101

Chen Wang;Wenshuo Li;Yuanqi Hu

{"title":"A 2-Vpp 106-dB SFDR Artifact-Tolerant Gm-C CT-DSM ADC With Residue-Compression and Gm-Boosting Technique","authors":"Chen Wang;Wenshuo Li;Yuanqi Hu","doi":"10.1109/TCSII.2026.3702101","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3702101","url":null,"abstract":"This brief presents a high-linearity, artifact-tolerant, fourth-order Gm–C continuous-time <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> modulator (CT-DSMS) for neural recording. To address the transconductor nonlinearity limitations inherent to conventional Gm–C CT-DSMs, a combined input–feedback linearity enhancement strategy is introduced. A passive single-bit, four-tap FIR-based low-pass filter DAC is employed to attenuate the input–feedback residue by more than <inline-formula> <tex-math>$40times $ </tex-math></inline-formula>, leveraging the intrinsic linearity of single-bit quantization. In parallel, a Gm-boosted differential difference amplifier with source degeneration is utilized to extend the linear operating range of the constructor, providing a 4–<inline-formula> <tex-math>$6times $ </tex-math></inline-formula> improvement relative to conventional implementations. Operating at a 10-MHz sampling frequency with a 50 kHz signal bandwidth, the proposed modulator achieves a 94.0 dB dynamic range (DR), 91.2 dB peak SNDR, and 106.0 dB SFDR under a 2-Vpp input, corresponding to a FoMSNDR of 170.2 dB. The modulator further demonstrates a high common-mode rejection ratio of 84 dB. Together with its wide linear input range, these attributes enable direct digitization of tens-of-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V-level biopotentials in the presence of volt-level artifacts, making the architecture well suited to buffer-less, high-impedance biopotential interfaces for neural recording.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"783-787"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0