IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第10页

A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7% 一个12v输入0.3 V至0.6 V输出不平衡电感电流变换器，达到90.7%的峰值效率

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-25 DOI: 10.1109/TCSII.2024.3486362

Chan-Ho Lee;Jeong-Hun Kim;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong

{"title":"A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7%","authors":"Chan-Ho Lee;Jeong-Hun Kim;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/TCSII.2024.3486362","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3486362","url":null,"abstract":"This brief proposed an imbalanced inductor-current buck (IIB) converter. The proposed IIB converter has two inductor current paths. The IIB converter provides majority of the load current through a current path composed of low voltage transistors and minority of the load current through the current path composed of high voltage transistors, which becomes further as voltage conversion ratio decreases. Therefore, the IIB converter reduces conduction loss as the voltage conversion ratio decreases, which is considerably important in low voltage applications. In addition, since this converter uses a flying capacitor network behind the inductor, it is invulnerable to the input voltage variation. The proposed converter has peak efficiencies of 90.7% at \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { IN}} {=} 12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { O}} {=} 0.6$ </tex-math></inline-formula>\u0000 V, and 85.6% at \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { IN}} {=} 12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { O}} {=} 0.3$ </tex-math></inline-formula>\u0000 V. The chip was fabricated in 130-nm BCD process with an area of 6.177 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"338-342"},"PeriodicalIF":4.0,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors 采用嵌套缠绕尾电感的面积高效CMOS交叉耦合LC-VCO

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-24 DOI: 10.1109/TCSII.2024.3485921

Hyogyoung An;Hyeonjun Nam;Sungjin Kim;Younghyun Lim;Heein Yoon

{"title":"An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors","authors":"Hyogyoung An;Hyeonjun Nam;Sungjin Kim;Younghyun Lim;Heein Yoon","doi":"10.1109/TCSII.2024.3485921","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485921","url":null,"abstract":"An area-efficient CMOS cross-coupled LC-VCO, operating from 5.74 GHz to 8.02 GHz and featuring a tail noise filter with two tail inductors integrated inside the main inductor, is presented for the first time. The tail noise filter comprised two nested intertwined tail inductors (NITIs) and a tail capacitor bank, effectively suppressing phase noise (PN) while generating negligible magnetic couplings between the main inductor and the NITIs. The proposed architecture enables area-efficient CMOS cross-coupled design, even with the two NITIs, but has no performance degradation, i.e., it eliminates the additional area for the tail noise filter. Implemented in 28-nm CMOS process, it consumed 11 mA current from 0.73 V power supply. The LC-VCO achieved PN of −116.38 dBc/Hz at 1 MHz offset frequency for an output frequency of 5.747 GHz. 37% and 27% reductions in silicon area were achieved, over the conventional LC-VCO and an LC-VCO using intertwined tail inductors (ITIs), respectively, without compromising on performance. The proposed design has the smallest area among state-of-the-art LC-VCOs that include a tail noise filter along with competitive PN and frequency tuning range (FTR).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"143-147"},"PeriodicalIF":4.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parasitic-Aware Analysis and Design of a Wideband gm-Boost Low Noise Amplifier at K-Band k波段宽带gm-Boost低噪声放大器的寄生感知分析与设计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-24 DOI: 10.1109/TCSII.2024.3485649

Hongjie Zeng;Zemeng Huang;Tao Tan;Yubing Li;Xiuping Li

{"title":"Parasitic-Aware Analysis and Design of a Wideband gm-Boost Low Noise Amplifier at K-Band","authors":"Hongjie Zeng;Zemeng Huang;Tao Tan;Yubing Li;Xiuping Li","doi":"10.1109/TCSII.2024.3485649","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485649","url":null,"abstract":"This brief presents a wideband low noise amplifier (LNA) at K-band. A parasitic-aware analysis focused on gain is proposed in the transformer feedback \u0000<inline-formula> <tex-math>$g_{mathrm {m}}$ </tex-math></inline-formula>\u0000-boost common-gate (CG) stage. This analysis models parasitic components as grounded equivalents, decoupling the amplifier into active circuitry and passive components. It addresses the design challenges of wideband amplifiers with complex capacitive networks, offering a more accurate representation of the amplifier’s characteristics and providing valuable guidance for parasitic-sensitive designs. The designed amplifier consists of a gm-boost transformer feedback CG stage followed by a capacitor-neutralized common source (CS) stage. An adapted interstage matching network is developed to compensate for the unbalanced transimpedance, which contributes to a flat overall wideband gain with a low noise figure (NF). The input and output of the LNA are well-matched and the LNA achieves a maximum gain of 14.6 dB, 3-dB bandwidth of 9.5 GHz (19-28.5 GHz), a minimum NF of 2.3 dB, and an input 1-dB compression point (IP1dB) exceeding -10.3 dBm across 19-28.5 GHz. The proposed LNA is implemented in a 110-nm CMOS process, occupying a compact chip area of 0.258 mm2 and consuming 25.6 mW at a supply voltage of 1.2 V. To the best of our knowledge, this brief represents the first comprehensive, parasitic-aware gain analysis of the transformer feedback \u0000<inline-formula> <tex-math>$g_{mathrm {m}}$ </tex-math></inline-formula>\u0000-boost CG stage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"138-142"},"PeriodicalIF":4.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration 前置开环增益校准的59.6fsrms抖动子采样锁相环

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485011

Yu-Chi Yen;Shen-Iuan Liu

引用次数: 0

Source Number Estimation in 2D Uniform Circular and L-Shaped Arrays With Unknown Nonuniform Noise 含未知非均匀噪声的二维均匀圆形和l形阵列的源数估计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485468

Mengxia He;S. C. Chan

{"title":"Source Number Estimation in 2D Uniform Circular and L-Shaped Arrays With Unknown Nonuniform Noise","authors":"Mengxia He;S. C. Chan","doi":"10.1109/TCSII.2024.3485468","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485468","url":null,"abstract":"Classical source number estimators are usually derived under the assumption of uniform white noise, which may degrade substantially with unknown nonuniform sensor noise. Advanced estimators designed for nonuniform noise are however computationally expensive with limited performance in unfavorable conditions, such as low signal-to-noise ratio, small number of snapshots, close angular separations and sources with different transmitter powers. This brief proposes a new likelihood ratio statistics-based method for source number estimation under uncorrelated nonuniform noise. Using the asymptotic theory, it is shown that the likelihood ratio follows a chi-square distribution. Hence, the number of sources can be estimated via a sequence of hypothesis tests using maximum likelihood estimators (MLEs) of the covariance matrix with different assumed source numbers. The low complexity subspace algorithm is proposed to obtain the ML estimates. Theoretical analysis demonstrates that the proposed estimator is consistent in the general asymptotic regime. Simulation results on 2D arrays such as uniform circular and L-shaped arrays show that the proposed estimator achieves a higher correct detection probability in unfavorable conditions and is more robust against nonuniformity of noise than state-of-the-art estimators.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"348-352"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications 机器学习应用中基于硬件优化回归树的Sigmoid和Tanh函数

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485493

Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi

{"title":"Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications","authors":"Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi","doi":"10.1109/TCSII.2024.3485493","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485493","url":null,"abstract":"The sigmoid and \u0000<inline-formula> <tex-math>$hyperbolic tangent~(tanh)$ </tex-math></inline-formula>\u0000 functions are widely recognized as the most commonly employed nonlinear activation functions in artificial neural networks. These functions incorporate exponential terms to introduce nonlinearity, which imposes significant challenges when realized on hardware. This brief presents a novel approach for the hardware implementation of sigmoid and tanh functions, leveraging a regression tree and linear regression. The proposed method divides their nonlinear region into small segments using a regression tree. These segments are further approximated using a linear regression technique, the line of best fit. Experimental results demonstrate the average errors of \u0000<inline-formula> <tex-math>$4times 10^{-4}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$9times 10^{-4}$ </tex-math></inline-formula>\u0000 of sigmoid and tanh functions compared to exact functions. The above functions produce 24.52% and 35.71% less average error than the best contemporary method when implemented on the hardware. Additionally, the hardware implementations of sigmoid and tanh functions are more area, power and delay efficient, showcasing the effectiveness of this method compared to other state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"283-287"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Temperature-Compensated Ku-Band Four-Beam Phased-Array Receiver With Low Attenuation and Relative Phase Variations 具有低衰减和相对相位变化的温度补偿ku波段四波束相控阵接收机

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485476

Shi Chao Jin;Jiaxing Sun;Zhuoheng Xie;Bo Huang;Dunge Liu;Yuqian Yang;Chenyu Mei;Jun Huang;Chenyu Wang;Xiulong Wu;Yu Jian Cheng

{"title":"A Temperature-Compensated Ku-Band Four-Beam Phased-Array Receiver With Low Attenuation and Relative Phase Variations","authors":"Shi Chao Jin;Jiaxing Sun;Zhuoheng Xie;Bo Huang;Dunge Liu;Yuqian Yang;Chenyu Mei;Jun Huang;Chenyu Wang;Xiulong Wu;Yu Jian Cheng","doi":"10.1109/TCSII.2024.3485476","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485476","url":null,"abstract":"This brief proposes a temperature-compensated Ku-band eight-element four-beam phased-array receiver with low attenuation and relative phase variations. By properly adjusting the gate voltage of the switch MOSFETs in the 6-bit step attenuator, the resistance of MOSFETs can remain constant with temperature variation. Furthermore, the attenuation and relative phase errors caused by ambient temperature variations can be effectively decreased to meet the requirements of phased-array systems. To verify the proposed method, an eight-element 10.7–12.7 GHz phased-array receiver is designed and fabricated using a 130-nm silicon-germanium (SiGe) BiCMOS process. With the help of minimized attenuation and phase variations, the phased-array receiver exhibits a root-mean-square (RMS) attenuation error less than 0.71 dB and a RMS relative phase error less than 2.7° from −40°C to 85°C at 10.7-12.7 GHz. Meanwhile, the measured noise figure (NF) and single-channel gain are 1.1-2.5 dB and 21.2-27.8 dB, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"83-87"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

All Stochastic-Spiking Neural Network (AS-SNN): Noise Induced Spike Pulse Generator for Input and Output Neurons With Resistive Synaptic Array 全随机尖峰神经网络（AS-SNN）：电阻式突触阵列输入输出神经元的噪声诱导尖峰脉冲发生器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485178

Honggu Kim;Yerim An;Minchul Kim;Gyeong-Chan Heo;Yong Shim

引用次数: 0

Erratum to “A 1–27 GHz SiGe Low Noise Amplifier With 27-dB Peak Gain and 2.85±1. 45 dB NF” 1 - 27 GHz SiGe低噪声放大器，峰值增益为27db， 2.85±1。45db NF”

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-22 DOI: 10.1109/TCSII.2024.3473488

Zongxiang Wang;Jixin Chen;Debin Hou;Peigen Zhou;Zhe Chen;Long Wang;Xiaojie Xu;Wei Hong

引用次数: 0

Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology 基于同步无线供电和数据传输技术的水下BWPT系统脉冲同步方案

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-22 DOI: 10.1109/TCSII.2024.3484453

Chaolai Da;Fang Li;Lifang Wang;Chengxuan Tao;Shufan Li;Ming Nie

引用次数: 0