IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第10页

Inverse-Free Hybrid Spatial-Temporal Derivative Neural Network for Time-Varying Matrix Moore–Penrose Inverse and Its Circuit Schematic 时变矩阵Moore-Penrose逆的无逆混合时空导数神经网络及其电路原理图

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-16 DOI: 10.1109/TCSII.2025.3530639

Bing Zhang;Yuhua Zheng;Shuai Li;Xinglong Chen;Yao Mao;Duc Truong Pham

引用次数: 0

An Edge Neuromorphic Processor With High-Accuracy On-Chip Aggregate-Label Learning 具有高精度片上聚合标签学习的边缘神经形态处理器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-15 DOI: 10.1109/TCSII.2025.3529670

Guanyu Chen;Mingju Chen;Tengxiao Wang;Haibing Wang;Xiang Fu;Yingcheng Lin;Liyuan Liu;Cong Shi

{"title":"An Edge Neuromorphic Processor With High-Accuracy On-Chip Aggregate-Label Learning","authors":"Guanyu Chen;Mingju Chen;Tengxiao Wang;Haibing Wang;Xiang Fu;Yingcheng Lin;Liyuan Liu;Cong Shi","doi":"10.1109/TCSII.2025.3529670","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3529670","url":null,"abstract":"Neuromorphic computing with bio-inspired spiking neural networks (SNNs) offers an energy-efficient paradigm for edge intelligence. But, achieving practically high on-chip SNN learning accuracy with limited hardware resources still remains challenging. To tackle this issue, this brief proposes an edge neuromorphic processor architecture enabling computationally-simple optimized aggregate-label (AL) algorithm to realize high-accuracy on-chip learning. To maximize utilization of multicore resources and minimize processing latency, our processor adopts techniques including uniform neuron-core mapping, layer-alternating workflow, time-step pipeline and event-driven scheme. We benchmarked our processor on an FPGA device, and attained high on-chip learning accuracies of 97.21%, 88.1%, 90.92%, 100% and 99.22% on MNIST, Fashion-MNIST, ETH-80, ORL-10, and Yale-10 datasets, respectively, using a small 2-layer fully-connected (FC) SNN, with a moderate resource cost and a relatively high energy efficiency. These results indicate that our design is very useful for many self-adaptive edge systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"509-513"},"PeriodicalIF":4.0,"publicationDate":"2025-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Predefined-Time Command Filtered Control for Tracking and Synchronization of Multi-Motor Servo Systems With Fuzzy Approximator 基于模糊逼近器的多电机伺服系统跟踪与同步的预定义时间命令滤波控制

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-14 DOI: 10.1109/TCSII.2025.3529750

Xiang Wang;Baofang Wang;Jinpeng Yu

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A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber 一种针对Kyber侧信道攻击的硬件友好型洗牌对策

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-13 DOI: 10.1109/TCSII.2025.3528751

Dejun Xu;Kai Wang;Jing Tian

{"title":"A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber","authors":"Dejun Xu;Kai Wang;Jing Tian","doi":"10.1109/TCSII.2025.3528751","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3528751","url":null,"abstract":"CRYSTALS-Kyber has been standardized as the only key-encapsulation mechanism (KEM) scheme by NIST to withstand attacks by large-scale quantum computers. However, the side-channel attacks (SCAs) on its implementation are still needed to be well considered for the upcoming migration. In this brief, we propose a secure and efficient hardware implementation for Kyber by incorporating a novel compact shuffling architecture. First of all, we modify the Fisher-Yates shuffle to make it more hardware-friendly. We then design an optimized shuffling architecture for the well-known open-source Kyber hardware implementation to enhance the security of all known and potential side-channel leakage points. Finally, we implement the modified Kyber design on FPGA and evaluate its security and performance. The security is verified by conducting correlation power analysis (CPA) and test vector leakage assessment (TVLA) on the hardware. Meanwhile, FPGA place-and-route results show that the proposed design reports only 8.7% degradation on the hardware efficiency compared with the original unprotected version, much better than existing hardware hiding schemes.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"504-508"},"PeriodicalIF":4.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Learning and Current Prediction of PMSM Drive via Differential Neural Networks 基于差分神经网络的永磁同步电机驱动学习与电流预测

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-08 DOI: 10.1109/TCSII.2025.3527024

Wenjie Mei;Xiaorui Wang;Yanrong Lu;Ke Yu;Shihua Li

引用次数: 0

On the Effect of Memory Error in a Time-Interleaved Pipeline ADC With a Shared Residue Amplifier 基于共享剩余放大器的时间交错管道ADC中存储器误差的影响

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-08 DOI: 10.1109/TCSII.2025.3526875

Debajit Basak;Siji Huang;George Yuan

引用次数: 0

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction 基于增益增强鉴相器和采样电容缩减的ii型参考采样锁相环的分析与设计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-08 DOI: 10.1109/TCSII.2025.3526921

Tailong Xu;Haoran Li;Xi Meng;Xiangxun Zhan;Yatao Peng;Jun Yin;Shiheng Yang;Chao Fan;Zhixiang Huang;Rui P. Martins;Pui-In Mak

{"title":"Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction","authors":"Tailong Xu;Haoran Li;Xi Meng;Xiangxun Zhan;Yatao Peng;Jun Yin;Shiheng Yang;Chao Fan;Zhixiang Huang;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3526921","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3526921","url":null,"abstract":"This brief analyzes the phase noise (PN) and reference (REF) spur performance of the reference-sampling (RS) PLL when the total sampling capacitor <inline-formula> <tex-math>$(C_{mathrm { S}})$ </tex-math></inline-formula> is reduced to save the power consumption of the crystal oscillator (XO) buffer. Based on the analysis, the saved power consumption from the XO buffer can be utilized to improve the PN of the voltage-controlled oscillator (VCO), which compensates for the in-band PN degradation induced by the <inline-formula> <tex-math>$C_{mathrm { S}}$ </tex-math></inline-formula> reduction. Based on this theme, we can reduce the total power consumption of the RS-PLL and the XO buffer without degrading the output root-mean-square (RMS) jitter by reducing <inline-formula> <tex-math>$C_{mathrm { S}}$ </tex-math></inline-formula> if a VCO with a high figure-of-merit (FoM) and a low <inline-formula> <tex-math>$1/{f}^{3}$ </tex-math></inline-formula> PN corner frequency is available. A type-II RS-PLL prototype utilizing a gain-boosting RS phase detector to suppress the voltage-to-current <inline-formula> <tex-math>$(G_{mathrm { M}})$ </tex-math></inline-formula> circuit noise is designed to verify the presented design strategy. With the aid of an inverse-class-F VCO with a FoM of 190.4 dBc/Hz at 1 MHz offset frequency and a <inline-formula> <tex-math>$1/{f}^{3}$ </tex-math></inline-formula> PN corner frequency of 300 kHz across the frequency tuning range from 5.2 GHz to 6.1 GHz, the RS-PLL prototype fabricated in a 65-nm CMOS achieves low RMS jitter and REF spur of 64.8 fs and -84.1 dBc, respectively, while dissipating 6.9 mW, corresponding to a jitter-power FoM (<inline-formula> <tex-math>$rm FoM{_{J}}$ </tex-math></inline-formula>) of -255.4 dB.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"439-443"},"PeriodicalIF":4.0,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2024 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 71 2024指数IEEE电路与系统交易II：快报简报卷71

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-08 DOI: 10.1109/TCSII.2025.3527324

引用次数: 0

Instrumentation Amplifier Input Impedance Calibration With Machine Learning-Based Optimizations 基于机器学习优化的仪器放大器输入阻抗校准

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-06 DOI: 10.1109/TCSII.2025.3526145

Safaa Abdelfattah;Hussein M. E. Hussein;Aatmesh Shrivastava;Marvin Onabajo

{"title":"Instrumentation Amplifier Input Impedance Calibration With Machine Learning-Based Optimizations","authors":"Safaa Abdelfattah;Hussein M. E. Hussein;Aatmesh Shrivastava;Marvin Onabajo","doi":"10.1109/TCSII.2025.3526145","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3526145","url":null,"abstract":"This brief introduces a digital calibration technique to boost the input impedance of instrumentation amplifiers (IAs) with digitally tunable input impedance. The technique employs two machine learning-driven optimization algorithms, the genetic algorithm (GA) and the particle swarm optimization (PSO) algorithm, to efficiently control integrated capacitor banks within the IA for the determination of the optimal input impedance. These algorithms offer a significant time reduction compared to a calibration with an exhaustive search, reducing calibration time by a factor of over <inline-formula> <tex-math>$10^{6}$ </tex-math></inline-formula> (with four 9-bit digital control words) while conserving computational resources. A prototype platform was developed to automatically optimize a fabricated IA test chip designed with 65-nm CMOS technology, which allows to test the machine learning algorithms using a microcontroller to control the digitally tunable input impedance. With an extra input capacitance of 100 pF, the GA algorithm achieved an input impedance of 1.75 G<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> after four generations (iterations), while the PSO algorithm achieved 1.27 G<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> with five iterations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"394-398"},"PeriodicalIF":4.0,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Series-LC-Assisted Oscillator Achieving –140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz 一种串联lc辅助振荡器，在10.7 GHz的10mhz偏置下实现-140.2 dBc/Hz相位噪声和187.5 dBc/Hz FoM

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-01 DOI: 10.1109/TCSII.2024.3524556

Xiangxun Zhan;Jun Yin;Rui P. Martins;Pui-In Mak

引用次数: 0