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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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Parallel Slew-Rate Enhancer With Current-Recycling Core for Switched-Capacitors Circuits 用于开关电容器电路的带电流再循环核心的并联骤变速率增强器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-04 DOI: 10.1109/TCSII.2024.3423313
Francesco Gagliardi;Alessandro Catania;Massimo Piotto;Paolo Bruschi;Michele Dei
{"title":"Parallel Slew-Rate Enhancer With Current-Recycling Core for Switched-Capacitors Circuits","authors":"Francesco Gagliardi;Alessandro Catania;Massimo Piotto;Paolo Bruschi;Michele Dei","doi":"10.1109/TCSII.2024.3423313","DOIUrl":"10.1109/TCSII.2024.3423313","url":null,"abstract":"Enhancing the slew-rate and settling speed of amplifiers in switched-capacitor circuits without incurring in static power penalties has long been a focal point. Standardized solutions remain elusive due to significant design challenges, particularly when confronted with capacitive loads close to the range of internal parasitic capacitances. Herein, we present a novel parallel-type slew-rate enhancer based on a current-recycling core, along with insights regarding settling time optimization under power constraints. We designed a switched-capacitor integrator based on a recycling folded cascode OTA, assisted by the proposed slew-rate enhancer, in a 180-nm 1.8-V CMOS technology. The circuit is operated with an equivalent capacitive load of approximately 8 pF and an input differential voltage step as large as 3.6 V. The system is required to settle in less than 40 ns, with a relative error on the final value below 0.1%. Simulation results show that, within the power budget of \u0000<inline-formula> <tex-math>$540~mu $ </tex-math></inline-formula>\u0000W, the proposed solution achieves a \u0000<inline-formula> <tex-math>$times 3.5$ </tex-math></inline-formula>\u0000 improvement in settling time compared to the OTA alone and a \u0000<inline-formula> <tex-math>$times 2.1$ </tex-math></inline-formula>\u0000 improvement compared to the OTA assisted by a standard parallel slew-rate enhancer.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4814-4818"},"PeriodicalIF":4.0,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10585330","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60-GHz Current-Reused Cascode Noise-Canceling Low Noise Amplifier 60-GHz 电流回用级联降噪低噪声放大器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-03 DOI: 10.1109/TCSII.2024.3422656
Aoran Han;Xun Luo
{"title":"A 60-GHz Current-Reused Cascode Noise-Canceling Low Noise Amplifier","authors":"Aoran Han;Xun Luo","doi":"10.1109/TCSII.2024.3422656","DOIUrl":"10.1109/TCSII.2024.3422656","url":null,"abstract":"In this brief, a current-reused noise-canceling low noise amplifier (LNA) operating at 60-GHz is proposed. To reduce the noise of cascode at millimeter-wave (mm-wave) frequency, an auxiliary path is introduced to neutralize the extra thermal noise of common-gate (CG) transistor caused by parasitic capacitance. The noise-canceling path is implemented in a current-reused way to prevent an excessive rise in dc power consumption. A size-aggregated self-coupling-canceling transformer is developed to decrease chip area without compromising noise cancellation effectiveness. The proposed cascode noise-canceling LNA is fabricated in a conventional 40-nm CMOS technology. The measurement results show a peak gain of 16.8 dB at 53.6 GHz and a 3-dB bandwidth from 50.6 to 67 GHz. The measured typical noise figure (NF) is 4.4–6.3 dB within the operating frequency range. The in-band input 1-dB compression point (IP1dB) is −13.0 dBm at 60 GHz. The proposed LNA can support 64-QAM with a 500-MHz channel bandwidth at 60 GHz achieving 2.3% Error Vector Magnitude (EVM).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4809-4813"},"PeriodicalIF":4.0,"publicationDate":"2024-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141549480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information 电气和电子工程师学会电路与系统论文集--II：特快摘要》出版信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-02 DOI: 10.1109/TCSII.2024.3417673
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3417673","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3417673","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 7","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10581879","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141494841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact Tunable Reflectionless Phase Shifter With Wide Bandwidth and Low Phase Deviation 带宽宽、相位偏差小的紧凑型可调式无反射移相器
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-02 DOI: 10.1109/TCSII.2024.3422279
Zilan Cao;Xiaojun Bi;Andy Shen;Chang Wu;Zhen Huang;Tao Guo;Qinfen Xu
{"title":"Compact Tunable Reflectionless Phase Shifter With Wide Bandwidth and Low Phase Deviation","authors":"Zilan Cao;Xiaojun Bi;Andy Shen;Chang Wu;Zhen Huang;Tao Guo;Qinfen Xu","doi":"10.1109/TCSII.2024.3422279","DOIUrl":"10.1109/TCSII.2024.3422279","url":null,"abstract":"A novel tunable reflectionless phase shifter (TRPS) utilizing the wideband reflectionless structure and two phase compensation techniques is firstly proposed, which offers a wide operational bandwidth, low phase deviation, and absorbed reflections. The operational bandwidth of the reflectionless structure is extended by incorporating independently-controlled resonant poles and low/high cut-off frequencies in the capacitor-loaded coupled structure and inductive absorptive networks, respectively. Furthermore, two phase compensation techniques are employed, including an AC grounded coupled line adopted in the tunable loads for impedance compensation and the inductive absorptive network reused to introduce additional phase, both contributing to low phase deviation. Measurement results indicate that the proposed TRPS features a fractional bandwidth of 116%, a continuously-tunable phase with deviation less than ±6.5°, and a continuous reflection absorptivity from DC to 12 GHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4864-4868"},"PeriodicalIF":4.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141524441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-02 DOI: 10.1109/TCSII.2024.3417669
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3417669","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3417669","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 7","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10581877","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141500284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Potentiostat-Based Wide-DR Multi-Sensor Integrated Interface for Heterogeneous Chemical Sensor Applications 用于异质化学传感器应用的基于恒电位仪的宽 DR 多传感器集成接口
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-01 DOI: 10.1109/TCSII.2024.3421366
Junyeong Yeom;Hyunjoong Kim;Woojae Jeong;Wootaek Cho;Taejung Kim;Souvik Bag;Yonggi Kim;Yunsik Lee;Heungjoo Shin;Jae Joon Kim
{"title":"A Potentiostat-Based Wide-DR Multi-Sensor Integrated Interface for Heterogeneous Chemical Sensor Applications","authors":"Junyeong Yeom;Hyunjoong Kim;Woojae Jeong;Wootaek Cho;Taejung Kim;Souvik Bag;Yonggi Kim;Yunsik Lee;Heungjoo Shin;Jae Joon Kim","doi":"10.1109/TCSII.2024.3421366","DOIUrl":"10.1109/TCSII.2024.3421366","url":null,"abstract":"A potentiostat-based wide dynamic range (DR) multi-sensor integrated interface is presented for heterogeneous chemical sensor applications. For versatility across various sensor kinds, a reconfigurable frontend structure based on the potentiostat is proposed to provide wide DR performance for multiple sensor types of electrochemical, chemo-resistive, and FET-based. Each operation mode for different sensor types is designed to support adaptive calibration capabilities on baseline, offset, and sensitivity. It is also designed to support selectable digital conversion methods for optimal conversion speed and resolution, depending on application requirements. In the electrochemical mode, bi-directional operation is implemented to support various detection methods including cyclic voltammetry and chronoamperometry. In the chemo-resistive mode, the DR performance is much extended especially in low-resistance range. Its read-out integrated circuit was fabricated in a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process. For system-level feasibility, a wireless sensor prototype with inhouse sensor devices was manufactured and experimentally verified, achieving measured DRs of 164.5 dB for current-type and 188 dB for resistive-type sensors.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4804-4808"},"PeriodicalIF":4.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141524442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 用于 FPGA 实现的基于 DSP 的高速低功耗 TRNG
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-01 DOI: 10.1109/TCSII.2024.3421323
Fabio Frustaci;Fanny Spagnolo;Pasquale Corsonello;Stefania Perri
{"title":"A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations","authors":"Fabio Frustaci;Fanny Spagnolo;Pasquale Corsonello;Stefania Perri","doi":"10.1109/TCSII.2024.3421323","DOIUrl":"10.1109/TCSII.2024.3421323","url":null,"abstract":"This brief presents an effective way to design high-throughput and low-power True Random Number Generators (TRNGs) for Field Programmable Gate Array (FPGA)-based digital systems. The proposed design makes an unconventional usage of the Digital Signal Processing (DSP) slice embedded within the AMD-Xilinx FPGA devices to implement high jitter ring oscillators as entropy sources for efficient TRNG designs. Thanks to its wide bit-width output, several configurations can be enabled to group multiple oscillators within a single DSP slice. As a result, a TRNG designed through the proposed scheme outputs up to 4 random bits per clock cycle, thus leading to a considerably high-throughput, while exploiting an ultra-compact architecture. When implemented on the AMD-Xilinx Zynq XC7Z020 System on Chip (SoC), the new architecture achieves a throughput of \u0000<inline-formula> <tex-math>$800times 10{^{{6}}}$ </tex-math></inline-formula>\u0000 bit/sec and an energy consumption of only 22 pJ/bit. When compared to state-of-the-art competitors it achieves a throughput rate up to \u0000<inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula>\u0000 higher and an energy consumption up to \u0000<inline-formula> <tex-math>$8times $ </tex-math></inline-formula>\u0000 lower. The new TRNG has been validated by means of the NIST SP 800-22, the NIST 800 90B and the AIS statistical tests.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4964-4968"},"PeriodicalIF":4.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10578016","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141509317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Steady-State Efficiency Optimization Method for PMSM Considering Current Distribution and Iron Loss Resistance 考虑电流分布和铁损电阻的 PMSM 稳态效率优化方法
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-06-28 DOI: 10.1109/TCSII.2024.3420783
Hanquan Zhang;Dong Xiao
{"title":"Steady-State Efficiency Optimization Method for PMSM Considering Current Distribution and Iron Loss Resistance","authors":"Hanquan Zhang;Dong Xiao","doi":"10.1109/TCSII.2024.3420783","DOIUrl":"10.1109/TCSII.2024.3420783","url":null,"abstract":"Conventional control strategy for permanent magnet synchronous machine (PMSM) has the defect of low steady-state efficiency as a result of ignoring iron loss resistance and unreasonable current distribution. In this brief, a steady-state efficiency improvement method considering the current distribution coefficient and iron loss resistance is proposed. Firstly, iron loss resistance is incorporated into equivalent circuit and mathematical model of the PMSM in d-q rotating coordinate frame. Secondly, steady-state reference current components of the d-axis and q-axis are analytically calculated by current distribution coefficients, two computational models that can accurately predict iron loss resistance under the condition of known and unknown hysteresis and eddy current loss parameters are derived and proposed for the first time. Finally, experimental comparison with conventional methods such as \u0000<inline-formula> <tex-math>$i_{mathrm { d}}{=}0$ </tex-math></inline-formula>\u0000 and MTPA proves validity and superiority for our proposed method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4924-4928"},"PeriodicalIF":4.0,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141529910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Triple Phase Shift Modulation Scheme for Bidirectional Wireless Power Transfer Systems With Efficiency Maximization 效率最大化的双向无线电力传输系统三重相移调制方案
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-06-27 DOI: 10.1109/TCSII.2024.3420095
Jianghua Lu;Shixiong Sun;Haojie Ke;Guorong Zhu
{"title":"Triple Phase Shift Modulation Scheme for Bidirectional Wireless Power Transfer Systems With Efficiency Maximization","authors":"Jianghua Lu;Shixiong Sun;Haojie Ke;Guorong Zhu","doi":"10.1109/TCSII.2024.3420095","DOIUrl":"10.1109/TCSII.2024.3420095","url":null,"abstract":"This brief proposed an optimal and unified triple phase shift (TPS) control strategy for some widely-used bidirectional inductive power transfer (BIPT) systems. The phase shift angles of the full-bridge converters at both the primary and secondary sides, as well as that between them, are developed and regulated dynamically to get zero-voltage switching (ZVS) operation over the full range of power level. Additionally, the resonant tank current is optimized to minimize the system conduction loss. Therefore, the proposed BIPT system will benefit with its efficiency maximization in terms of possible voltage gain (i.e., Buck, Boost, and Unity). A series-series (S-S) compensated BIPT system is taken as an example and a 250W GaN-based experimental prototype is built to verify the proposed modulation scheme. Its peak efficiency is up to 95.1% and increased by 1.9% compared with the conventional TPS control method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5029-5033"},"PeriodicalIF":4.0,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141524444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nullor-Based Inversion of MIMO Circuital Systems 基于 Nullor 的多输入多输出电路系统反演
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-06-27 DOI: 10.1109/TCSII.2024.3419907
Oliviero Massi;Riccardo Giampiccolo;Alberto Bernardini
{"title":"Nullor-Based Inversion of MIMO Circuital Systems","authors":"Oliviero Massi;Riccardo Giampiccolo;Alberto Bernardini","doi":"10.1109/TCSII.2024.3419907","DOIUrl":"10.1109/TCSII.2024.3419907","url":null,"abstract":"Nullors have already demonstrated their efficacy in designing the inverse of a given circuital system in the Single-Input Single-Output (SISO) case. These inverse systems have found diverse applications, ranging from analog electronics, particularly in chaos synchronization, to digital signal processing, for the development of transducer virtualization algorithms. In this brief, we extend the nullor-based circuit inversion approach to the Multiple-Input Multiple-Output (MIMO) case. In particular, we generalize Leuciuc’s theorem, originally applicable to SISO systems, to the class of MIMO circuital systems whose input and output signals share the same vector space dimension. The validity of the presented theoretical result is verified in different linear and nonlinear application scenarios.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5054-5058"},"PeriodicalIF":4.0,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141524443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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