IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第10页

Reachable Set Estimation of Memristive Inertial Neural Networks 记忆性惯性神经网络的可达集估计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-23 DOI: 10.1109/TCSII.2025.3572855

Yuxin Jiang;Song Zhu;Shiping Wen;Chaoxu Mu

引用次数: 0

Hardware Aware Polyalphabetic Cipher Design Using Spin-Orbit Torque Controlled Spintronic Devices 基于自旋轨道转矩控制的自旋电子器件的硬件感知多字母密码设计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-22 DOI: 10.1109/TCSII.2025.3572616

Divyanshu Divyanshu;Aijaz H. Lone;Meng Tang;Camelia Florica;Selma Amara;Gianluca Setti

引用次数: 0

An 88.96 dB HDR CMOS Image Sensor Modeled on Visual Neuronal Response 基于视觉神经元响应的88.96 dB HDR CMOS图像传感器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-21 DOI: 10.1109/TCSII.2025.3572086

Jingjing Liu;Yuchen Wang;Bingjun Xiong;Zhipeng Li;Liang Shi;Junhao He

{"title":"An 88.96 dB HDR CMOS Image Sensor Modeled on Visual Neuronal Response","authors":"Jingjing Liu;Yuchen Wang;Bingjun Xiong;Zhipeng Li;Liang Shi;Junhao He","doi":"10.1109/TCSII.2025.3572086","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3572086","url":null,"abstract":"This brief proposes a low-voltage low-power high dynamic range (HDR) CMOS image sensor (CIS) with visual neuronal responses (VNR) tailored for IoT applications, especially biomedical scenarios, which demand low power consumption and limited transmission bandwidth. The proposed CIS modeled on the nonlinear compression characteristics of illumination in the visual nervous system to enhance the dynamic range (DR). By employing a dynamic readout of pixel signals and comparing with a reference ramp voltage, the output of the proposed CIS conforms to the Naka-Rushton function, which describes the response features of visual neurons. The proposed CIS adopts a column-parallel architecture to enable simultaneous exposure, readout, and quantization of pixels in each row, combined with several low-power reset circuits to reduce image lag and inter-row crosstalk. A <inline-formula> <tex-math>$126times 64$ </tex-math></inline-formula> HDR CIS with a <inline-formula> <tex-math>$6.6~mu $ </tex-math></inline-formula>m pixel pitch was fabricated using a 180 nm CMOS technology. Measurement results show a DR exceeding 88.96 dB, with a total power consumption of <inline-formula> <tex-math>$18.62~mu $ </tex-math></inline-formula>W at 60 fps and 0.8 V supply.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"878-882"},"PeriodicalIF":4.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Visual-Cortex-Mimetic Tiny Neuromorphic Vision Processor Based on Reconfigurable Cortical Neuron Unit 基于可重构皮质神经元单元的仿视觉皮质微型神经形态视觉处理器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-19 DOI: 10.1109/TCSII.2025.3571598

Mingju Chen;Junxian He;Haibing Wang;Tengxiao Wang;Haoran Gao;Liyuan Liu;Ying Wang;Cong Shi

{"title":"A Visual-Cortex-Mimetic Tiny Neuromorphic Vision Processor Based on Reconfigurable Cortical Neuron Unit","authors":"Mingju Chen;Junxian He;Haibing Wang;Tengxiao Wang;Haoran Gao;Liyuan Liu;Ying Wang;Cong Shi","doi":"10.1109/TCSII.2025.3571598","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3571598","url":null,"abstract":"Edge visual systems demand high energy-efficiency vision processors like neuromorphic hardware leveraging spike-based computations. But their disability of directly interacting with non-spike information in the real world requests additional components to execute image pre-processing, spike encoding and decoding, severely increasing overall system cost, energy and latency. To overcome such drawback, this brief proposes a tiny neuromorphic vision processor which emulates functional regions along the ventral pathway in the visual cortex. It performs image pre-processing, spike encoding, spike-based feature extraction and classification, spike decoding as well as decision making on a single chip. To reduce hardware resources, our processor builds on a reconfigurable cortical neuron (RCN) unit, which runs different neuron models for different visual cortex regions in a time-multiplexing fashion. It also embeds biological learning circuits to better adapt the processor to dynamic edge scenarios. Our neuromorphic processor was prototyped on a very-low-cost Xilinx Zynq-7010 device. On the MNIST dataset, it exhibited a real-time inference speed of 696 frame/s covering image pre-processing to final decision and a high on-chip learning accuracy of 97.12%, while only delivering a power consumption as low as 118 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"943-947"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Reduced Capacitance H-9 Five-Level Switched Boost Capacitor Transformerless Inverter 小电容H-9五电平开关升压电容无变压器逆变器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-19 DOI: 10.1109/TCSII.2025.3552764

Md Sartaj Ahmed;Ravi Raushan;Md Waseem Ahmad

{"title":"A Reduced Capacitance H-9 Five-Level Switched Boost Capacitor Transformerless Inverter","authors":"Md Sartaj Ahmed;Ravi Raushan;Md Waseem Ahmad","doi":"10.1109/TCSII.2025.3552764","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552764","url":null,"abstract":"Transformerless switched capacitor-based multi-level inverters are well-known for their applications in industrial and renewable energy systems. The primary features of a switched capacitor-based transformerless inverter should be minimizing leakage current for safety and minimizing ripple current for efficiency and reliability. This brief proposes a new single-stage, single-phase, five-level H-9-based transformerless inverter for standalone PV systems. This H-9 inverter, utilizes nine switches to produce the desired output voltage levels. It achieves boost functionalities by combining the switched capacitor (SC) unit with the switched boost (SB) unit in a single design. This topology effectively mitigates the leakage current by virtually grounding the load terminal through the filter capacitor. Furthermore, the ripple current of the capacitors in the switched-capacitor unit is minimized, and it is inherently balanced. To this end, the feasibility of utilizing the modulation technique for control is demonstrated, and the relevant results are experimentally validated using a laboratory prototype of the proposed converter.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"788-792"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm 具有转移训练算法的28纳米无mfcc关键字可切换关键字定位系统

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-19 DOI: 10.1109/TCSII.2025.3552970

Fei Tan;Yujia Wang;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak

{"title":"A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm","authors":"Fei Tan;Yujia Wang;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3552970","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552970","url":null,"abstract":"In this brief, we propose an ultra-low-power mel frequency cepstral coefficients (MFCCs)-free keyword switchable KWS system that supports ten sub-classifiers (2 keywords each, 20 keywords in total) through a time-domain transferred training convolutional neural network (TT-CNN). The proposed TT-CNN reduces the model size by sharing the first two convolutional layers with all the keywords with a transferred training approach. Hence, the power budget for memory and computation is largely reduced. The TT-CNN supports flexible keyword demand in different scenes by selecting different kernels in the custom-designed 5T-SRAM. The time-domain feature of the proposed TT-CNN avoids the power-hungry feature extractor (FEx), further reducing the overall power consumption. To benchmark with the state-of-the-art, we demonstrated the proposed system with two cascaded scalable 10-Class KWS chips in 28nm CMOS. Our design achieves a high accuracy of 92.8% on 20 keywords from the Google speech command dataset (GSCD). It also shows that the memory overhead for each keyword can be reduced by 20% with the lowest reported 20-class KWS power consumption of <inline-formula> <tex-math>$1.2~mu $ </tex-math></inline-formula> W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"803-807"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 4 × 4 Fully Integrated RF Transceiver in 6 GHz Frequency Band With Single-Channel Bandwidth of 400 MHz and PHY Data-Rate of 8.8 Gbps 6ghz频段4 × 4全集成射频收发器，单通道带宽400mhz， PHY数据速率8.8 Gbps

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-18 DOI: 10.1109/TCSII.2025.3552472

Youming Zhang;Fengyi Huang;Xusheng Tang;Junjie Li;Zhennan Wei;Yunqi Cao

{"title":"A 4 × 4 Fully Integrated RF Transceiver in 6 GHz Frequency Band With Single-Channel Bandwidth of 400 MHz and PHY Data-Rate of 8.8 Gbps","authors":"Youming Zhang;Fengyi Huang;Xusheng Tang;Junjie Li;Zhennan Wei;Yunqi Cao","doi":"10.1109/TCSII.2025.3552472","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552472","url":null,"abstract":"This brief presents a fully integrated CMOS <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> MIMO RF transceiver (TRX) with single-channel bandwidth (BW) of 400 MHz in the 6 GHz band (5.925-7.125 GHz). In the receiver (RX) frontend, an improved noise-canceling low noise amplifier (LNA) and a cross-coupled transconductance <inline-formula> <tex-math>$(G_{M})$ </tex-math></inline-formula> with IIP2 enhancement is implemented. In the transmitter (TX) frontend, a power amplifier driver (PAD) is integrated with cascade AM-PM distortion compensation to eliminate the AM-PM distortion. A hierarchical LO distribution network is employed in the 1-to-4 LO distribution chain to enhance the consistency among the LO branches. The single-chip TRX is reconfigurable for TDD/FDD operation, with the RX exhibiting a noise figure of 3.5-4.1 dB, a gain control range of 45 dB with 1 dB step and ±0.2 dB gain flatness. The TX output spectrum exhibits >32 dBc signal to noise ratio (SNR). The RX and TX error vector magnitudes (EVMs) are −30.2 dB and −30.5 dB, respectively, with 160 MHz BW 256QAM. A TX-to-RX PHY data-rate of 8.8 Gbps based on <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> MIMO is achieved, with other major parameters comparable to the prior arts without resorting to digital calibration circuits.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"723-727"},"PeriodicalIF":4.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Adaptive Body Tuned Sense Amplifier for Energy Efficient In-Memory Computing 一种用于节能内存计算的自适应体调谐感测放大器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-17 DOI: 10.1109/TCSII.2025.3551822

Bibhudutta Satapathy;Karan Jadhav;Amandeep Kaur

引用次数: 0

OnSort: An O(n) Comparison-Free Sorter for Large-Scale Dataset With Parallel Prefetching and Sparse-Aware Mechanism OnSort：基于并行预取和稀疏感知机制的大规模数据集O(n)无比较排序器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-16 DOI: 10.1109/TCSII.2025.3570797

Muxuan Gao;Juntao Jiang;Shuangming Lei;Huifeng Wu;Jun Chen;Yong Liu

{"title":"OnSort: An O(n) Comparison-Free Sorter for Large-Scale Dataset With Parallel Prefetching and Sparse-Aware Mechanism","authors":"Muxuan Gao;Juntao Jiang;Shuangming Lei;Huifeng Wu;Jun Chen;Yong Liu","doi":"10.1109/TCSII.2025.3570797","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3570797","url":null,"abstract":"This brief proposes OnSort, a parallel comparison-free sorting architecture with <inline-formula> <tex-math>$mathcal {O}(n)$ </tex-math></inline-formula> time complexity, utilizing the SRAM structure to support large-scale datasets efficiently. The performance of existing comparison-free sorters is limited by uneven value distribution and variable element numbers. To address these issues, we introduce a parallel prefetching strategy to accelerate the indexing process and a sparse-aware mechanism to narrow the indexing search range. Furthermore, OnSort implements streaming execution through a pipelined design, thereby optimizing the previously overlooked latency of the counting phase. Experimental results show that, under the configuration of sorting 65,536 16-bit data elements, OnSort achieves a <inline-formula> <tex-math>$1.97times $ </tex-math></inline-formula> speedup and a <inline-formula> <tex-math>$22.6times $ </tex-math></inline-formula> throughput-to-area ratio compared to the existing design. The source code is available at <uri>https://github.com/gmx-hub/OnSort</uri>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"933-937"},"PeriodicalIF":4.0,"publicationDate":"2025-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Energy-Efficient Capacitance-to-Digital Converter With Top and Bottom Plate Sampling for Pressure Sensors 一种具有顶底板采样的压力传感器高效电容-数字转换器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-14 DOI: 10.1109/TCSII.2025.3551361

Qingjiang Xia;Fei Zhou;Yuze Niu;Mingzhong He;Wengao Lu;Yacong Zhang;Zhongjian Chen

{"title":"An Energy-Efficient Capacitance-to-Digital Converter With Top and Bottom Plate Sampling for Pressure Sensors","authors":"Qingjiang Xia;Fei Zhou;Yuze Niu;Mingzhong He;Wengao Lu;Yacong Zhang;Zhongjian Chen","doi":"10.1109/TCSII.2025.3551361","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3551361","url":null,"abstract":"This brief presents a 12-bit low-power successive-approximation-register (SAR) capacitance-to-digital converter (CDC) for capacitive pressure sensors. It adopts a capacitance-to-voltage front-end (CVFE) scheme to decouple the capacitive digital-to-analog converter (CDAC) from the sensor capacitor, enabling a large swing of the SAR analog-to-digital converter (ADC) and a wide capacitance sensing range. To improve power efficiency, this brief proposed a top and bottom sampling (TBS) for CVFE circuit to achieve a single-ended sampling while differential conversion. The TBS includes only one sampling phase, which relaxes the amplifier’s bandwidth requirements, thereby reducing the power consumption of the CVFE. The prototype chip was fabricated using a 180-nm CMOS process. The measured capacitance resolution is 1.76 fF and the measurement capacitance range is from 0.63 pF to 38.37 pF. The proposed CDC consumes <inline-formula> <tex-math>$3.90~mu $ </tex-math></inline-formula>W with a <inline-formula> <tex-math>$128~mu $ </tex-math></inline-formula>s conversion time, bringing a power efficiency of 80.6 fJ/conversion-step.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"678-682"},"PeriodicalIF":4.0,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0