IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第10页

A Hybrid Signal and Model-Based Fault Diagnostic Strategy for Current Sensors in Six-Phase Sinusoidal Doubly Salient Electro-Magnetic Machines 基于混合信号和模型的六相正弦双凸极电机电流传感器故障诊断策略

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2025-12-19 DOI: 10.1109/TCSII.2025.3646263

Xingwei Zhou;Wentao Pan;Xiang Chang;Chengjia Lu;Xu Wang;Li Zhang;Xing Zhao

{"title":"A Hybrid Signal and Model-Based Fault Diagnostic Strategy for Current Sensors in Six-Phase Sinusoidal Doubly Salient Electro-Magnetic Machines","authors":"Xingwei Zhou;Wentao Pan;Xiang Chang;Chengjia Lu;Xu Wang;Li Zhang;Xing Zhao","doi":"10.1109/TCSII.2025.3646263","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3646263","url":null,"abstract":"To enhance the diagnosis capability of current sensor faults in symmetrical six-phase sinusoidal doubly salient electromagnetic machines (SDSEM) system, a hybrid signal and model-based diagnosis strategy is proposed in this brief. At first, the current sensor fault operating characteristic is investigated, and the features of z1-z2 subspace currents are analyzed in detail. Then, on the base of the currents feature, a novel phase current sensor fault diagnostic strategy is proposed, most of the faulty phase current sensor can be diagnosed according to the changes in the diagnosis signals which are constructed from z1-z2 subspace currents. In further, to distinguish the blind spot caused by the symmetrical windings with 60° phase shift, an easy-implemented model-based current observer is designed, the faulty phase current sensor can be further identified according to the difference between the sampled and observed currents. With the combined hybrid signal and model-based diagnosis strategy, accurate discriminations of phase current sensor fault are desired to be achieved. The multiple experiments validate the correctness and the feasibility of the proposed methods.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"328-332"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148482759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 16-to-24.9 GHz Dual-Core Dual-Mode Noise-Circulating VCO Using Single-Phase Switch With FOMT of 209.0 dBc/Hz 采用单相开关的16 ~ 24.9 GHz双核双模噪声循环压控振荡器，fomo为209.0 dBc/Hz

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-02 DOI: 10.1109/TCSII.2026.3669392

Wanqing Wu;Xinyi Zhang;Ning Zhang;Ruiyong Xiang;Haigang Feng;Zhihua Wang

{"title":"A 16-to-24.9 GHz Dual-Core Dual-Mode Noise-Circulating VCO Using Single-Phase Switch With FOMT of 209.0 dBc/Hz","authors":"Wanqing Wu;Xinyi Zhang;Ning Zhang;Ruiyong Xiang;Haigang Feng;Zhihua Wang","doi":"10.1109/TCSII.2026.3669392","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3669392","url":null,"abstract":"This brief presents a dual-core dual-mode noise-circulating voltage-controlled oscillator (VCO) with a wide frequency tuning range (FTR) and low phase noise (PN) for K-band applications. Specifically, the VCO employs an optimized capacitively coupled noise-circulating structure to operate in the K-band while suppressing the thermal noise contribution of the transistors. A low-noise dual-mode inductor is proposed. By utilizing a single-phase switch network, it achieves a wide FTR without degrading the phase noise performance, eliminating the detrimental effects of mode-switching. Fabricated in a 65-nm CMOS process, the VCO occupies an active core area of 0.096 mm2. When operating at 16.32 GHz, the VCO achieves -148.4 dBc/Hz at 10 MHz offset frequency after the frequency is divided by three. While the power consumption is 4.9 mW from a 0.9 V supply, the resulting figure-of-merit (FOM) is 196.2 dBc/Hz. With a FTR from 16 GHz to 24.9 GHz (43.5%), the VCO achieves a FOM with tuning range (FOM<inline-formula> <tex-math>${}_{mathrm {T}}$ </tex-math></inline-formula>) of 209.0 dBc/Hz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"508-512"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 9-b 3–7.5-GHz 2.53-LSB-INL High-Linearity Phase Interpolator With CMOS-Signal-Targeted Calibration in 65-nm for High-Speed Data Links 用于高速数据链路的9-b 3- 7.5 ghz 2.53-LSB-INL高线性相位插补器，65纳米cmos信号定向校准

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-30 DOI: 10.1109/TCSII.2026.3678518

Zexin Su;Junyan Zhu;Chang Liu;Tao Hu;Yao Liu;Jixin Chen;Franco Maloberti;Bo Li

{"title":"A 9-b 3–7.5-GHz 2.53-LSB-INL High-Linearity Phase Interpolator With CMOS-Signal-Targeted Calibration in 65-nm for High-Speed Data Links","authors":"Zexin Su;Junyan Zhu;Chang Liu;Tao Hu;Yao Liu;Jixin Chen;Franco Maloberti;Bo Li","doi":"10.1109/TCSII.2026.3678518","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3678518","url":null,"abstract":"In this work, a high-linearity 8-phase CMOS-targeted-calibration phase interpolator (PI) is proposed. In classical current-mode logic (CML) PIs, improvement efforts primarily focus on correcting the CML signal phase error, while neglecting a significant transfer phase error that occurs when converting the CML signal to the CMOS signal, resulting from the amplitude differences of CML phases and the threshold variation of the transfer circuit. To address this problem, a CMOS-signal-targeted calibration technique is proposed, which considers both error sources: the CML inherent phase error and the transfer error from CML to CMOS. The phase error will be extracted directly from the final CMOS signal, and the calibration will be implemented according to this total phase error. In the proposed calibration scheme, the specific CMOS phases (22.5° phase group) are adopted as phase references, which have identical CML amplitudes before CMOS to avoid the transfer error; and other CMOS phases will be calibrated based on the references. Fabricated in a 65nm CMOS process, the chip achieves an integral non-linearity (INL) of less than 2.53 LSB and a differential non-linearity (DNL) of less than 0.77 LSB with 9 bits resolution across a frequency range of 3 to 7.5 GHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"523-527"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Optimized Dead-Time for Soft-Switching in CCM of Current-Fed Interleaved Boost Converter 电流馈电交错升压变换器CCM软开关死区优化

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-26 DOI: 10.1109/TCSII.2026.3677874

Dinh Phuc Nguyen;Weize Xu;Chun-Jen Yao;Huang-Jen Chiu

引用次数: 0

A 0.95-ppm/°C Voltage Reference With Second-Order Core-Injection Sub-Ranging Compensation 一个0.95 ppm/°C电压基准与二阶堆芯注入子量程补偿

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-04-06 DOI: 10.1109/TCSII.2026.3681102

Wenzhao Lv;Pengxu Ren;Dan Ye;Chao Jiang;Zhuojun Chen

引用次数: 0

A 2-to-18 GHz Power Amplifier With 31-dB Gain and ±0.5 dB In-Band Ripple Using Segmented Matching in 0.18-μm SiGe BiCMOS 基于0.18 μm SiGe BiCMOS的31 dB增益和±0.5 dB带内纹波的2 ~ 18 GHz功率放大器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-03-06 DOI: 10.1109/TCSII.2026.3671329

Jianbing Liu;Fanyi Meng

{"title":"A 2-to-18 GHz Power Amplifier With 31-dB Gain and ±0.5 dB In-Band Ripple Using Segmented Matching in 0.18-μm SiGe BiCMOS","authors":"Jianbing Liu;Fanyi Meng","doi":"10.1109/TCSII.2026.3671329","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3671329","url":null,"abstract":"This brief proposes an ultra-wideband power amplifier (PA) covering the <italic>S-C-X-Ku <bold>bands, realized in the HHGRACE 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula><bold>m SiGe BiCMOS process. A frequency-domain characteristic-based segmented matching strategy is adopted, which leverages the substantial frequency-dependent variation of inductive/capacitive reactance within the operating band—particularly the inductive reactance of choke coils—to separately construct targeted low- and high-frequency impedance matching networks. Measurement results show that the PA achieves an ultra-wide bandwidth of 2–18 GHz (160% fractional bandwidth) with a gain of 31 dB at 10 GHz and a small gain ripple of ±0.5 dB. It maintains <inline-formula> <tex-math>$S$ </tex-math></inline-formula><inline-formula> <tex-math>${}_{mathbf {11}}$ </tex-math></inline-formula><-<bold>10 dB and <inline-formula> <tex-math>$S$ </tex-math></inline-formula><inline-formula> <tex-math>${}_{mathbf {22}}$ </tex-math></inline-formula>< -<bold>8.5 dB across the band, with a 1-dB compression point (<italic>OP<inline-formula> <tex-math>${}_{mathbf {1dB}}$ </tex-math></inline-formula>) of 14.7 dBm, a maximum saturated output power (<inline-formula> <tex-math>${P} _{mathbf {SAT}}$ </tex-math></inline-formula>) of 15.7 dBm and a peak power-added efficiency (<italic>PAE) of 14.88% at 8 GHz. The PA features a compact core area of 0.245 mm2. Compared to state-of-the-art designs, the proposed PA realizes ultra-wide bandwidth, high gain, flat gain response, and compact size, making it suitable for modern ultra-wideband communication systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 5","pages":"548-552"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Data-Driven Secondary Frequency Restoration and SoC Balancing Control of ESSs With Multiple Faults Under Event-Triggered Communication 事件触发通信下多故障ess的数据驱动次频恢复与SoC均衡控制

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2025-11-24 DOI: 10.1109/TCSII.2025.3636156

Zhenjian Xie;Yi Tang

{"title":"Data-Driven Secondary Frequency Restoration and SoC Balancing Control of ESSs With Multiple Faults Under Event-Triggered Communication","authors":"Zhenjian Xie;Yi Tang","doi":"10.1109/TCSII.2025.3636156","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3636156","url":null,"abstract":"This brief focuses on the secondary frequency restoration and state-of-charge (SoC) balancing control problem for energy storage systems (ESSs) with multiple faults under event-triggered communications. Specifically, a data-driven estimator is first designed by using the temporal convolutional network (TCN) to estimate the communication faults. Then, a <inline-formula> <tex-math>$k$ </tex-math></inline-formula>-step fault estimator is introduced to estimate the unknown actuator faults such that the estimation error converges to zero as the number of estimation steps increases to infinity. Based on these estimators, an event-triggered distributed secondary fault-tolerant controller is designed by introducing a dynamic event-triggered mechanism for each ESS. Different from existing secondary control results on ESSs, the developed strategy can achieve both frequency restoration and SoC balancing with restricted communication under multiple faults. It is shown that both frequency restoration and the SoC balancing objectives can be achieved under the developed method. Finally, a real-time experiment is introduced to show the effectiveness of the developed method.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"288-292"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148483969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact GaN MMIC Doherty Power Amplifier Module Employing Phase-Reduced Load Modulation Network 采用减相负载调制网络的紧凑GaN MMIC多尔蒂功率放大器模块

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-01-23 DOI: 10.1109/TCSII.2026.3657512

Shuang Liu;Jingzhou Pang;Ruibin Gao;Zhijiang Dai;Weimin Shi;Shichang Chen;Mingyu Li

{"title":"Compact GaN MMIC Doherty Power Amplifier Module Employing Phase-Reduced Load Modulation Network","authors":"Shuang Liu;Jingzhou Pang;Ruibin Gao;Zhijiang Dai;Weimin Shi;Shichang Chen;Mingyu Li","doi":"10.1109/TCSII.2026.3657512","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3657512","url":null,"abstract":"This brief presents the design and implementation of a compact high-efficiency Doherty power amplifier (DPA) module employing a modified load modulation network (LMN) with reduced-phase characteristic. The analysis of different parameter combinations of LMN phase and complex combining impedance is performed and provides a phase-reduced LMN that can be designed, thereby effectively minimizing the chip size and achieving a compact design. Fabricated in a 0.12-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m Gallium nitride (GaN) process, the designed DPA integrates the input network and the phase-reduced LMN into a <inline-formula> <tex-math>$1.5times 1.5~{{text {mm}}^{{2}}}$ </tex-math></inline-formula> monolithic microwave integrated circuit (MMIC), while the post-matching network (PMN) is implemented on a printed circuit board (PCB). Prototype testing within the 2.95–3.7 GHz operation band shows a saturation efficiency of 61.36%–71.17%, a saturated output power of 39.19–39.92 dBm, and an efficiency of 46.35%–53.69% at the 8 dB power back-off (PBO) point. Modulated signal testing was conducted using a OFDM signal with an 8 dB peak-to-average power ratio (PAPR) and an 80 MHz bandwidth. After digital pre-distortion (DPD) processing, the adjacent channel power ratio (ACPR) was better than -45.6 dBc.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"268-272"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148487283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 18.3–38.3-GHz Power Amplifier With Adaptive Dual-Voltage-Path Crossing Cold-FET Pair Achieving 22.7-dBm Psat and 31.9% PAE 一种18.3 - 38.3 ghz功率放大器的自适应双电压通路交叉冷场效应管对实现22.7 dbm Psat和31.9% PAE

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-01-20 DOI: 10.1109/TCSII.2026.3656380

Xuelong Chen;Haoshen Zhu;Zhuohang Liang;Jingye Zhang;Dingyuan Zeng;Song Chen;Quan Xue

{"title":"A 18.3–38.3-GHz Power Amplifier With Adaptive Dual-Voltage-Path Crossing Cold-FET Pair Achieving 22.7-dBm Psat and 31.9% PAE","authors":"Xuelong Chen;Haoshen Zhu;Zhuohang Liang;Jingye Zhang;Dingyuan Zeng;Song Chen;Quan Xue","doi":"10.1109/TCSII.2026.3656380","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3656380","url":null,"abstract":"This brief presents a wideband linear CMOS power amplifier (PA) for 5G millimeter wave (mm-wave) applications. In order to improve linearity, this PA adopts an analog pre-distortion (APD) linearizer using an adaptive dual-voltage-path crossing cold-FET pair (ADCCP). The proposed ADCCP is implemented by connecting the drain and gate of differential cold-FET mutually in a crossing manner, which can enhance the equivalent impedance of cold-FET significantly. Moreover, an adaptive bias circuit (ABC) with dual-voltage-path is applied to control Vgs of ADCCP to transform the transistor from the saturation region to the turn-off region, which can further increase the equivalent impedance of the cold-FET to enhance linearity. In addition, input and interstage transformers are meticulously designed using gain shaping technique to ensure wideband performance. The implemented PA achieves a 3-dB bandwidth of 18.3-38.3 GHz, with the peak gain of 20.8 dB, peak saturated output power (Psat) of 22.7 dBm, and peak power-added efficiency (PAE) of 31.9%. Wideband output power and efficiency performance was achieved with OP<inline-formula> <tex-math>${}_{text {1dB}} geq 21$ </tex-math></inline-formula> dBm, PAE<inline-formula> <tex-math>${}_{text {1dB}} geq 22$ </tex-math></inline-formula>% in 21.5-36.1 GHz (50.7% FBW).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"248-252"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148483871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Depth-First Iterative Number-Theoretic Transform Architecture for CKKS Bootstrapping on FPGA 基于FPGA的CKKS自举深度优先迭代数论变换体系

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-01-15 DOI: 10.1109/TCSII.2026.3654894

Hien Nguyen;Samsul Huda;Yasuyuki Nogami;Tuy Tan Nguyen

{"title":"A Depth-First Iterative Number-Theoretic Transform Architecture for CKKS Bootstrapping on FPGA","authors":"Hien Nguyen;Samsul Huda;Yasuyuki Nogami;Tuy Tan Nguyen","doi":"10.1109/TCSII.2026.3654894","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3654894","url":null,"abstract":"Despite the potential of fully homomorphic encryption as a solution to privacy-preserving calculations, it faces limitations in practical deployment, especially in Cheon-Kim-Kim-Song (CKKS) bootstrapping, where large-scale polynomial computations require a lot of computing resources. Conventional number-theoretic transform (NTT) implementations often encounter high memory usage, limited local data, and less scalable hardware, especially in multi-prime scenarios. We propose a depth-first search (DFS) strategy for NTT computation and a DFS-based mixed-radix for performing CKKS bootstrapping. This proposed design combines local buffer reuse with a modular, stack-based control scheme, which reduces unnecessary memory access and prevents redundant hardware replication among primes, achieving a high area-time efficiency. On Xilinx Artix UltraScale FPGA, this design executes a complete 54-prime, <inline-formula> <tex-math>$2^{17}$ </tex-math></inline-formula>-point NTT in 3.33 milliseconds, relying less on logic and BRAM than similar solutions and yielding better area-time-product and scalability compared to the latest state-of-the-art designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"303-307"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148483882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0