IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第10页

A 38.4 nW, 1.2 V, 250-Hz, 2nd-Order gm – C LPF With Degenerative SCP Transconductors Achieving 800-mVPP Input Range and 82.1- μVrms IRN for ECG Acquisition 一款 38.4 nW、1.2 V、250 Hz、二阶 gm-C LPF，采用去势 SCP 晶体管，可实现 800 mVPP 输入范围和 82.1-μ Vrms IRN，用于心电图采集

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-29 DOI: 10.1109/TCSII.2024.3451494

Surachoke Thanapitak;Prajuab Pawarangkoon;Wanlop Surakampontorn;Rafidah Ahmad;Ruhaifi Abdullah Zawawi;Asrulnizam Abd. Manaf;Suriya Adirek;Chaiyan Chanapromma

{"title":"A 38.4 nW, 1.2 V, 250-Hz, 2nd-Order gm – C LPF With Degenerative SCP Transconductors Achieving 800-mVPP Input Range and 82.1- μVrms IRN for ECG Acquisition","authors":"Surachoke Thanapitak;Prajuab Pawarangkoon;Wanlop Surakampontorn;Rafidah Ahmad;Ruhaifi Abdullah Zawawi;Asrulnizam Abd. Manaf;Suriya Adirek;Chaiyan Chanapromma","doi":"10.1109/TCSII.2024.3451494","DOIUrl":"10.1109/TCSII.2024.3451494","url":null,"abstract":"In this brief, a \u0000<inline-formula> <tex-math>$2{^{text {nd}}}$ </tex-math></inline-formula>\u0000-order \u0000<inline-formula> <tex-math>$g_{mathrm { m}} - C$ </tex-math></inline-formula>\u0000 lowpass filter with a practical input linear range of \u0000<inline-formula> <tex-math>$400~{mathrm { mV}}_{mathrm { P}}$ </tex-math></inline-formula>\u0000 dedicated to ECG signal acquisition is proposed. This filter employs a degenerative source-coupled-pair circuit as a \u0000<inline-formula> <tex-math>$g_{mathrm { m}}$ </tex-math></inline-formula>\u0000 cell. It enhances the linear input range by a factor of \u0000<inline-formula> <tex-math>$times 4$ </tex-math></inline-formula>\u0000 compared with the source follower filter. Additionally, to mitigate the effect of current source mismatch, a dynamic element matching technique is applied. By doing so, HD2 is suppressed more than 1.5 dB over the entire passband frequency. This proposed filter is implemented in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m CMOS process. It offers a 250-Hz bandwidth with input-referred noise and a dynamic range of \u0000<inline-formula> <tex-math>$82.1~mu {mathrm { V}}_{mathrm {mathrm {rms}}}$ </tex-math></inline-formula>\u0000 and 67.34 dB, respectively. The power consumption of 38.4 nW is achieved with a 1.2 V supply. Compared with other recent nano-power filters, the proposed filter provides the highest linear input range with competitive Figure-of-Merit to the top-tier designs. It is therefore beneficial to the practical implementation of a low-power ECG acquisition system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"3-7"},"PeriodicalIF":4.0,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Conservation of Total-Activity-Degree for Mix-Valued Logical Networks 混合值逻辑网络的总活动度守恒性

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-29 DOI: 10.1109/TCSII.2024.3452056

Lingling Wu;Wenying Hou;Xinrong Yang;Haitao Li

引用次数: 0

Stability Analysis of Amplidyne Electrical Systems With Time-Varying Delay via a Matrix-Injection Method 通过矩阵注入法分析具有时变延迟的放大器电气系统的稳定性

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-29 DOI: 10.1109/TCSII.2024.3451555

Hong-Jian Huang;Chuan-Ke Zhang;Li Jin;Hong-Zhang Wang;Zhe-Li Yuan

引用次数: 0

A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography 基于 RLWE 的密码学轻量级高效加密/解密协处理器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-29 DOI: 10.1109/TCSII.2024.3451971

Yushu Yang;Zihang Wang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang

{"title":"A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography","authors":"Yushu Yang;Zihang Wang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang","doi":"10.1109/TCSII.2024.3451971","DOIUrl":"10.1109/TCSII.2024.3451971","url":null,"abstract":"Lattice-based cryptography has experienced significant advancements in recent years due to its versatility and simplicity. The ring learning with errors (RLWE) problem is widely adopted in lattice-based cryptography. However, the polynomial multiplication is the performance bottleneck of RLWE-based cryptography, which requires further examination. In this brief, a lightweight and efficient encryption/decryption coprocessor for RLWE-based cryptography is proposed. The time complexity of the Schoolbook polynomial multiplication (SPM) is reduced from \u0000<inline-formula> <tex-math>${n}^{2}$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$ {n}^{ {2}} {/8}$ </tex-math></inline-formula>\u0000 by enhancing multiplication parallelism. Moreover, an optimized structure for the Compressed cumulative distribution table (CDT) Gaussian sampler is proposed, resulting in 22.2% reduction in storage resource. The proposed SPM structure demonstrates a \u0000<inline-formula> <tex-math>$2.3times $ </tex-math></inline-formula>\u0000 performance speedup and \u0000<inline-formula> <tex-math>$2.7times $ </tex-math></inline-formula>\u0000 hardware efficiency for the encryption core, compared with state-of-the-art SPM accelerators. Additionally, it achieves a \u0000<inline-formula> <tex-math>$2.4times $ </tex-math></inline-formula>\u0000 performance speedup and \u0000<inline-formula> <tex-math>$3.2times $ </tex-math></inline-formula>\u0000 improvements on hardware efficiency for the decryption core.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5004-5008"},"PeriodicalIF":4.0,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC RFSoC 上具有片上 Sign-Sign LMS 自适应和加载配置文件优化功能的离散多音有线收发器数据路径

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-27 DOI: 10.1109/TCSII.2024.3450695

Jaewon Lee;Seoyoung Jang;Donggeon Kim;Yujin Choi;Jong-Hyeok Yoon;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim

{"title":"A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC","authors":"Jaewon Lee;Seoyoung Jang;Donggeon Kim;Yujin Choi;Jong-Hyeok Yoon;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim","doi":"10.1109/TCSII.2024.3450695","DOIUrl":"10.1109/TCSII.2024.3450695","url":null,"abstract":"This brief presents a discrete multi-tone (DMT) wireline transceiver (TRX) datapath and introduces the RFSoC-based real-time hardware platform to quickly sweep the optimum bit and power loading profile constrained by the peak-to-average-power ratio (PAPR). The datapath is implemented based on 32-parallel multi-path delay feedback (MDF) fast Fourier transform (FFT)/inverse FFT (IFFT) processors to save resources, integrating with the sign-sign least mean square (SS-LMS) engine. The loading is computed for the channel signal-to-noise ratio (SNR) and PAPR. The platform consists of 2.048 GS/s data converters, the DMT datapath implemented on programmable logic (PL) running at 64 MHz, and the channel board. This system enables a quick bit-error-rate (BER) test at an order of 1.0E-9, accelerating the finding of optimal loading with realistic hardware effects and random clipping events. Experimental results show that the data rate could reach a maximum of 6.82 Gb/s at a BER of 5.7E-4 and a minimum BER of 3.7E-7 for a target data rate of 4.81 Gb/s with a channel exhibiting 16.3 dB insertion loss (IL) at Nyquist.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4889-4893"},"PeriodicalIF":4.0,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 190-217-GHz Frequency Multiplier Chain With 13.2 dB Conversion Gain in 65-nm CMOS 在 65 纳米 CMOS 中实现 13.2 dB 转换增益的 190-217-GHz 倍频器链

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-26 DOI: 10.1109/TCSII.2024.3449631

Hao Guo;Kaizhe Guo;Zhicheng Lin;Kam Man Shum;Chi Hou Chan

引用次数: 0

Precise Individual Illumination Control of Matrix LED With Bypass Gate Driver and 8-Bit PWM 利用旁路栅极驱动器和 8 位 PWM 对矩阵式 LED 进行精确的单独照明控制

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-23 DOI: 10.1109/TCSII.2024.3448489

Jonghyuk Chae;Jaehun Jeong;Byeongha Park;Seungju Lee;Jongmin Park;Jinwook Burm

引用次数: 0

A 5.4-7.4 GHz Ultra-Low Jitter Injection-Locked Frequency Tripler With 3rd Harmonic Current Boosting Input Buffer 带三次谐波电流增强输入缓冲器的 5.4-7.4 GHz 超低抖动注入锁定频率三倍频器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-20 DOI: 10.1109/TCSII.2024.3446728

Sonam Sadhukhan;Arpan Thakkar;Pranav Kumar;Saurabh Saxena

{"title":"A 5.4-7.4 GHz Ultra-Low Jitter Injection-Locked Frequency Tripler With 3rd Harmonic Current Boosting Input Buffer","authors":"Sonam Sadhukhan;Arpan Thakkar;Pranav Kumar;Saurabh Saxena","doi":"10.1109/TCSII.2024.3446728","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446728","url":null,"abstract":"We present a 5.4-to-7.4 GHz injection-locked frequency tripler (ILFT) with enhanced \u0000<inline-formula> <tex-math>$3^{rd}$ </tex-math></inline-formula>\u0000 harmonic injection using collector-to-base transformer-coupled input buffer. Regenerative feedback in the input buffer using a collector-to-base coupled transformer provides up to 2x improvement in the locking range of the ILFT compared to a conventional ILFT. Fabricated in \u0000<inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>\u0000 m BiCMOS technology, the tripler exhibits a jitter tracking bandwidth, \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000 of 20 MHz. Due to its optimal jitter tracking bandwidth, the tripler filters the input noise beyond the \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000 and effectively suppresses the free-running oscillator’s phase noise below \u0000<inline-formula> <tex-math>$omega _{JTB}$ </tex-math></inline-formula>\u0000. We achieve an output rms jitter of 33.6 fs for an input rms jitter of 68 fs over a bandwidth of [1k-100MHz]. The ILFT demonstrates a good sub-harmonic rejection ratio, SHRR of 51 dB and 48 dB for fundamental and second harmonic, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4693-4697"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator 带 2 位转换/周期时域比较器的 0.6 V 4-MS/s 异步 SAR ADC

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-20 DOI: 10.1109/TCSII.2024.3446534

Sang-Hun Lee;Won-Young Lee

引用次数: 0

Efficient Metastability Mitigation and Sub-Band Filtering in VCO-Based EEG Recording 基于 VCO 的脑电图记录中的高效转移性缓解和子带滤波器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-08-20 DOI: 10.1109/TCSII.2024.3446187

Zijian Tang;Chao Sun;Yuan Ma;Minqian Zheng;Chao Zhang;Zhixiong Ma;Tongfei Wang;Milin Zhang

{"title":"Efficient Metastability Mitigation and Sub-Band Filtering in VCO-Based EEG Recording","authors":"Zijian Tang;Chao Sun;Yuan Ma;Minqian Zheng;Chao Zhang;Zhixiong Ma;Tongfei Wang;Milin Zhang","doi":"10.1109/TCSII.2024.3446187","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3446187","url":null,"abstract":"This brief proposes an efficient structure for electroencephalogram (EEG) signal recording. A single-sample strategy is proposed to mitigate metastability issues in Voltage-Controlled Oscillator (VCO) Analog Front Ends (AFEs), offering timing margins of 14 phase cycles and simplifying the result arbitration logic to 1-bit multiplexing. Additionally, an analysis of existing EEG sub-band filter designs is presented, followed by an efficient band multiplexing serial multiplier structure that capitalizes on timing slacks. This design features a reduction in both the number of multipliers and the complexity of the multiplexing network. The proposed design was implemented using 40nm CMOS technology. The VCO-AFE demonstrates stable, error-free recordings with an input-referred noise (IRN) of \u0000<inline-formula> <tex-math>$0.66boldsymbol {mu }$ </tex-math></inline-formula>\u0000V\u0000<inline-formula> <tex-math>$boldsymbol {_{rms}}$ </tex-math></inline-formula>\u0000 within 0.5–60Hz, according to the measurement results. The proposed sub-band filter exhibits substantial savings of 11% and 51% in area and power, respectively, compared to prior work when scaled to the same technology node.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4999-5003"},"PeriodicalIF":4.0,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0