IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第9页

A 1.62 – 10-Gb/s CDR Using Wide-Range VCO With Linearized KVCO 使用宽范围VCO和线性化KVCO的1.62 - 10gb /s CDR

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-24 DOI: 10.1109/TCSII.2025.3532628

Dong-Seob Shin;Young-Chan Jang

引用次数: 0

A 74.3 dB SNDR 3rd-Order VCO-Based DSM With Built-In Passive Low-Pass Filter in 65 nm CMOS 基于74.3 dB SNDR、内置无源低通滤波器的65纳米CMOS三阶vco DSM

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-24 DOI: 10.1109/TCSII.2025.3533698

Shuqun Ding;Tianqi Xu;Yang Zhang;Xian Tang

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Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder 基于cmos的lpc解码器约束感知退火

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-22 DOI: 10.1109/TCSII.2025.3532665

Eslam Elmitwalli;Zeljko Ignjatovic;Selçuk Köse

引用次数: 0

A 0.35–0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS 一个0.35 - 0.5 V 0.0136-mm²12 -MHz数字锁频环路，线路灵敏度为1.06%/V

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-20 DOI: 10.1109/TCSII.2025.3531710

Dan Shi;Ka-Meng Lei;Rui P. Martins;Pui-In Mak

{"title":"A 0.35–0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS","authors":"Dan Shi;Ka-Meng Lei;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3531710","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3531710","url":null,"abstract":"This brief presents a fully integrated sub-0.5 V digital frequency-locked loop (DFLL) incorporating a clock-boosting RC network to secure frequency accuracy under ultra-low voltage (ULV) operation. It embodies 3 key features: 1) a clock-boosting RC network with a time constant <inline-formula> <tex-math>$tau $ </tex-math></inline-formula> = RC to set the nominal frequency, 2) a dynamic tail-boosted comparator with offset background calibration to facilitate operation in ULV regime, and 3) a hybrid digital-controlled oscillator (DCO) with resolution enhancement to uphold the frequency stability. Fabricated in 65-nm CMOS, the DFLL features a compact footprint of 0.0136 mm2 and consumes <inline-formula> <tex-math>$5.7~mu $ </tex-math></inline-formula> W under 0.35 V at room temperature. It achieves a line sensitivity of 1.06%/V across 0.35 to 0.5 V, and a frequency inaccuracy of 176 ppm/°C between −30 and 120 ° C. Benefitting from the offset calibration technique to reduce the inband noise, the DFLL demonstrates outstanding jitter <inline-formula> <tex-math>$Fo{mathrm { M}}_{mathrm { Jitter}}$ </tex-math></inline-formula> of −224.5 dB and Allan deviation floor of <5 ppm, showcasing exceptional frequency stability.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"459-463"},"PeriodicalIF":4.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.2-3 GHz Inductor-Less LNA Using Noise-Canceling and Dual-Resistor Feedback Technique 采用降噪和双电阻反馈技术的0.2- 3ghz无电感LNA

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-20 DOI: 10.1109/TCSII.2025.3531994

Junfan Yan;Wenjie Feng;Pei Qin;Haoshen Zhu;Yunfei Cao;Wenquan Che;Quan Xue

{"title":"A 0.2-3 GHz Inductor-Less LNA Using Noise-Canceling and Dual-Resistor Feedback Technique","authors":"Junfan Yan;Wenjie Feng;Pei Qin;Haoshen Zhu;Yunfei Cao;Wenquan Che;Quan Xue","doi":"10.1109/TCSII.2025.3531994","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3531994","url":null,"abstract":"In this brief, an inductor-less low-noise amplifier (LNA) that utilizes a noise-canceling technique along with dual-resistor feedback is proposed. The conventional single-resistor feedback structure exhibits a performance constraint that limits the relationship between power gain and input matching. In contrast, the dual-resistor feedback structure proposed in this brief overcomes this limitation, enabling both high gain and low noise while maintaining good input matching. The dual-resistor feedback configuration includes a local feedback resistor which enhances the gain. Additionally, the global feedback resistor directly connect the inputs and outputs of the circuit, thereby breaking the constraints between the properties through feedback. The proposed LNA fabricated in 65-nm CMOS technology exhibiting a minimal NF of 2.08 dB within a 3-dB bandwidth that spans from 0.25 to 2.83 GHz, along with a peak power gain of 16.53 dB. The circuit operates with a power consumption of 10.6 mW under a supply voltage of 1.1 V, while occupying a core area of only 0.012 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"469-473"},"PeriodicalIF":4.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A High-Accuracy Bandgap Reference With Compact Output Driver 具有紧凑型输出驱动器的高精度带隙基准

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-20 DOI: 10.1109/TCSII.2025.3531922

Haoyu Zhuang;Yizhan Li;Xingyu Wang;Liangchen Huang;Qiang Li

{"title":"A High-Accuracy Bandgap Reference With Compact Output Driver","authors":"Haoyu Zhuang;Yizhan Li;Xingyu Wang;Liangchen Huang;Qiang Li","doi":"10.1109/TCSII.2025.3531922","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3531922","url":null,"abstract":"A high-accuracy bandgap reference (BGR) is proposed in this brief. It employs various techniques, including base-current compensation and curvature correction, to enhance the accuracy of reference voltage. The proposed curvature correction is advantageous, since it is insensitive to process variations and reduces chip area, when compared to existing solutions. Additionally, the differential amplifiers are no longer needed in the proposed circuit, and thus it no longer has the problems of offset voltage and increased energy consumption. Besides, a compact output driver is incorporated to accommodate large load currents while ensuring a good load regulation. Additionally, an over-temperature shutdown scheme is realized to save energy at elevated temperatures. This brief is designed with a 180 nm BCD process. It realizes a temperature coefficient (TC) of smaller than 3 ppm/°C (typical) across a temperature range of <inline-formula> <tex-math>$- 40sim 85~^{circ }$ </tex-math></inline-formula>C and at a supply voltage of 7 V. Meanwhile, a 2.2 ppm/mA load regulation is obtained for load currents varying from 0 to 100 mA at a supply voltage of 11 V. A −98.3 dB power supply rejection ratio (PSRR) is also achieved at 1 Hz. When compared with other works, the highlight of this brief is a compact output driver, an over-temperature shutdown scheme, 2 times larger range of supply voltage of 5 to 11 V, and a good TC <inline-formula> <tex-math>$leq 3$ </tex-math></inline-formula> ppm/°C (typical).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"464-468"},"PeriodicalIF":4.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unraveling Negative Feedback Translations: Gains, Peaking, Stability, and Loop Variations 揭示负反馈转换：增益，峰值，稳定性和循环变化

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-17 DOI: 10.1109/TCSII.2025.3531242

Tiancheng Zhao;Gabriel A. Rincón-Mora

引用次数: 0

A 12.6-pJ/Conversion Temperature Sensor With 0.98-mV/K Temperature-Voltage Sensitivity 12.6 pj /转换温度传感器，温度电压灵敏度0.98 mv /K

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-16 DOI: 10.1109/TCSII.2025.3530257

Jiajun Tang;Xiyuan Tang

引用次数: 0

An 85.5% PCE and 99.31% TE Piezoelectric Energy Harvesting Interface With Sub-One-Cycle Sampling and Dual-Loop MPPT 基于亚一周期采样和双回路MPPT的85.5% PCE和99.31% TE压电能量收集界面

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-16 DOI: 10.1109/TCSII.2025.3530088

Xufeng Liao;Yiyang Wang;Yu Du;Shihao Xiao;Xincai Liu;Zhangming Zhu;Lianxi Liu

{"title":"An 85.5% PCE and 99.31% TE Piezoelectric Energy Harvesting Interface With Sub-One-Cycle Sampling and Dual-Loop MPPT","authors":"Xufeng Liao;Yiyang Wang;Yu Du;Shihao Xiao;Xincai Liu;Zhangming Zhu;Lianxi Liu","doi":"10.1109/TCSII.2025.3530088","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3530088","url":null,"abstract":"This brief presents a high power conversion efficiency (PCE) and tracking efficiency (TE) piezoelectric energy harvesting interface (PEHI). A sub-one-cycle sampling algorithm is proposed to quickly obtain the open-circuit voltage and then reduce the open-circuit sampling loss. To further improve the PCE and TE, a coarse-fine dual-loop (MPPT) is proposed, which balances the MPPT time and accuracy. The proposed interface is implemented in a <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS process, with a core area of <inline-formula> <tex-math>$949times 644~mu $ </tex-math></inline-formula>m2. With the sub-one-cycle sampling algorithm and the dual-loop MPPT control, the proposed PEHI can achieve a peak tracking efficiency of 99.31% and a peak power conversion efficiency (PCE) of 85.5% within the peak open-circuit voltage <inline-formula> <tex-math>$(V_{mathrm { POC}})$ </tex-math></inline-formula> range from 1 V to 2 V. FOM of the proposed PEHI is improved by about 1.76 times compared to the traditional FOCV PEHIs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"444-448"},"PeriodicalIF":4.0,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DRAM Physically Unclonable Function (PUF) Using Dual Word-Line Activated Twin-Cells 使用双字行激活双电池的DRAM物理不可克隆功能（PUF）

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-01-16 DOI: 10.1109/TCSII.2025.3530514

Mookyoung Yoo;Seon Bhin Kim;Hyeoktae Son;Kyounghwan Kim;Jihyang Wi;Gibae Nam;Minhyoek Son;Manhyoek Choi;Inju Yu;Dong Kyue Kim;Hyoungho Ko

{"title":"DRAM Physically Unclonable Function (PUF) Using Dual Word-Line Activated Twin-Cells","authors":"Mookyoung Yoo;Seon Bhin Kim;Hyeoktae Son;Kyounghwan Kim;Jihyang Wi;Gibae Nam;Minhyoek Son;Manhyoek Choi;Inju Yu;Dong Kyue Kim;Hyoungho Ko","doi":"10.1109/TCSII.2025.3530514","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3530514","url":null,"abstract":"Physically unclonable function (PUF) generates a unique fingerprint or root of trust using the inherent randomness introduced during manufacturing. PUF outputs requires to be unique, random, robust, and unclonable. Dynamic random access memory (DRAM)-based PUFs are attractive due to their high density and randomness, achieved by controlling critical timings parameters, including <inline-formula> <tex-math>$t_{RCD}, t_{RP}$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$t_{REF}$ </tex-math></inline-formula>. Traditional DRAM PUFs use a single word-line (WL) to select individual cells connected to a bit-line (BL), generating random outputs through “absolute” mismatches in properties such as cell capacitance, leakage current, and charge redistribution timings. In this brief, we present a novel twin-cell DRAM PUF that employs “differential” mismatches between activated cells. Dual WLs in this design activated both twin-cells connected to the BL and bit-line bar (BLb). Leakage currents through the access transistors discharged the precharged cells, and the residual charges in the cell capacitances were redistributed to the BL capacitances following the discharge period. The sense amplifier amplified the relative mismatches between the twin-cells to generate the PUF output. The PUF was fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process. It operates at a nominal voltage of 1 V. It demonstrated 49.5% uniformity and 98.51% reliability under nominal voltage and temperature. The inter-chip Hamming distance (HD) was 45.91%, while the inter-WL HD and inter-PUF HD were 50.19% and 49.98%, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"514-518"},"PeriodicalIF":4.0,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0