IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第9页

Clock Edge Triggering Control in Topology-Based Logic Dynamic Systems Using Matrix Approaches 基于矩阵方法的拓扑逻辑动态系统时钟边触发控制

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-29 DOI: 10.1109/TCSII.2025.3565551

Yingzhe Jia;Jiayu Hu;Yiliang Li;Peng Guo;Qianming Xu;An Luo;Abdelhamid Tayebi

引用次数: 0

Neural-Learning-Based Adaptive Sliding Mode Impedance Force Control of Robotic Microinjection Systems Interacting With Viscoelastic Cells 基于神经学习的机器人微注射系统粘弹性单元相互作用的自适应滑模阻抗力控制

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-25 DOI: 10.1109/TCSII.2025.3564463

Shengzheng Kang;Tao Li;Xiaolong Yang;Yao Li;Mingyang Xie

{"title":"Neural-Learning-Based Adaptive Sliding Mode Impedance Force Control of Robotic Microinjection Systems Interacting With Viscoelastic Cells","authors":"Shengzheng Kang;Tao Li;Xiaolong Yang;Yao Li;Mingyang Xie","doi":"10.1109/TCSII.2025.3564463","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3564463","url":null,"abstract":"Robotic microinjection has been widely applied in biomedical engineering, but faces a great challenge on the precise force interaction with cells due to their inherently deformable, fragile, and nonlinear viscoelastic properties. This brief proposes a new neural-learning based adaptive sliding mode impedance force control scheme for the robotic microinjection system to improve the interaction performance. The key features of the developed method are as follows: i) Target impedance is derived by utilizing the nonlinear Hunt-Crossley model to match the microscale interaction with environmental cells; ii) An integral terminal sliding mode manifold based on the impedance error is designed to achieve finite-time convergence and accurate force tracking; iii) The proposed scheme relieves the burden of environmental model dependence by estimating the uncertain bound of external disturbances through an adaptive neural network compensator. The control system stability is analyzed by the Lyapunov theory, and the force tracking performance is also verified via a series of experiments.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"828-832"},"PeriodicalIF":4.0,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SSPP Transmission System With Negative Group Delay and Power Compensation 具有负群延迟和功率补偿的SSPP传输系统

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-25 DOI: 10.1109/TCSII.2025.3564569

Guodong Lu;Qi Kang;Weiwen Li

引用次数: 0

A 22.5~28.5 -GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS 基于平面度增强技术的22.5~28.5 ghz低振幅变化低相位误差混合移相器，用于40nm CMOS下的5G NR

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-23 DOI: 10.1109/TCSII.2025.3563519

Shiping Zheng;Yun Wang;Ziyang Deng;Chen Jiang;Hongtao Xu

引用次数: 0

A 40 TOPS Single-Chip Accelerator Enabling Low-Latency Inference for Deep Neural Networks 一种支持深度神经网络低延迟推理的40 TOPS单芯片加速器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-21 DOI: 10.1109/TCSII.2025.3563062

Xun He;Tao Cao;Youjiang Liu;Le Zhong;Guoping Xiao;Cong Yu

{"title":"A 40 TOPS Single-Chip Accelerator Enabling Low-Latency Inference for Deep Neural Networks","authors":"Xun He;Tao Cao;Youjiang Liu;Le Zhong;Guoping Xiao;Cong Yu","doi":"10.1109/TCSII.2025.3563062","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3563062","url":null,"abstract":"To achieve low latency for edge applications, a single-chip sparse accelerator is proposed, which can conduct deep neural network (DNN) inference only using limited on-chip memory. Private memory is eliminated, and all memories are shared to reduce power and chip area. An adaptive and variable-length compression algorithm is proposed to store sparse DNNs. A weak-constrained pruning algorithm is proposed to resolve load balance issue in kernel level, which can achieve almost the same sparsity as unconstrained pruning schemes (UCP). Based on these works, a low latency inference accelerator is fabricated in 28-nm CMOS with 8256 MACs and 9.4 MB on-chip SRAM, which can achieve a latency of 0.44 ms for YOLO3 tiny. For high-sparsity layers, our chip can achieve <inline-formula> <tex-math>$6.1times $ </tex-math></inline-formula> speedup and a throughput of 40 TOPS. With a pruned YOLO model, our accelerator achieves <inline-formula> <tex-math>$6.7times $ </tex-math></inline-formula> lower latency and <inline-formula> <tex-math>$21.7times $ </tex-math></inline-formula> better energy efficiency than Jetson Orin. A high-speed evaluation platform is built to demonstrate real-time object detection at a throughput of 600 frames per second (fps) with a power of 1.34 W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"848-852"},"PeriodicalIF":4.0,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Cost and Speed Co-Optimized Parallel Stochastic Multiplier for Binary Inputs Supporting Variable Bit-Widths 支持可变位宽的二进制输入的代价和速度协同优化并行随机乘法器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-18 DOI: 10.1109/TCSII.2025.3562199

Qiang He;Yudi Zhao;Zhihuai Zhang;Gang Du;Xiaofei Nie;Ye Lu;Shisheng Xiong;Kai Zhao

{"title":"A Cost and Speed Co-Optimized Parallel Stochastic Multiplier for Binary Inputs Supporting Variable Bit-Widths","authors":"Qiang He;Yudi Zhao;Zhihuai Zhang;Gang Du;Xiaofei Nie;Ye Lu;Shisheng Xiong;Kai Zhao","doi":"10.1109/TCSII.2025.3562199","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3562199","url":null,"abstract":"Stochastic circuits offer the benefits of small area and lower power consumption. However, as the bit width of the operands increases, the area and latency of stochastic circuits also need to increase exponentially to meet the precision requirements, resulting in a decrease in performance. This brief introduces a low-cost and high-speed parallel approximate stochastic computing multiplier (PASCM), which takes binary streams as both inputs and outputs. The PASCM is suitable for multiplication operations with multi-bit width. In order to further enhance the accuracy of the PASCM, an error compensation mechanism has been proposed. To verify the performance of PASCM, validation was conducted on FPGA. The experimental results indicate that the proposed design exhibits significant area and latency advantages among existing multipliers. Take 8-bit as an example, the PASCM shows a 48.33%, 18.61%, 45.74%, and 57.95% reduction in Look-Up Table (LUT), latency, power delay product (PDP), and area delay product (ADP), respectively, compared to the 8-bit precise binary multiplier implemented using an IP core. To further validate the design, the PASCM was constructed into Multiply-Accumulate units (MAC) and applied to several image processing algorithms on FPGA. The proposed multiplier showed excellent results in terms of peak signal-to-noise ratio (PSNR) and mean structural similarity index (MSSIM), with some algorithms achieving complete consistency with binary computation results, and the hardware performance also surpasses the most advanced designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1068-1072"},"PeriodicalIF":4.9,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Area-Cost VLSI Architecture of Fault-Aware High-Reliability Triple-Mode Polar Decoder Chip Reconfiguring SC and SCL Decoding 重构SC和SCL译码的故障感知高可靠性三模极性译码芯片的低面积成本VLSI架构

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-16 DOI: 10.1109/TCSII.2025.3561211

Xin-Yu Shih;Dong-Lin Wu;Wei-Lun Chang

引用次数: 0

A New Variant of Turns-Ratio Independent Shoot-Through Current-Based Magnetically-Coupled Z-Source Inverter With Smooth DC-Link Voltage and Enhanced High-Gain 一种基于圆滑直流链路电压和增强高增益的磁耦合z源逆变器的新型匝比无关击穿电流

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-15 DOI: 10.1109/TCSII.2025.3560895

S. Konar;P. K. Gayen;S. S. Saha

{"title":"A New Variant of Turns-Ratio Independent Shoot-Through Current-Based Magnetically-Coupled Z-Source Inverter With Smooth DC-Link Voltage and Enhanced High-Gain","authors":"S. Konar;P. K. Gayen;S. S. Saha","doi":"10.1109/TCSII.2025.3560895","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3560895","url":null,"abstract":"In a magnetically coupled impedance-source (MCIS) inverter, the low value of shoot-through (ST) current is desired to reduce the ratings and losses of the power converter. In this regard, turns-ratio-independent ST current is an important requirement. Very few inverters (active-switched Y-source MCIS inverters) are found in a recent article, which claims turns-ratio-independent ST current as a figure of merit. But it is observed that the voltage gain of the turn-ratio-independent ST current-based configuration is lesser than the turns-ratio-dependent ST current-based inverters. Therefore, this brief proposes a new variant of an active-switched MCIS inverter with a smooth DC-link voltage, which simultaneously exhibits enhanced voltage gain and a turns ratio-independent ST current. The voltage gain of the suggested network is higher than that of the recent equivalent MCIS inverters for the same magnitude and duration of shoot-through current, i.e., the voltage gains per shoot-through current (combined figure of merit) are significantly improved in the proposed inverter. The switching device power (SDP) is also reduced in the suggested inverter. Its desired operation is experimentally verified.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 6","pages":"858-862"},"PeriodicalIF":4.0,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.62-pJ/Bit 60-GHz OOK Receiver With Supply Interference Tolerance for Short-Range Interconnects 面向短距离互连的0.62 pj /Bit 60ghz OOK接收机

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-15 DOI: 10.1109/TCSII.2025.3560305

Junhong Liu;Yi Wu;Guangyin Feng;Rongbin Liu;Shaoxian Li;Chuan Hu;Xiuyin Zhang

引用次数: 0

Design and Application of Mean and Square Root Circuits for Stochastic Computing 随机计算中均方根电路的设计与应用

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-04-15 DOI: 10.1109/TCSII.2025.3560332

Shaowei Wang;Kai Shi;Yaohua Xu;Yi Wang;Yongqiang Zhang

引用次数: 0