IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第9页

A 120 GHz gm-boosting Low-Noise Amplifier in 40-nm CMOS 一种采用40nm CMOS的120 GHz提升毫米波低噪声放大器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-06 DOI: 10.1109/TCSII.2024.3493038

In Cheol Yoo;Dong Ouk Cho;Dong-Woo Kang;Bontae Koo;Chul Woo Byeon

引用次数: 0

Time-Elapsed-Reliant Observer-Based Control of Semi-Markov Jump Linear Systems With Bilaterally Bounded Sojourn Time 驻留时间有界的半马尔可夫跳变线性系统的时间依赖观测器控制

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-04 DOI: 10.1109/TCSII.2024.3491032

Yongxiao Tian;Zepeng Ning;Huaicheng Yan;Yan Peng

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An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR 片上交流耦合非对称输出级激光雷达

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-11-04 DOI: 10.1109/TCSII.2024.3489640

Yuye Yang;Hao Feng;Zhenyu Yin;Shuaizhe Ma;Jia Li;Xinyin Shan;Yifei Xia;Ruixuan Yang;Bing Zhang;Li Geng;Dan Li

{"title":"An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR","authors":"Yuye Yang;Hao Feng;Zhenyu Yin;Shuaizhe Ma;Jia Li;Xinyin Shan;Yifei Xia;Ruixuan Yang;Bing Zhang;Li Geng;Dan Li","doi":"10.1109/TCSII.2024.3489640","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3489640","url":null,"abstract":"In this brief, an on-chip AC coupled analog front-end circuit with asymmetric output stage is proposed for a pulsed direct time-of-flight LiDAR receiver. The AFE employs a novel on-chip AC coupled scheme for APD cathode bias voltage tuning in a cost-effective manner. A reverse current cancellation circuit helps the circuit recover rapidly under large input current. A transimpedance amplifier is designed for low noise which is desirable to process weak signals. An asymmetric output stage doubles the output swing under the same bias current compared to conventional current mode logic topology. This prototype chip is fabricated in a standard 180 nm CMOS process and the measurement results shows bandwidth, gain, input-referred noise current of 151 MHz, 102 dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, and 3.51 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000 Hz, respectively. The maximum differential output swing reaches \u0000<inline-formula> <tex-math>$1.8~rm V_{textrm {pp,diff}}$ </tex-math></inline-formula>\u0000 based on both electrical and optical measurement setup.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"148-152"},"PeriodicalIF":4.0,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference MorphBungee-Lite：基于分层事件批处理学习/推理的平衡跨核工作负载的边缘神经形态架构

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-30 DOI: 10.1109/TCSII.2024.3488526

Zhengqing Zhong;Haibing Wang;Mingju Chen;Yingcheng Lin;Min Tian;Tengxiao Wang;Liyuan Liu;Cong Shi

{"title":"MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference","authors":"Zhengqing Zhong;Haibing Wang;Mingju Chen;Yingcheng Lin;Min Tian;Tengxiao Wang;Liyuan Liu;Cong Shi","doi":"10.1109/TCSII.2024.3488526","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3488526","url":null,"abstract":"Neuromorphic processors are promising candidates for energy-constrained intelligent systems, as they emulate cortical computations via spatiotemporally sparse binary spikes. However, achieving high-accuracy, high-throughput and cost-efficient neuromorphic processing remains challenging. To fully utilize hardware resources for performance improvement, we propose a multi-core neuromorphic architecture characteristic of a uniform neuron-core mapping scheme and a layer-wise event-batch-based parallel processing paradigm. These techniques ensure highly balanced cross-core workloads regardless of actual mapped neural network topologies as well as unpredictable input and internally generated spike counts varying from sample to sample. An FPGA prototype of our neuromorphic processor was implemented. It exhibited comparably high on-chip learning accuracies on various visual and non-visual benchmarks, high learning/inference frame rates (low processing latencies), with a moderate amount of logic and memory resource consumptions.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"293-297"},"PeriodicalIF":4.0,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3477193

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IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information 电气和电子工程师学会电路与系统论文集--II：特快摘要》出版信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3477191

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Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium 2024 年国际科学与应用科学会议特邀编辑特刊：中国科学院期刊专题讨论会

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3467908

Antonio Liscidini

引用次数: 0

Reachable Set Estimation of Inertial Complex-Valued Memristive Neural Networks 惯性复值记忆神经网络的可达集估计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-28 DOI: 10.1109/TCSII.2024.3486746

Jiemei Zhao;Yi Shen;Leimin Wang;Liqi Yu

引用次数: 0

An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN 使用高精度转换算法的高效大脑启发加速器用于峰值可变形CNN

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-28 DOI: 10.1109/TCSII.2024.3487266

Haonan Zhang;Siyu Zhang;Wendong Mao;Zhongfeng Wang

{"title":"An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN","authors":"Haonan Zhang;Siyu Zhang;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TCSII.2024.3487266","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3487266","url":null,"abstract":"Spiking Neural Network (SNN), inspired by the brain, has shown promising potential in terms of low-power deployment on resource-constrained devices. The SNN can be obtained by two approaches: training from scratch or conversion from existing Artificial Neural Network (ANN). However, the directly training SNN often leads to suboptimal accuracy. Therefore, methods based on converting existing ANN have become the preferred choice for achieving high accuracy. To enhance the feature-capturing capability of the converted SNNs, various operations, such as transposed convolution and deformable convolution, have been introduced, which bring multiple challenges to conversion algorithms and hardware designs. In this brief, we propose a universal SNN conversion method for deformable convolution to enhance the modeling capability of receptive fields for spatial information. The proposed conversion algorithm not only maintains high accuracy but also makes converted deformable convolutions highly hardware-efficient. Building upon the deformable SNN, we develop a low-complexity processing element and computing array, enabling flexible execution of complex and heterogeneous operations within deformable SNNs without requiring any multipliers. In addition, the overall architecture with energy-efficient dataflow is designed for our deformable SNN model and is implemented in TSMC 28-nm HPC+ technology node. Experiments show that the proposed conversion algorithm suffers negligible accuracy degradation in the challenging object detection task. The accelerator achieves at least \u0000<inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula>\u0000 higher energy efficiency compared to previous designs while maintaining 47.9% mAP.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"288-292"},"PeriodicalIF":4.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An X-Band 7-Bit High Resolution and Ultra-Low Amplitude Variations Phase Shifter With Current Correction Technique 采用电流校正技术的x波段7位高分辨率超低幅度变化移相器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-25 DOI: 10.1109/TCSII.2024.3486569

Dongwei Pang;Jun Wang;Zongming Duan

引用次数: 0