{"title":"The Three-Stage Identification Method of the Sandwich Model With Hysteresis","authors":"Ya Gu;Haiyan Hou;Yonghong Tan","doi":"10.1109/TCSII.2025.3580551","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580551","url":null,"abstract":"This brief investigates the identification of sandwich systems exhibiting hysteresis behavior. To address the problem that the filtering effect of the previous-stage subsystem on the input signal results in the filtered excitation input causing insufficient excitation of the subsequent-stage subsystems, thus reducing the identification accuracy, a new robust three-stage identification method is proposed to ensure the sufficient excitation of the entire system and enhance the identification accuracy. The key to this method lies in the staged estimation of subsystem parameters. In each stage, parameter estimation is carried out using the key-item separation principle combined with an iterative process. Then, based on the previously estimated submodel parameters, an inverse model is developed to filter the input excitation signal. Therefore, the insufficient excitation of the subsequent-stage subsystem caused by the filtering effect of the previous-stage subsystem on the input signal is counteracted, enhancing parameter estimation accuracy. Finally, this method is applied to the parameter identification of an electromagnetic micromirror.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1058-1062"},"PeriodicalIF":4.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yang Zhang;Xilong Kang;Weixuan Wang;Yizhi Ding;Lizheng Ren;Yiran Zhang;Ruiqi Tan;Zhen Wang;Hao Cai;Bo Liu
{"title":"KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM","authors":"Yang Zhang;Xilong Kang;Weixuan Wang;Yizhi Ding;Lizheng Ren;Yiran Zhang;Ruiqi Tan;Zhen Wang;Hao Cai;Bo Liu","doi":"10.1109/TCSII.2025.3580135","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580135","url":null,"abstract":"This brief proposes KV-CIM, a KV-Cache oriented Digital Compute-In-Memory (DCIM) sparse attention accelerator, to address computational and memory bottlenecks in autoregressive inference for large language models. Key innovations include: a) A query-aware pre-compute architecture, which dynamically selects and accesses KV-Cache for critical tokens at the pre-compute stage (Stage1) and deploys KV-Cache segmentally on memory-constrained edge devices while maintaining computational accuracy at the formal computation stage (Stage2); b) A cross-stage DCIM macro featuring precision-configurable adder trees, which works in approximate mode at Stage1 and changes to full precision mode at Stage2; c) A query-stationary dataflow that retains the current query tensors in q-CIM across stages to eliminate data movement. Under 28-nm CMOS technology, the proposed KV-CIM achieves 35.16 TOPS/W and 82% reduction of external memory access with negligible degradation in LLaMA2 expressiveness.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1073-1077"},"PeriodicalIF":4.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaofeng Huang;Jiaqing Lin;Fengguang Liu;Wen Ji;Haibing Yin;Siwei Ma
{"title":"Efficient Hardware Architecture Design of K-Means Clustering Algorithm for AV1 Palette Mode Coding","authors":"Xiaofeng Huang;Jiaqing Lin;Fengguang Liu;Wen Ji;Haibing Yin;Siwei Ma","doi":"10.1109/TCSII.2025.3580435","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580435","url":null,"abstract":"The palette mode is a specialized coding tool for coding screen content video in Alliance for Open Media Video 1 (AV1), and K-means clustering is a necessary step in the palette mode. However, the high computational complexity and the strong data dependency in K-means clustering impede real-time processing. To address these issues, we propose an efficient hardware architecture design for the K-means clustering algorithm. Firstly, we propose a fully pipelined hardware architecture with two data-interleaving optimization methods, including K-interleaving and block-interleaving. Then, we propose a novel method for reusing original pixel data, which is motivated by the fact that the input original pixels are the same for different coding blocks. Finally, we propose a parallelized architecture that features three “K-means Engine” modules, with reusing of the “Euclidean distance calculate” module to minimize area. Experimental results show that the proposed hardware architecture can process all K-means clustering for pixels in a superblock in 10246 cycles under 650MHz working frequency, which can achieve 4K@30fps real-time processing. To the best of our knowledge, our work is the first attempt to design a K-means clustering hardware accelerator for palette mode in AV1.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1078-1082"},"PeriodicalIF":4.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Neural Network-Enhanced Digital Background Calibration Algorithm for Residue Amplifier Nonlinearity in Pipelined ADCs","authors":"Yutao Peng;Ziwei Lai;Hu Wang;Jun Zhang;Dongbing Fu;Yabo Ni;Tao Liu;Zhifei Lu;Xizhu Peng;He Tang","doi":"10.1109/TCSII.2025.3580062","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580062","url":null,"abstract":"This brief proposes a neural network-enhanced digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. A customized convolutional neural network (CNN) is designed to extract the information of the linear and the third-order nonlinear gain errors of RA with dither injection. Compared to traditional correlation-based calibration algorithms, the proposed method can significantly improve convergence speed and robustness against dither capacitor mismatch. Compared with previous neural network-based calibration techniques which are commonly used for foreground calibration, the proposed method can operate in background to follow error variations without any risk of signal fidelity problems. Off-chip validation with a silicon-proven 14-bit 1.3 GS/s pipelined ADC shows that, after calibration, the SNDR and SFDR are improved from 46.6 dB and 55.2 dB to 63.1 dB and 80.4 dB, respectively. Moreover, the proposed method takes only 75K samples to reach convergence, whereas traditional algorithms require several to hundreds of millions of samples to achieve convergence (<inline-formula> <tex-math>$10{^{{2}}} sim 10{^{{4}}}$ </tex-math></inline-formula> times faster). The implementation result shows that the power consumption of the proposed calibrator is 34.8 mW at 1.3 GHz clock frequency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1008-1012"},"PeriodicalIF":4.9,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kai Li;Zhipeng Wang;Fanyi Meng;Kaixue Ma;Keping Wang
{"title":"A 28.4-to-39.2 GHz Low-Power Injection-Locked Frequency Quadrupler With Reconfigurable Pre-Filter-Amplifier","authors":"Kai Li;Zhipeng Wang;Fanyi Meng;Kaixue Ma;Keping Wang","doi":"10.1109/TCSII.2025.3579551","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3579551","url":null,"abstract":"In this brief, a 28.4 to 39.2 GHz injection-locked frequency quadrupler (ILFQ) is fabricated in a 65nm CMOS process. A reconfigurable pre-filter-amplifier (RPFA) structure is proposed to pre-process the output current of the harmonic generator. By switching between two modes, the RPFA effectively filters out the undesired harmonics and amplifies the desired 4th harmonic. Therefore, both the harmonic rejection and locking range of the ILFQ are improved. In addition, a load tank based on a three-coil coupled transformer and an impedance-boosting transformer is designed to further extend the locking range, increase the output power, and reduce the DC power consumption. The measured results show that the proposed ILFQ achieves a 31.9% locking range (28.4 GHz to 39.2 GHz). Across the whole locking range, the measured 1st/2nd/3rd harmonic rejection ratio (HRR) is better than 42.4/37.4/15 dBc, respectively. Within the range of 28.4 to 36.2 GHz, >29 dBc 1st/2nd/3rd HRR is achieved. The measured maximum DC power consumption is 13.3 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"998-1002"},"PeriodicalIF":4.9,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi Lu;Xiru Wu;Yaonan Wang;Rili Wu;Yuhai Zhong;Jiexin Xie
{"title":"Hybrid Scheduling-Based Asynchronous H∞ Control for Markov Jump Power Systems With Cyber Attacks","authors":"Yi Lu;Xiru Wu;Yaonan Wang;Rili Wu;Yuhai Zhong;Jiexin Xie","doi":"10.1109/TCSII.2025.3578663","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578663","url":null,"abstract":"This brief investigates the asynchronous <inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula> control problem of discrete-time hidden Markov jump power systems (hMJPSs) under cyber attacks. To precisely capture the dynamic characteristics of transient faults and circuit breaker switching in power systems, a hidden Markov jump process with unknown information is introduced. A hybrid scheduling protocol via event triggering is proposed to enhance the utilization of communication resources. By dynamically adjusting the data transmission frequency of sensor nodes, the protocol significantly reduces communication resource usage while maintaining <inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula> performance of the system. Additionally, considering the mode mismatched behavior between the power systems and the controllers, the asynchronous state-feedback controller is designed. Through the mode-dependent Lyapunov function, the sufficient conditions for the mean-square stability of hMJPSs are derived. Finally, the effectiveness and practicality of the proposed method are validated via simulation examples.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1048-1052"},"PeriodicalIF":4.9,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Won-Gyu Kim;Sang-Yun Nam;Young-Jun Jeon;Sung-Wan Hong
{"title":"A 1.8–5.5-V LDO–BGR System With LACM Buffer for High PSRR in Camera Applications","authors":"Won-Gyu Kim;Sang-Yun Nam;Young-Jun Jeon;Sung-Wan Hong","doi":"10.1109/TCSII.2025.3578616","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578616","url":null,"abstract":"This brief proposes a low-dropout regulator (LDO) and bandgap reference (BGR) system designed for camera applications, where high power supply rejection ratio (PSRR) and low output noise are critical. To achieve a stable output across a wide load range from no load to 600 mA a load-adaptive current-mirror (LACM) buffer is introduced. The LACM buffer effectively regulates current flow across different load conditions, minimizing power loss while ensuring stable operation. Additionally, a sample-and-hold (S/H)-based BGR is implemented to eliminate noise propagation from the supply voltage <inline-formula> <tex-math>$(V_{mathrm { SYS}})$ </tex-math></inline-formula> to the reference voltage <inline-formula> <tex-math>$(V_{mathrm { REF}})$ </tex-math></inline-formula>, further enhancing PSRR. The proposed system was fabricated using a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1108-1112"},"PeriodicalIF":4.9,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Privacy-Preserving Optimal Battery Control for Energy Storage Systems Using Adaptive Dynamic Programming","authors":"Jiaoni Wang;Jiayue Sun","doi":"10.1109/TCSII.2025.3578944","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578944","url":null,"abstract":"This brief investigates the problems of high electricity costs due to price fluctuations and data transmission security risks in energy management systems. To mitigate these issues, first, a privacy-preserving communication framework based on encryption-decryption mechanisms is designed to enhance data security and prevent malicious attacks. Then, a battery management approach based on an adaptive dynamic programming algorithm with privacy protection is designed to optimize energy scheduling, reduce electricity costs, and extend battery lifetime. The algorithm is implemented using an actor-critic neural network architecture, and it is proven that the weight estimation errors are uniformly ultimately bounded. Finally, simulation results validate the designed approach’s capability in reducing electricity costs and enhancing data security.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1053-1057"},"PeriodicalIF":4.9,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Switch-as-Resistor Self-Adaptive Gate-Biasing Technique for Optimized Forward and Reverse Conduction in a CMOS Rectifier","authors":"Yi Chen Lee;Harikrishnan Ramiah;Tian Siang Ho;Fu Qi Chua;Wen Xun Lian;Kishore Kumar Pakkirisami Churchill;Yong Chen","doi":"10.1109/TCSII.2025.3578345","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578345","url":null,"abstract":"This brief proposes a switch-as-resistor self-adaptive gate-biasing technique implemented in a 900 MHz single-stage cross-coupled rectifier for IoT and WSN applications. The proposed method employs NMOS switches as the resistive component (RRES), which are controlled by a rectangular signal from a CMOS inverter. This configuration adaptively enables (disables) the NMOS switches during reverse (forward) conduction phases, and self-adaptively provides gate-biasing, resulting in conserved forward charge with mitigated reverse charge. As a result, the output power is enhanced with higher charge accumulation at the output terminal. The circuit gives a measured result of 84.3% in peak power conversion efficiency (PCE) at an input power (PIN) of –21 dBm through a 100 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> load. The proposed circuit also achieves a 25 dB DR with a PCE of over 20%. With a compact chip area of 0.0105 mm2, the rectifier achieves the widest PDR of 25 dB and a sensitivity of –18 dBm under a 100 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> load. Compared to other state-of-the-art rectifiers, the proposed scheme demonstrates higher performance in terms of PDR and PCE.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1103-1107"},"PeriodicalIF":4.9,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cong Huang;Li Zhu;Weiping Ding;Peng Mei;Shichun Yang;Quan Shi
{"title":"An Encoding–Decoding-Based State Estimation Scheme for State-Saturated Systems Under Buffer-Aided Mechanism","authors":"Cong Huang;Li Zhu;Weiping Ding;Peng Mei;Shichun Yang;Quan Shi","doi":"10.1109/TCSII.2025.3578535","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578535","url":null,"abstract":"In this brief, the encoding-decoding-based state estimation problem is investigated for a class of state-saturated systems under buffer-aided mechanism where the wireless communication is unreliable. The buffer-aided mechanism is exploited to improve the data utilization and estimation performance with the capability of storing the undelivered signals and then transmits them to the remote estimator at each transmission instant. To overcome inherent communication limitations, a novel probabilistic encoding-decoding scheme is introduced to compress the sensor measurements. The objective of this brief is to develop an encoding-decoding-based estimator such that the estimation error covariance is minimized in certain sense for all possible state saturations as well as the effects induced by buffer-aided mechanism. The estimation error covariance conditioned on the transmission intervals is first obtained in recursions and then is minimized by the choice of the appropriate estimator gain. Finally, simulation results are presented to demonstrate the validity of the proposed estimation scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1043-1047"},"PeriodicalIF":4.9,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}