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Prescribed-Time Synchronization of Second-Order Kuramoto Oscillators 二阶Kuramoto振子的规定时间同步
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-16 DOI: 10.1109/TCSII.2026.3664824
Rui Tang;Huihui Song;Xinpo Lin;Shuaihao Jiang;Xiang Gao;Zhuang Liu;Jianxing Liu
{"title":"Prescribed-Time Synchronization of Second-Order Kuramoto Oscillators","authors":"Rui Tang;Huihui Song;Xinpo Lin;Shuaihao Jiang;Xiang Gao;Zhuang Liu;Jianxing Liu","doi":"10.1109/TCSII.2026.3664824","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3664824","url":null,"abstract":"This brief addresses the problem of frequency and phase synchronization in a network of second-order Kuramoto oscillators with inertia. Distinct from traditional asymptotic synchronization, which theoretically requires infinite time, a prescribed-time control scheme is proposed to force the system states to synchronize within a user-defined duration. Specifically, a coordinate transformation is introduced to eliminate the drift induced by heterogeneous natural power injections, and a time-varying scaling function is incorporated into the controller design to regulate the convergence rate. Based on a constructed Lyapunov function containing cross-terms, rigorous theoretical analysis ensures that the synchronization error converges to zero at the prescribed time regardless of initial conditions. Finally, numerical simulations are provided to demonstrate the effectiveness and robustness of the proposed approach.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"453-457"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1-kHz BW 106-dB SNDR DT Zoom ADC 1 khz bw106 db SNDR DT变焦ADC
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1109/TCSII.2026.3663707
Yuhua Liang;Yuxi Zhu;Ruiwen Liu;Yanbo Zhang;Zhong Tang;Zhangming Zhu
{"title":"A 1-kHz BW 106-dB SNDR DT Zoom ADC","authors":"Yuhua Liang;Yuxi Zhu;Ruiwen Liu;Yanbo Zhang;Zhong Tang;Zhangming Zhu","doi":"10.1109/TCSII.2026.3663707","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3663707","url":null,"abstract":"This brief presents a high-linearity discrete-time (DT) Zoom analog-to-digital converter (ADC). To enhance linearity and simplify implementation, a coarse first-order sigma-delta modulator (SDM) followed by a 16-tap finite-impulse-response (FIR) DAC is employed, inherently suppressing harmonic distortion and eliminating the complex hardware associated with a conventional successive-approximation register (SAR) ADC and dynamic element matching (DWA). The proposed architecture achieves a 35 dB improvement in third-harmonic distortion (HD3) over a conventional 4-bit SAR-based implementation. Fabricated in a 180-nm CMOS process, the prototype measures a 106-dB signal-to-noise-and-distortion ratio (SNDR), a 109.7-dB dynamic range (DR), and a 111.1-dB spurious-free dynamic range (SFDR) over a 1-kHz bandwidth, while consuming <inline-formula> <tex-math>$63.1mu $ </tex-math></inline-formula> W from a 1.8-V supply at an 800-kHz sampling rate. This corresponds to a Schreier figure-of-merit (FoM) of 178 dB based on SNDR and 181.7 dB based on DR, without employing DWA techniques.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"373-377"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.4-GHz −247.7-dB Jitter-FoM Ring-VCO-Based Injection-Locked PLL With Triple-Point Injection and Injection Timing-Pulsewidth Calibration 一个2.4 ghz−247.7 db基于抖动的环vco注入锁相环，具有三点注入和注入定时脉宽校准
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-26 DOI: 10.1109/TCSII.2026.3668302
Zhen Li;Yuxiao Zhou;Shize Duan;Xing Quan;Yuanyuan Cui;Xiang Yi;Xunying Zhang
{"title":"A 2.4-GHz −247.7-dB Jitter-FoM Ring-VCO-Based Injection-Locked PLL With Triple-Point Injection and Injection Timing-Pulsewidth Calibration","authors":"Zhen Li;Yuxiao Zhou;Shize Duan;Xing Quan;Yuanyuan Cui;Xiang Yi;Xunying Zhang","doi":"10.1109/TCSII.2026.3668302","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3668302","url":null,"abstract":"This brief introduces an injection-locked phase-locked loop (ILPLL) with triple-point injection and background injection pulse self-calibration techniques. The proposed triple-point injection scheme effectively eliminates the phase shift induced by conventional direct injection while enhancing injection strength by combining direct injection, cross-coupled complementary injection, and tail injection, thereby achieving low jitter. Furthermore, concurrent calibration of both injection timing and pulsewidth provides further jitter suppression and ensures low spur. Fabricated in a 28-nm CMOS process, the proposed ILPLL achieves an RMS jitter of 135 fs, a reference spur of −70.9 dBc, and a state-of-the-art FoM<sub>jitter</sub> of −247.7 dB at an operating frequency of 2.4 GHz. The proposed ILPLL consumes 9.3 mW power from a 0.9 V supply and occupies an active area of 0.02 mm<sup>2</sup>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"408-412"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60-V Chopper Amplifier Achieving 0.12-μV Ripple and 2-μV VOS Over Full Temperature With Calibration 一种60v斩波放大器，可在全温度下实现0.12 μ v纹波和2 μ v VOS
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-10 DOI: 10.1109/TCSII.2026.3663261
Jingbin Feng;Shanshan Zhou;Peiru Hou;Pengda Qu;Yue Zhao;Zhiming Xiao
{"title":"A 60-V Chopper Amplifier Achieving 0.12-μV Ripple and 2-μV VOS Over Full Temperature With Calibration","authors":"Jingbin Feng;Shanshan Zhou;Peiru Hou;Pengda Qu;Yue Zhao;Zhiming Xiao","doi":"10.1109/TCSII.2026.3663261","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3663261","url":null,"abstract":"This brief presents a 60 V chopper-stabilized operational amplifier (opamp) with an 8 MHz gain-bandwidth product (GBW) and precision calibration. A novel high-voltage adaptive clock-bootstrap technique is proposed, compensates for temperature variations of the threshold voltage, and maintains a constant overdrive voltage. The opamp integrates a <inline-formula> <tex-math>$500times $ </tex-math></inline-formula> gain module to amplify and calibrate the non-chopped offset voltage, thereby reducing output ripple. It adopts a calibration scheme with temperature-compensated bit weights which are proportional to the transconductance of the chopper-path input transistor pair. Fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m Bipolar-CMOS-DMOS process, the amplifier employs input-referred offset and ripple minimization techniques while ensuring consistent performance over a wide input common-mode voltage range and temperature span, achieving a 3-<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula> offset voltage of <inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>V across 100 samples (-<inline-formula> <tex-math>$40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C), an offset drift of 7 nV/°C, and a maximum input-referred ripple of <inline-formula> <tex-math>$0.12~mu $ </tex-math></inline-formula>V<sub>RMS</sub>(Root Mean Square).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"368-372"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Linearization Technique for CCO-Based ADCs for AiMC MVM Architectures Using Resistive Memory Devices 基于cco的AiMC MVM架构adc线性化技术
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-06 DOI: 10.1109/TCSII.2026.3661725
Andrea Lico;Marco Pasotti;Riccardo Zurla;Riccardo Vignali;Lorenzo Greco;Alessandro Cabrini;Eleonora Franchi Scarselli;Alessio Antolini
{"title":"Linearization Technique for CCO-Based ADCs for AiMC MVM Architectures Using Resistive Memory Devices","authors":"Andrea Lico;Marco Pasotti;Riccardo Zurla;Riccardo Vignali;Lorenzo Greco;Alessandro Cabrini;Eleonora Franchi Scarselli;Alessio Antolini","doi":"10.1109/TCSII.2026.3661725","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3661725","url":null,"abstract":"This brief presents a design technique to linearize the frequency-to-conductance characteristic of a Current-Controlled Oscillator (CCO) within a CCO-based ADC used for Matrix-Vector Multiplication (MVM) in Analog in-Memory Computing (AiMC) accelerators. The proposed linearization is achieved by leveraging a bitline voltage regulator (BLVR), a circuit commonly employed to bias the bitlines (BLs) of computational resistive memory arrays. The BLVR utilizes a resistor and a copy of the bitline current to create a feedback mechanism that dynamically adjusts the bitline voltage in response to changes in the total bitline conductance (<inline-formula> <tex-math>$boldsymbol {g_{BL}}$ </tex-math></inline-formula>). This feedback reduces the oscillation period by an amount that linearizes the relationship between the CCO output frequency (<inline-formula> <tex-math>$boldsymbol {f_{CCO}}$ </tex-math></inline-formula>) and <inline-formula> <tex-math>$boldsymbol {g_{BL}}$ </tex-math></inline-formula>. Simulations in 28 nm FD-SOI technology demonstrate that the proposed BLVR reduces the quadratic coefficient <inline-formula> <tex-math>$boldsymbol {k_{2}}$ </tex-math></inline-formula> of a polynomial approximation of the <inline-formula> <tex-math>$boldsymbol {f_{CCO}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$boldsymbol {g_{BL}}$ </tex-math></inline-formula> characteristic from <inline-formula> <tex-math>$boldsymbol {5.88times 10^{-2}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$boldsymbol {2.31times 10^{-2}}$ </tex-math></inline-formula>, corresponding to a <inline-formula> <tex-math>$boldsymbol {2.5times }$ </tex-math></inline-formula> improvement in linearity in the full conductance range.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"363-367"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11373241","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fully Integrated 16-MHz Voltage-Mode Relaxation Oscillator With Current Calibration for Temperature Compensation 一个完全集成的16 mhz电压模式弛豫振荡器与温度补偿电流校准
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-06 DOI: 10.1109/TCSII.2026.3661186
Jaekwang Yun;Jooyeol Rhee
{"title":"A Fully Integrated 16-MHz Voltage-Mode Relaxation Oscillator With Current Calibration for Temperature Compensation","authors":"Jaekwang Yun;Jooyeol Rhee","doi":"10.1109/TCSII.2026.3661186","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3661186","url":null,"abstract":"This brief presents a fully integrated 16-MHz on-chip voltage-mode relaxation oscillator that employs a current calibration technique for temperature. Fabricated in a 130nm CMOS process, the prototype occupies only 0.048mm<inline-formula> <tex-math>${}^{mathbf {2}}$ </tex-math></inline-formula> of active area. The proposed calibration method leverages an on-chip bandgap reference to stabilize the oscillator’s reference current and control voltage against temperature variations. With calibration enabled, the oscillator’s temperature coefficient is reduced from 405.83 ppm/°C to 93.83 ppm/°C, with an average of 77.32 ppm/°C measured from–<inline-formula> <tex-math>$40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$80~^{circ }$ </tex-math></inline-formula>C, demonstrating significantly improved frequency stability. Operating at 16 MHz, the design consumes <inline-formula> <tex-math>$60mu $ </tex-math></inline-formula>W, corresponding to a power efficiency figure of merit (<italic>FoM</i><inline-formula> <tex-math>${}_{mathbf {1}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$3.75~mu $ </tex-math></inline-formula>W/MHz, and achieves a phase noise FoM (<italic>FoM</i><inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula>) of–142.3 dBc/Hz. These results confirm that the proposed oscillator provides a compact, low-power clock source with excellent temperature stability.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"358-362"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Multiplierless FPGA Architecture for Brain-Inspired Rulkov Neuron Mapping 基于大脑的Rulkov神经元映射的高效无乘法器FPGA架构
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2025-12-26 DOI: 10.1109/TCSII.2025.3648509
Huan Chen;Xiaojun Ji;Jun Sun;Mohammad Sh. Daoud;Abdulilah Mohammad Mayet;Xiaotian Pan;Chaochao Wang;Guodao Zhang;Xinjun Miao
{"title":"Efficient Multiplierless FPGA Architecture for Brain-Inspired Rulkov Neuron Mapping","authors":"Huan Chen;Xiaojun Ji;Jun Sun;Mohammad Sh. Daoud;Abdulilah Mohammad Mayet;Xiaotian Pan;Chaochao Wang;Guodao Zhang;Xinjun Miao","doi":"10.1109/TCSII.2025.3648509","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3648509","url":null,"abstract":"This brief presents a high-efficiency, multiplierless Field-Programmable Gate Array (FPGA) realization of the Rulkov neuron map using a hybrid approximation framework. The proposed approach integrates High-Frequency Point Detection (HFPD) for accurate spiking approximation and Exponential Binary Power (EBP) computed via Coordinate Rotation Digital Computer (CORDIC) for efficient bursting dynamics, fully eliminating multipliers and dividers. Implemented on a Xilinx Virtex-4 FPGA, the design achieves a synthesis frequency of 276.9 MHz, reduces hardware utilization by 30%, and improves speed by <inline-formula> <tex-math>$1.27times $ </tex-math></inline-formula> compared to the baseline. An average Root Mean Squared Error (RMSE) of 0.54 and successful two-coupled and ten-multiplexed implementations confirm the accuracy, scalability, and real-time suitability of the proposed Rulkov-Digital Circuit (R-DC) architecture for neuromorphic computing systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"298-302"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148482839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-02-27 DOI: 10.1109/TCSII.2026.3664626
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2026.3664626","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3664626","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"C2-C2"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11417353","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148482842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Efficiency Reconfigurable Charge Pump With Full Capacitance Utilization and Two-Dimensional Multiphase Interleaving 一种全电容利用和二维多相交错的高效可重构电荷泵
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-01-01 DOI: 10.1109/TCSII.2025.3650389
Ziliang Zhou;Zhenhao Li;Xi Deng;Mingyang Gong;Min Tan
{"title":"A High-Efficiency Reconfigurable Charge Pump With Full Capacitance Utilization and Two-Dimensional Multiphase Interleaving","authors":"Ziliang Zhou;Zhenhao Li;Xi Deng;Mingyang Gong;Min Tan","doi":"10.1109/TCSII.2025.3650389","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3650389","url":null,"abstract":"This paper presents a reconfigurable high-voltage charge pump with regulated output, designed to deliver high efficiency across a wide operating range. Different from previous designs, the charge pump is reconfigured by connecting unit cells in series or parallel, achieving full capacitance utilization and hence improved power efficiency. The stage reconfiguration circuit is implemented without using high-voltage tolerant devices and allows modularity and scalability. Two-dimensional multiphase interleaving is proposed to enhance power efficiency while reducing the input current ripple and output voltage ripple. The system was fabricated in a 55 nm standard CMOS process occupying a core area of <inline-formula> <tex-math>$470~mu $ </tex-math></inline-formula>m by <inline-formula> <tex-math>$225~mu $ </tex-math></inline-formula>m. Experimental results indicate the maximum increase in efficiency for different load currents is 10%. The peak efficiency increases from 46.2% to 51.4% at a 150-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>A load and 8-V output while achieving >42% overall efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"333-337"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148483368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact V-Band Quad-Core VCO With Coupling-Coexistence and Dual-Filtering Techniques 采用耦合共存和双滤波技术的紧凑型v波段四核压控振荡器
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-03-01 Epub Date: 2026-01-06 DOI: 10.1109/TCSII.2026.3651531
Junyuan Tu;Kaiming Zhong;Yongchun Li;Shuai Deng;Jiasheng Liang;Ruilong Yuan;Hongli He;Xiang Yi;Haoshen Zhu
{"title":"A Compact V-Band Quad-Core VCO With Coupling-Coexistence and Dual-Filtering Techniques","authors":"Junyuan Tu;Kaiming Zhong;Yongchun Li;Shuai Deng;Jiasheng Liang;Ruilong Yuan;Hongli He;Xiang Yi;Haoshen Zhu","doi":"10.1109/TCSII.2026.3651531","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3651531","url":null,"abstract":"This brief proposes a compact and low phase noise (PN) <inline-formula> <tex-math>$V$ </tex-math></inline-formula>-band quad-core voltage-controlled oscillator (VCO) in a 28-nm CMOS technology, capable of extracting third-harmonic frequencies for <inline-formula> <tex-math>$D$ </tex-math></inline-formula>-band integrated sensing and communication (ISAC) systems. Coupling-coexistence technique based on a tri-coupled transformer and dual-filtering technique enhance PN without additional area. A compact snowflake geometry topology is proposed, employing both inductor-sharing and mode-rejection techniques. The measured quad-core VCO tunes from 49.8 to 53.9 GHz, achieving -94.2 dBc/Hz and -121.1 dBc/Hz optimal phase noise (PN) at 1 MHz and 10 MHz offset, respectively, at 53.6 GHz carrier. The design also achieves the comparable area and power consumption of a single-core oscillator, combined with the PN performance advantages of multi-core oscillators, achieving a high FoM<sub>A</sub> of -200.1 dBc/Hz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 3","pages":"243-247"},"PeriodicalIF":4.6,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148483872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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