IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第9页

Cryogenic CMOS Active Mixer Employing Transformer-Based Current-Bleeding Technique 基于变压器放流技术的低温CMOS有源混频器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-18 DOI: 10.1109/TCSII.2025.3543306

Junhyeop Kim;Juhui Jeong;Junghwan Han

引用次数: 0

A Current-Mode Multiply-Accumulate Macro in Sensing-Computing Fusion System for Feature Extraction and Redundancy Reduction 一种用于特征提取和冗余减少的电流模式乘累积宏

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-18 DOI: 10.1109/TCSII.2025.3543173

Xu Ren;Xinpeng Li;Chang Xue;Yandong He;Gang Du

引用次数: 0

A 43.4-dB Gain 7.6-mW 197.5% Bandwidth Double Noise-Canceling Cryogenic LNA Using Gain Peaking Technique for Multiple Spin Qubit Readout 基于增益峰值技术的43.4 db增益7.6 mw 197.5%带宽双降噪低温LNA多自旋量子位读出

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-18 DOI: 10.1109/TCSII.2025.3543474

Mahesh Kumar Chaubey;Yin-Cheng Chang;Po-Chang Wu;Hann-Huei Tsai;Shawn S. H. Hsu

{"title":"A 43.4-dB Gain 7.6-mW 197.5% Bandwidth Double Noise-Canceling Cryogenic LNA Using Gain Peaking Technique for Multiple Spin Qubit Readout","authors":"Mahesh Kumar Chaubey;Yin-Cheng Chang;Po-Chang Wu;Hann-Huei Tsai;Shawn S. H. Hsu","doi":"10.1109/TCSII.2025.3543474","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3543474","url":null,"abstract":"This brief proposes a cryogenic stacked inverter-based gain-flattening low-noise amplifier (LNA) with dual current reuse and dual noise-canceling in 28-nm CMOS. The LNA features a current-reuse high-Q gate inductor and cascode inverter-based input stage with shunt-resistive feedback, optimizing wideband input impedance. A cryogenic aware self-body bias (SBB) mitigates <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$r_{mathrm { out}}$ </tex-math></inline-formula> variations at cryogenic temperatures. The design incorporates a source-degenerated common-source (CS) main amplifier, followed by current reuse inductor gain peaking cascode dual noise-canceling CS transistors, enhancing transconductance and suppressing noise in both main and auxiliary amplifiers. At cryogenic temperature (4 K), the LNA achieves a measured peak gain <inline-formula> <tex-math>$(S_{21})$ </tex-math></inline-formula> of 43.4 dB, with a large 3-dB bandwidth from 0.02 – 3.2 GHz (197.5% fractional BW) and a minimum NF of 0.37 dB (corresponding to noise temperature <inline-formula> <tex-math>$T_{N}$ </tex-math></inline-formula> of 25.8 K) at 0.7 GHz under power dissipation of 7.6 mW. The circuit occupies an active area of 0.31 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"638-642"},"PeriodicalIF":4.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Single-Ended Back-Bias Voltage Generator Using One Pumping Capacitor 使用一个泵浦电容的单端反偏置电压发生器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-14 DOI: 10.1109/TCSII.2025.3542106

Taegun Yim;Hongil Yoon

{"title":"Single-Ended Back-Bias Voltage Generator Using One Pumping Capacitor","authors":"Taegun Yim;Hongil Yoon","doi":"10.1109/TCSII.2025.3542106","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3542106","url":null,"abstract":"As the dynamic random-access memory technology advances, the size of storage capacitors has diminished. This trend has been accompanied by the challenge of reading cell data reliably from the storage capacitor. One of the most common approaches to solving this problem is preserving stored data by suppressing the sub-threshold leakage current in the access transistors with a negative body bias with a back-bias voltage (VBB) generator. This brief introduces a single-ended VBB generator using only one pumping capacitor. Conventional VBB generators with single-ended structures have a threshold voltage loss and unwanted charge-sharing at internal nodes and load outputs, causing performance degradation. The proposed circuit addresses these issues by employing a grounded gate inverter and an n-channel metal-oxide semiconductor transistor as a discharge transistor. This novel configuration can generate a negative voltage up to the supply voltage level with only one pumping capacitor with merits of power and size. Using the DBHitek <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m process technology, the proposed circuit has the lowest power consumption, power-delay product, and better pumping efficiency compared to the conventional single-ended VBB generator circuits.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"554-558"},"PeriodicalIF":4.0,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dynamic Event-Triggered-Based Iterative Filtering and Fault Compensation for PMSG-Based Wind Turbine Systems Under Deception Attack 欺骗攻击下pmsg风力发电系统的动态事件触发迭代滤波与故障补偿

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-14 DOI: 10.1109/TCSII.2025.3542156

Yang Gu;Mouquan Shen;Ju H. Park;Guangdeng Zong;Tingwen Huang

引用次数: 0

A General Form for the Extra Element Theorem 额外元素定理的一般形式

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-14 DOI: 10.1109/TCSII.2025.3542278

Ricardo Riaza

引用次数: 0

A Compact RF Module With Hybrid Stacked Transformer and Integrated Transceiver Switch in 65 nm CMOS Technology 基于65nm CMOS技术的混合堆叠变压器和集成收发器开关的紧凑射频模块

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-13 DOI: 10.1109/TCSII.2025.3541586

Yuting Chen;Qing Guo;Yue Ma;Xingang Ren;Bo Wu;Gang Wang;Xianliang Wu

{"title":"A Compact RF Module With Hybrid Stacked Transformer and Integrated Transceiver Switch in 65 nm CMOS Technology","authors":"Yuting Chen;Qing Guo;Yue Ma;Xingang Ren;Bo Wu;Gang Wang;Xianliang Wu","doi":"10.1109/TCSII.2025.3541586","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3541586","url":null,"abstract":"In this brief, we propose an RF module that integrates a Doherty power amplifier (PA), a low noise amplifier (LNA), and a transceiver (TRX) switch. This configuration enables transmitter (TX) and receiver (RX) mode conversion using a single MOSFET as a switch and a hybrid stacked transformer (HSTF) that covers just 0.0182 mm2. The HSTF co-designs the output matching network (OMN) of the Doherty PA and the input matching network (IMN) of the LNA, thereby reducing insertion loss and significantly miniaturizing the RF front-end. The introduction of an adjustable capacitor bank helps in regulating the parasitic capacitance generated by different operating modes in the HSTF. The 35–41 GHz TRX front-end is implemented in a 65 nm CMOS (1P9M) process. In the TX mode, the high saturated output power (Psat), 1-dB output compression point (OP1dB) and peak power added efficiency (PAE) are measured as 18.6 dBm, 17.7 dBm, and 25.8% at 38 GHz, respectively. The measured PAE at 6-dB and 9-dB power back-off (PBO) efficiency are 18.3% and 13.7%, resulting in efficiency enhancement ratios of 1.46 and 1.51 when compared with an ideal class-B PA. In the RX mode, the minimum noise figure (NF) is 4.8 dB at 38 GHz. The overall chip size of the TRX, including the three-stage PA/LNA and I/O pads, is approximately <inline-formula> <tex-math>$1.34times 0.98$ </tex-math></inline-formula> mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"549-553"},"PeriodicalIF":4.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Practical Prescribed-Time Tracking Control for High-Order Nonholonomic Systems With Matched and Mismatched Uncertainties 具有匹配和不匹配不确定性的高阶非完整系统的实用规定时间跟踪控制

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-13 DOI: 10.1109/TCSII.2025.3541963

Jiaping Qiang;Li Li;Yuanqing Xia;Xiangyi Ren;Yipeng Cao

引用次数: 0

A 140-GHz CMOS Four-Way Power Combining Doherty Power Amplifier With Adaptive Biasing 带有自适应偏置的140 ghz CMOS四路功率组合多尔蒂功率放大器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-12 DOI: 10.1109/TCSII.2025.3541202

Junyuan Tu;Guohao He;Aguan Hong;Yuxin Yang;Xiang Yi;Pei Qin;Haoshen Zhu;Wenquan Che;Quan Xue

引用次数: 0

An 8-to-12-Bit Resolution-Reconfigurable SAR ADC With Fast-Window-Switching Technique 基于快速窗口切换技术的8- 12位分辨率可重构SAR ADC

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-12 DOI: 10.1109/TCSII.2025.3541236

Yuhua Liang;Shida Song;Zhangming Zhu

{"title":"An 8-to-12-Bit Resolution-Reconfigurable SAR ADC With Fast-Window-Switching Technique","authors":"Yuhua Liang;Shida Song;Zhangming Zhu","doi":"10.1109/TCSII.2025.3541236","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3541236","url":null,"abstract":"This brief presents a resolution-reconfigurable successive-approximation-register (SAR) analog-to-digital converter (ADC). The reconfigurable capacitor digital-to-analog converter (CDAC) is designed to support 8/10/12-bit resolution modes. In order to mitigate the nonlinearity introduced by capacitor mismatch and suppress the transition glitch during the most significant bit trial in 10/12-bit modes, the Fast-Window-Switching (FWS) technique is proposed. The FWS technique can improve the linearity of the ADC without increasing the total capacitance of the CDAC, thus reducing the chip area and the burden of input buffers. The prototype is fabricated in a 180-nm CMOS process and occupies an active area of 0.23mm2. On the condition of a sampling rate of 10-MS/s, the achieved SNDR and SFDR are 48.3dB and 60.8dB in the 8-bit mode. With the FWS performing its role in the 10/12-bit mode, the ADC achieves 59.2dB/65.5dB SNDR and 73.4dB/79.6dB SFDR, and consumes <inline-formula> <tex-math>$350mu $ </tex-math></inline-formula>W/<inline-formula> <tex-math>$580mu $ </tex-math></inline-formula>W at 1.8V supply.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"544-548"},"PeriodicalIF":4.0,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0