Efficient Hardware Architecture Design of K-Means Clustering Algorithm for AV1 Palette Mode Coding

Abstract

The palette mode is a specialized coding tool for coding screen content video in Alliance for Open Media Video 1 (AV1), and K-means clustering is a necessary step in the palette mode. However, the high computational complexity and the strong data dependency in K-means clustering impede real-time processing. To address these issues, we propose an efficient hardware architecture design for the K-means clustering algorithm. Firstly, we propose a fully pipelined hardware architecture with two data-interleaving optimization methods, including K-interleaving and block-interleaving. Then, we propose a novel method for reusing original pixel data, which is motivated by the fact that the input original pixels are the same for different coding blocks. Finally, we propose a parallelized architecture that features three “K-means Engine” modules, with reusing of the “Euclidean distance calculate” module to minimize area. Experimental results show that the proposed hardware architecture can process all K-means clustering for pixels in a superblock in 10246 cycles under 650MHz working frequency, which can achieve 4K@30fps real-time processing. To the best of our knowledge, our work is the first attempt to design a K-means clustering hardware accelerator for palette mode in AV1.