IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第8页

A 10-bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-loop Amplifier and Parallel Conversion Through Comparator Reusing 具有非线性补偿开环放大器和通过重复使用比较器进行并行转换的 10 位 500-MS/s 管排式 SAR ADC

IF 4.4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-17 DOI: 10.1109/tcsii.2024.3462557

Nannan Li, Hanrui Zhang, Bin Liu, Lei Pei, Jinfu Wang, Huanhuan Qi, Jie Zhang, Xiaofei Wang, Hong Zhang

引用次数: 0

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications 用于航空航天应用的新型抗辐射硬化、速度和功率优化型非易失性锁存器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-16 DOI: 10.1109/TCSII.2024.3460809

Shixing Li;Chenyi Wang;Zhongzhen Tong;Chao Wang;Bi Wang;Zhaohao Wang

引用次数: 0

A 275 μ W 81.5 dB-SNDR and 200 kS/s CT IDSM With an AC-OSA-Based Integrator Using CNRS and FIR DACs 一种275 μ W 81.5 dB-SNDR和200 kS/s CT IDSM，带有基于ac - sa的集成器，采用CNRS和FIR dac

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-16 DOI: 10.1109/TCSII.2024.3461338

Han Yang;Lin Huang;Xiangwei Zhang;Yuqi Wang;Qiankun Zhao;Ying Hou;Xiaosong Wang;Yu Liu

{"title":"A 275 μ W 81.5 dB-SNDR and 200 kS/s CT IDSM With an AC-OSA-Based Integrator Using CNRS and FIR DACs","authors":"Han Yang;Lin Huang;Xiangwei Zhang;Yuqi Wang;Qiankun Zhao;Ying Hou;Xiaosong Wang;Yu Liu","doi":"10.1109/TCSII.2024.3461338","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3461338","url":null,"abstract":"This brief presents an energy-efficient continuous-time incremental delta-sigma modulator (CT IDSM), where the first integrator employs a fourth-order feedforward-compensated amplifier based on an AC-coupled OTA-stacking amplifier (AC-OSA) and utilizes a charge neutralization reset scheme (CNRS). Extending the AC-OSA to incremental structures significantly improves the energy efficiency of the ADC. The core innovation is the use of CNRS for periodic resets, addressing common-mode (CM) disturbances and incomplete differential-mode (DM) signal resets caused by the conventional shorted integration capacitor scheme. Additionally, to enhance area and power efficiency when using high-tap FIR DACs in CT IDSMs, we propose an excess-loop-delay compensation (ELDC) FIR DAC suitable for single-bit (SB) architectures. A third-order single-loop SB CT IDSM with an eight-tap FIR DAC is fabricated in a 65nm CMOS process and achieves SNDR, SNR, and DR values of 81.5dB, 81.8dB, and 85dB, respectively at a Nyquist conversion rate of 200kS/s. The core area is 0.227mm2, and the ADC consumes \u0000<inline-formula> <tex-math>$275{mu }$ </tex-math></inline-formula>\u0000W. The Schreier (SNDR) figure-of-merit (FoM) is 167.1dB.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"23-27"},"PeriodicalIF":4.0,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bandwidth Extension Technique for Improving Jitter in Ring-VCO-Based Sub-Sampling PLLs 改善基于环形 VCO 的子采样 PLL 抖动的带宽扩展技术

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-13 DOI: 10.1109/TCSII.2024.3460072

Mehran Ghahramani;Hamed Hoznian;Amir Nikpaik

{"title":"A Bandwidth Extension Technique for Improving Jitter in Ring-VCO-Based Sub-Sampling PLLs","authors":"Mehran Ghahramani;Hamed Hoznian;Amir Nikpaik","doi":"10.1109/TCSII.2024.3460072","DOIUrl":"10.1109/TCSII.2024.3460072","url":null,"abstract":"This brief proposes a structure to enhance the bandwidth of type-I sub-sampling phase-locked loops (SSPLL) without compromising the loop stability. A voltage-controlled delay line (VCDL) is employed at the output of the voltage-controlled oscillator (VCO) to readjust the phase of the VCO. The delay of this VCDL is controlled based on the instantaneous phase of the VCO, extracted at the output of the phase detector. Using theoretical analysis and simulations, it is proved that the bandwidth of the VCO phase noise to the output phase noise transfer function can increase up to \u0000<inline-formula> <tex-math>$ {0.4f_{text {REF}}}$ </tex-math></inline-formula>\u0000 while maintaining phase margin. This enhanced bandwidth improves the VCO phase noise filtering strength of the PLL, leading to a superior jitter performance. The phase-domain model reveals a significant reduction in integrated jitter, compared to conventional type-I and type-II SSPLL, respectively. Furthermore, it is shown that the jitter reduction capability in the proposed loop remains robust against temperature and process variations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"123-127"},"PeriodicalIF":4.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parametric Interpolation Model Order Reduction on Grassmann Manifolds by Parallelization 通过并行化减少格拉斯曼曼图谱上的参数插值模型阶次

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-13 DOI: 10.1109/TCSII.2024.3460171

Kang-Li Xu;Zhen Li;Peter Benner

引用次数: 0

In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET 使用混合 VGSOT-MTJ/GAA-CNTFET 的基于互补感应时间读出电路的 In-MRAM 计算技术

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-13 DOI: 10.1109/TCSII.2024.3460169

Zhongzhen Tong;Sifan Sun;Kaili Zhang;Chenghang Li;Daming Zhou;Zhaohao Wang;Xiaoyang Lin;Weisheng Zhao

{"title":"In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET","authors":"Zhongzhen Tong;Sifan Sun;Kaili Zhang;Chenghang Li;Daming Zhou;Zhaohao Wang;Xiaoyang Lin;Weisheng Zhao","doi":"10.1109/TCSII.2024.3460169","DOIUrl":"10.1109/TCSII.2024.3460169","url":null,"abstract":"Gate-all-around carbon nanotube field-effect-transistors (GAA-CNTFETs) and voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) are expected to realize significant savings in energy consumption and computing delay compared to the existing silicon-based FinFETs. This brief proposes an in-MRAM computing macro based on a newly developed complementary-sensing time-based readout circuit (CSTRC) to accelerate binary neural networks (BNNs). An 8 kb MRAM was simulated using both GAA-CNTFET/VGSOT-MTJ and 14 nm FinFET/VGSOT-MTJ technologies to validate the effectiveness of the proposed design. The proposed CSTRC can achieve read operations and binary multiply-and-accumulate (BMAC) without additional peripheral circuits and achieve a notable decrease in the read bit error rate and column-level conditional row error rate by 1–5 and 1–13 orders of magnitude, respectively, compared to those reported previously. Moreover, under the GAA-CNTFET/VGSOT-MTJ process, the read energy consumption and delay were reduced by 59.1–78.9% and 23.9–29.7%, respectively; the BMAC energy efficiency and throughput were 10231 1-b TOPS/W and 1.8 TOPS, respectively increased by 2.9 and 1.27 times at 0.8 V supply voltage when comparing to its 14-nm FinFET /VGSOT-MTJ counterparts.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"173-177"},"PeriodicalIF":4.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low Quiescent Current Fast Transient LDO Regulator With Segmented Pass Transistors 采用分段式通过晶体管的低静态电流快速瞬态 LDO 稳压器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-12 DOI: 10.1109/TCSII.2024.3458975

Yani Li;Zonghui Li;Libo Qian;Xiudeng Wang;Zhangming Zhu

{"title":"A Low Quiescent Current Fast Transient LDO Regulator With Segmented Pass Transistors","authors":"Yani Li;Zonghui Li;Libo Qian;Xiudeng Wang;Zhangming Zhu","doi":"10.1109/TCSII.2024.3458975","DOIUrl":"10.1109/TCSII.2024.3458975","url":null,"abstract":"This brief proposes a low quiescent current fast transient low-dropout regulator (LDO). The pass field-effect transistor (FET) in the LDO is segmented into three sections to cope with different loads. Under no-load mode, the smallest-sized pass transistor is directly driven by the error amplifier (EA) for low quiescent current. At light- and heavy- load modes, the medium and largest sized pass FETs are respectively switched on by different strength buffers for fast transient response. The proposed LDO is implemented in a \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000m BCD process with an active area of 0.0875 mm2. The LDO consumes a quiescent current of 25 nA at no-load condition, with an input voltage range of 1.5 V-5.5 V and an output voltage range of 1.2 V-5 V. The measured transient output voltage is 28 mV when load current is switched from 0 mA to 200 mA in 100 ns with \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000 F load capacitance. The recovery time is about \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000s. Compared to reported counterparts, the proposed LDO shows an excellent figure-of-merit (FOM).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"13-17"},"PeriodicalIF":4.0,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Closed-Form Expressions for the Input Impedance of Some 2-D Fractal Circuit Networks 某些二维分形电路网络输入阻抗的封闭式表达式

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-12 DOI: 10.1109/TCSII.2024.3459091

Ahmed S. Elwakil;Anis Allagui;Mohamed B. Elamien;Costas Psychalinos;Brent Maundy

引用次数: 0

LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators LTE：轻量级、定时高效的不等规模多项式乘法加速器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-11 DOI: 10.1109/TCSII.2024.3458871

Yazheng Tu;Tianyou Bao;Pengzhou He;Leonel Sousa;Jiafeng Xie

{"title":"LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators","authors":"Yazheng Tu;Tianyou Bao;Pengzhou He;Leonel Sousa;Jiafeng Xie","doi":"10.1109/TCSII.2024.3458871","DOIUrl":"10.1109/TCSII.2024.3458871","url":null,"abstract":"Integer polynomial multiplication has been frequently used in post-quantum cryptography and fully homomorphic encryption systems. Particularly, there exists a special polynomial multiplication, where the polynomial degree can be a power of two and the coefficients of the two input polynomials are unequal-sized (difficult to deploy fast algorithm for implementation efficiency). Following this direction, in this brief, we propose a novel hardware-implemented Lightweight and Timing-Efficient (LTE) integer polynomial multiplication design framework. We proposed two new algorithms for efficient implementation of the targeted polynomial multiplication. Accordingly, we presented two hardware accelerators with the help of several new hardware design techniques. The final implementation showcases the proposed accelerators’ superior performance, e.g., the proposed Accelerator-I \u0000<inline-formula> <tex-math>$(v=512)$ </tex-math></inline-formula>\u0000 has 44.7% less equivalent area-delay product (EADP) than the state-of-the-art design for \u0000<inline-formula> <tex-math>$n=4,096$ </tex-math></inline-formula>\u0000, while the proposed Accelerator-II has at least 38.7% less ADP than the competing designs for \u0000<inline-formula> <tex-math>$n=1,024$ </tex-math></inline-formula>\u0000. The proposed strategy is highly efficient and can be extended for other usage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"253-257"},"PeriodicalIF":4.0,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142193386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm 使用最小正形式和 Winograd 快速算法的高效并行可缩放大型整数乘法器架构

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-10 DOI: 10.1109/TCSII.2024.3457494

Jianfei Wang;Jia Hou;Fahong Zhang;Yishuo Meng;Yang Su;Chen Yang

引用次数: 0