IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第8页

ScaDA-Rou: A Scalable, Deadlock-Free, and Adaptive Routing for 3-D Multi-Chiplet System ScaDA-Rou：三维多芯片系统的可扩展、无死锁和自适应路由

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-01-30 DOI: 10.1109/TCSII.2026.3659753

Lijing Zhu;Huaxi Gu;Yun Tan;Guangming Zhang

{"title":"ScaDA-Rou: A Scalable, Deadlock-Free, and Adaptive Routing for 3-D Multi-Chiplet System","authors":"Lijing Zhu;Huaxi Gu;Yun Tan;Guangming Zhang","doi":"10.1109/TCSII.2026.3659753","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3659753","url":null,"abstract":"With the rapid advancement of high-performance computing and AI applications, the demand for computational power has escalated dramatically. Chiplet technology has emerged as a pivotal solution to meet increasingly complex computational requirements. Three-dimension integration technology has further enabled three-dimensional chiplet systems to achieve high-density computing, offering substantial computational capabilities. However, combining several chiplets into a single system-on-chip (SoC) presents serious deadlock concerns between processor units and chiplets. To address this challenge, this brief presents ScaDA-Rou, a scalable, deadlock-free, and adaptive routing algorithm specifically designed for 3D chiplet systems. ScaDA-Rou combines the turn model with virtual network partitioning to efficiently avoid deadlocks while optimizing network performance. In-plane deadlocks are avoided by setting turn restrictions in the routers. In addition, deadlocks among different planes are avoided by separating the virtual channels used for the source and destination planes of the cross-plane packets. The benchmark results demonstrate that ScaDA-Rou achieves, on average, performance improvement of 89.2% in latency under various synthetic traffic and system sizes. Moreover, with several real application trace scenarios, ScaDA-Rou achieves higher performance compared with traditional routing algorithms.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"433-437"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1.2-ns Delay Level Shifter Circuit Using Multiple Fast Charging, Discharging, and Feed-Forward Paths 使用多个快速充电、放电和前馈路径的1.2 ns延迟电平移位电路

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-25 DOI: 10.1109/TCSII.2026.3667894

Amir Aghajani;Mohammad Makhdoumi Akram;Reza Bostani;Ahmad Hassan;Benoit Gosselin

{"title":"A 1.2-ns Delay Level Shifter Circuit Using Multiple Fast Charging, Discharging, and Feed-Forward Paths","authors":"Amir Aghajani;Mohammad Makhdoumi Akram;Reza Bostani;Ahmad Hassan;Benoit Gosselin","doi":"10.1109/TCSII.2026.3667894","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3667894","url":null,"abstract":"This brief presents a new high-speed, low-power level shifter circuit capable of converting low-voltage input pulses to high-voltage output pulses with minimal propagation delay and dynamic power consumption. The proposed architecture leverages fast feed-forward, charging and discharging paths to enhance speed and energy efficiency, making it suitable for high-performance and high-speed applications such as system-on-chip (SoCs), high-speed memories, and FPGAs. Implemented in 130 nm TSMC CMOS technology, the circuit supports input voltages ranging from 200 mV to 0.8 V and converts them to a 1.2 V output. It achieves propagation delays of 1.19 ns and 0.34 ns for input voltages of 0.3 V and 0.4 V, respectively. The level shifter exhibits low energy consumption, with average energy per transition measured at 16.22 fJ and 14.92 fJ for 0.3 V and 0.4 V inputs, respectively. The total silicon area of the circuit is <inline-formula> <tex-math>$49.4~mu $ </tex-math></inline-formula>m<sup>2</sup>. We show that the presented design outperforms recent solutions.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"393-397"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12-bit 200-MS/s SAR ADC With Capacitor-Reuse-Based Redundant Weighting Technique 基于电容复用冗余加权技术的12位200ms /s SAR ADC

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-03-02 DOI: 10.1109/TCSII.2026.3669414

Angyang Li;Yi Shen;Anji Huang;Shubin Liu;Ruixue Ding;Zhangming Zhu

引用次数: 0

A High Efficiency Doherty Power Amplifier MMIC With Active Second Harmonic Injection Technique 采用主动二次谐波注入技术的高效多赫蒂功率放大器MMIC

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1109/TCSII.2026.3663733

Lin Yang;Shihua Liu;Xingyuan Fu;Ming Zhang;Baozhu Wang;Qi Han;YuHang He;Weimin Hou

{"title":"A High Efficiency Doherty Power Amplifier MMIC With Active Second Harmonic Injection Technique","authors":"Lin Yang;Shihua Liu;Xingyuan Fu;Ming Zhang;Baozhu Wang;Qi Han;YuHang He;Weimin Hou","doi":"10.1109/TCSII.2026.3663733","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3663733","url":null,"abstract":"In this brief, a novel design methodology for Doherty power amplifier (DPA) MMIC is proposed to improve the efficiency of the DPAs. The design equations of a compact harmonic-controlled bias network (CHCBN) are derived, which can achieve inverse class-F amplifier load conditions with adjustable fundamental frequency impedance, this approach effectively improves the saturated and back-off efficiency of the DPA. An active second harmonic injection network (HIN) is proposed which utilizes the second harmonic components generated by the carrier and peaking devices for mutual injection to achieve the amplitude modulation of the DPA drain waveform in the saturated state, further improving the saturated efficiency of the DPA. To validate the methodology, a C-band high efficiency DPA MMIC is designed and fabricated in a <inline-formula> <tex-math>$0.25~mu $ </tex-math></inline-formula>m GaN-HEMT process. The measurement results show that the fabricated DPA exhibits the saturated output power (Psat) of 39.6 dBm–40.6 dBm, with a saturated drain efficiency (DE) of 53.9%–61.5%, and a 6-dB back-off DE of 51.4%–56.0% over the 4.8-5.4 GHz frequency band. The proposed DPA demonstrates the highest 6-dB back-off efficiency among the published broadband GaN MMIC DPAs operating in similar frequency band.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"443-447"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comprehensive High-to-Low Delay Model for NCFET Circuits NCFET电路的综合高低延迟模型

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-16 DOI: 10.1109/TCSII.2026.3665021

Ananda Sankar Chakraborty;Ali M. Niknejad

引用次数: 0

A 47-nA Quiescent Current Dual-Mode Buck Converter With Fast Load Transient Response From Ultra-Light Load Mode 在超轻负载模式下具有快速负载瞬态响应的47-nA静态电流双模降压变换器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-25 DOI: 10.1109/TCSII.2026.3668052

Dongxu Li;Yanqi Zheng;Xian Tang

{"title":"A 47-nA Quiescent Current Dual-Mode Buck Converter With Fast Load Transient Response From Ultra-Light Load Mode","authors":"Dongxu Li;Yanqi Zheng;Xian Tang","doi":"10.1109/TCSII.2026.3668052","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3668052","url":null,"abstract":"This brief proposes a dual-mode ultra-low quiescent current buck converter that achieves high efficiency over a wide load range. The system employs adaptive on-time control (AOT) for heavy load and adaptive clock control (ACC) for light load. To enhance transient performance under light load, a fast clock frequency locking (FCFL) circuit is proposed to enable quick load tracking with simple digital logic. Additionally, a nA low-power load step transient enhancement (LSTE) circuit is presented, effectively reducing overshoot and undershoot during load transients. The converter is implemented in a <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m process and operates with an input voltage of 2.4 V to 3.3 V and an output of 1.6 V. The load current ranges from 500 nA to 300 mA. The total quiescent current is 47 nA contributed to ACC digital control and it achieves 87% efficiency at <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>A load current, with a peak efficiency of 95.9% at 2.4V input. It achieves an undershoot voltage of 60 mV with recovery time of <inline-formula> <tex-math>$6~mu $ </tex-math></inline-formula>s when load current switching from <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>A to 100 mA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"398-402"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Suppression of Low-Frequency Noise From Diode Forward Voltage Based on Chopper Stabilization in a Charge-Discharge Capacitive Sensing Circuit 基于斩波稳定的充放电电容感测电路中二极管正向电压低频噪声抑制

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-03-03 DOI: 10.1109/TCSII.2026.3670226

Han Wu;Zheyu Yu;Zhihao Liu;Hui Chen;Cheng Ma;Shaobo Qu;Yanzheng Bai;Zebing Zhou

{"title":"Suppression of Low-Frequency Noise From Diode Forward Voltage Based on Chopper Stabilization in a Charge-Discharge Capacitive Sensing Circuit","authors":"Han Wu;Zheyu Yu;Zhihao Liu;Hui Chen;Cheng Ma;Shaobo Qu;Yanzheng Bai;Zebing Zhou","doi":"10.1109/TCSII.2026.3670226","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3670226","url":null,"abstract":"Charge-discharge capacitive sensing circuit has the advantages of high precision, simple structure and low power consumption. However, its low-frequency noise performance is limited by the fluctuations of the forward voltage of the switching diodes in the ring-diode circuit. In this brief, a chopper stabilization circuit is designed by periodically interchanging the positions of the four diodes to suppress the low-frequency noise introduced by the ring-diode circuit. The principle is analyzed and the noise performance is validated. Experimental results show that this method can significantly suppress the low-frequency noise of the sensing circuit. At a carrier frequency of 2.5 MHz, the equivalent capacitance resolution of the sensing circuit at 0.01 Hz is improved from about 1.1 aF/Hz<inline-formula> <tex-math>${}^{mathrm {1/2}}$ </tex-math></inline-formula> to about 0.12 aF/Hz<inline-formula> <tex-math>${}^{mathrm {1/2}}$ </tex-math></inline-formula>. The optimized sensing circuit can promote the application in fields with high requirements for low-frequency performance, such as space inertial sensors and planetary seismometers.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"428-432"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 37–48 GHz Frequency Doubler With >47.8 dBc FRR Utilizing a Staggered Fundamental Suppression Technique 采用交错基波抑制技术的37 - 48ghz倍频器，频域比为>47.8 dBc

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-03 DOI: 10.1109/TCSII.2026.3660904

Yuyang Chen;Chao Yang;Xiaoming Liu;Jing Jin;Jianjun Zhou

引用次数: 0

A Direct-Capacitance-Conversion FeRAM Characterization Platform for Enabling Non-Destructive 3-D Ferroelectric Capacitor Readout 实现非破坏性三维铁电电容读出的直接电容转换FeRAM表征平台

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-26 DOI: 10.1109/TCSII.2026.3668123

Xiongfei Jiang;Chaohan Wang;Yang Xiang;Shiwei Wang;Themis Prodromakis;Marie Garcia Bardon;Jan Van Houdt;Fernando Garcia Redondo;Dwaipayan Biswas

{"title":"A Direct-Capacitance-Conversion FeRAM Characterization Platform for Enabling Non-Destructive 3-D Ferroelectric Capacitor Readout","authors":"Xiongfei Jiang;Chaohan Wang;Yang Xiang;Shiwei Wang;Themis Prodromakis;Marie Garcia Bardon;Jan Van Houdt;Fernando Garcia Redondo;Dwaipayan Biswas","doi":"10.1109/TCSII.2026.3668123","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3668123","url":null,"abstract":"Ferroelectric-capacitor-based memory (FeRAM) is a promising emerging non-volatile memory technology that offers fast access and high endurance. Recent studies have demonstrated Ferroelectric-capacitor-based memory (FeRAM) has the potential to support Non-Destructive Readout (NDRO) as well as 3D stacking, enabling read operations that do not disturb or minor disturb the stored polarization state and higher density. However, variations in ferroelectric materials and layer structures lead to diverse hysteresis behaviors, resulting in different sensing requirements. In addition, the reduced capacitor size in deeply stacked 3D architectures further decreases the available charge, making accurate readout increasingly challenging. To better understand these issues, this work presents a highly scalable direct-capacitance-conversion characterization circuit that is capable of extracting the equivalent ferroelectric capacitance from a 3D FeRAM array. Leveraging a continuous-time delta-sigma modulator (CTDSM), the proposed platform can accurately quantize small ferroelectric equivalent capacitances ranging from 0 to 72fF with low noise and high resolution, and achieves a capacitance resolution of <inline-formula> <tex-math>$0.045mathrm {fF_{rms}}$ </tex-math></inline-formula> while consuming only <inline-formula> <tex-math>$3mu $ </tex-math></inline-formula>W power and occupying 0.001mm<sup>2</sup> chip area under a 22nm FDSOI technology. These results demonstrate the capability to characterize 3D FeRAM arrays with up to 64 vertically stacked ferroelectric capacitors (FeCAPs) and highlight strong scalability for large-scale FeRAM evaluation and design exploration.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"403-407"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compensation Techniques for Frequency and Gain Temperature Drift in Open-Loop VCO-ADCs 开环vco - adc频率和增益温度漂移补偿技术

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-04-01 Epub Date: 2026-02-19 DOI: 10.1109/TCSII.2026.3666238

Javier Granizo;Ruben Garvi;Victor Medina;Andres Quintero;Andreas Wiesbauer;Luis Hernandez

{"title":"Compensation Techniques for Frequency and Gain Temperature Drift in Open-Loop VCO-ADCs","authors":"Javier Granizo;Ruben Garvi;Victor Medina;Andres Quintero;Andreas Wiesbauer;Luis Hernandez","doi":"10.1109/TCSII.2026.3666238","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3666238","url":null,"abstract":"This manuscript presents two approaches to improve the temperature effects on ring oscillators used in open-loop VCO-ADCs. The first approach is a circuit design optimization, which is based on an analysis of the ring oscillator against temperature, considering both gain and frequency deviations. It is shown that ring oscillators can be biased in regions with stable frequency or gain. The second technique is an oscillator stabilization circuitry for differential VCO-ADCs. We propose a common-mode feedback circuit that tracks the VCO frequencies to tune the common bias point. Therefore, intrinsic VCO variations are also compensated by this feedback. A proof of concept chip demonstrating both techniques has been implemented in <inline-formula> <tex-math>$0.13mu $ </tex-math></inline-formula>m. The chip measurements show a frequency and gain drift of 6% and ±0.25dB respectively between -40°C to 100°C. These measurements are comparable to the results achieved by digital temperature calibration without requiring an on-chip temperature sensor.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"378-382"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0