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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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Small-Signal Modeling of an S-S Compensated IPT System Under Frequency Modulation 调频下S-S补偿IPT系统的小信号建模
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582261
Tianqi Li;Guangce Zheng;Chaoqun Qi;Haoyu Wang;Yu Liu;Minfan Fu
{"title":"Small-Signal Modeling of an S-S Compensated IPT System Under Frequency Modulation","authors":"Tianqi Li;Guangce Zheng;Chaoqun Qi;Haoyu Wang;Yu Liu;Minfan Fu","doi":"10.1109/TCSII.2025.3582261","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3582261","url":null,"abstract":"Frequency modulation is widely utilized in inductive power transfer systems and is also included in the Qi standard for low-power chargers. This brief examines small-signal modeling and simplification methods using an example of an S-S compensated system under frequency modulation. Initially, it develop models for the resonant components under frequency perturbation, which subsequently help in constructing the model of the resonant tank. By incorporating the models of the inverter and rectifier, it derives a sixth-order model for the entire system. The pole-zero analysis helps simplify this sixth-order model to a third-order and a first-order model. Experimental results show that these models can accurately predict the system’s control-to-output gain up to 1/2, 2/5, and 1/10 of the switching frequency. These models effectively illustrate the impacts of circuit parameters and the trade-offs between accuracy and complexity.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1113-1117"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single-Event Upset Monitor-Based Radiation-Hardened Latch for Multi-Node Upset 基于单事件镦粗监视器的多节点镦粗辐射硬化闩锁
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582493
Zhan Zheyu;Liu Hainan;Li Duoli;Ma Quangang;Zhao Wenxin;Yan Zhenzhen;Li Bo
{"title":"Single-Event Upset Monitor-Based Radiation-Hardened Latch for Multi-Node Upset","authors":"Zhan Zheyu;Liu Hainan;Li Duoli;Ma Quangang;Zhao Wenxin;Yan Zhenzhen;Li Bo","doi":"10.1109/TCSII.2025.3582493","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3582493","url":null,"abstract":"This brief describes a novel latch design, the Single-Event Upset (SEU) monitoring-based Radiation Hardened Latch (SMRHL), which is robust under multi-node upset (MNU) conditions. The SEU monitoring circuit of SMRHL is designed to detect the presence of SEU events inside the latch and trigger alarm signals accordingly, thus ensuring that the SMRHL can output correct data. The simulation results demonstrate that the proposed SMRHL minimizes the number of SEU-sensitive nodes and achieves a significant improvement of up to 57.9X in power-delay-area-product compared to other state-of-the-art MNU latches. Additionally, the SMRHL’s capability to generate SEU alarm signals enhances reliability at the system architecture level.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1093-1097"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs 具有高偏置容限的体偏混合感测放大器，用于低压sram
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582549
Minglong Jia;Pengyuan Zhao;Linnan Li;Xiang Li;Zhi Li;Huidong Zhao;Shushan Qiao
{"title":"Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs","authors":"Minglong Jia;Pengyuan Zhao;Linnan Li;Xiang Li;Zhi Li;Huidong Zhao;Shushan Qiao","doi":"10.1109/TCSII.2025.3582549","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3582549","url":null,"abstract":"The offset voltage (VOS) of the Sense Amplifier (SA) is a critical parameter that affects sensing delay and energy consumption in SRAM. This brief proposes a Body-Biased Hybrid Sense Amplifier (BHSA) that effectively reduces the standard deviation (<inline-formula> <tex-math>$sigma {_{text {OS}}}$ </tex-math></inline-formula>) of VOS in low-voltage SRAM applications without need for the additional capacitors or auxiliary control circuits. Results of post-simulation demonstrate that the BHSA shows an average 44% reduction in <inline-formula> <tex-math>$sigma {_{text {OS}}}$ </tex-math></inline-formula> compared to the VLSA across the 0.3-0.9 V supply voltage range, with a specific reduction of 49.4% achieved at 0.3 V. Two 16 kb SRAMs with integrated BHSA and VLSA, respectively, were fabricated under the 22 nm FDSOI technology. Measurements indicates that the SRAM with integrated BHSA achieves a 48.2% reduction in bitline discharge delay and a 13.7% decrease in read power consumption at 0.45 V compared to traditional designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1098-1102"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination UniPRE：具有统一最大池预测和冗余消除的SNN-ANN加速器
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3582265
Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang
{"title":"UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination","authors":"Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang","doi":"10.1109/TCSII.2025.3582265","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3582265","url":null,"abstract":"The integration of Spiking Neural Networks (SNNs) and Artificial Neural Networks (ANNs) for specific tasks has attracted considerable interest due to their potential for high energy efficiency and accuracy. In SNN-ANN fused hardware, many works focus on neuron-level fusion of operators. Though some have explored optimizations at the dataflow level, they are restricted to only one kind of networks. This brief introduces a dataflow-level unified predicting method to eliminate redundant computations resulted from max-pooling operations for both SNN and ANN by exploiting Channel-wise Importance (CI). An accelerator with online sorting of Channel-wise Importance (CI) to support this optimization is also proposed, named as UniPRE. Results show that UniPRE reduces 44.77% and 31.85% overall computations with negligible accuracy loss for SNN and ANN using 37.5% channels for prediction. Implemented in the standard 28-nm CMOS technology, UniPRE can reach an energy efficiency of 19.32 TSOPS/W and 4.26 TOPS/W, with an area efficiency of 370.10 GSOPS/mm2 and 92.52 GOPS/mm2 for SNN and ANN paradigms of 8-bit weight precision, respectively. In layer-wise evaluation of real networks, up to <inline-formula> <tex-math>$1.79times $ </tex-math></inline-formula> energy reduction is achieved with 25% channels used for prediction.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1088-1092"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HIMAM: Hardware Implementation of Multiply-and-Max/Min Layers for Energy-Efficient DNN Inference 高效DNN推理的乘和最大/最小层的硬件实现
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-20 DOI: 10.1109/TCSII.2025.3581784
Fanny Spagnolo;Pasquale Corsonello;Stefania Perri
{"title":"HIMAM: Hardware Implementation of Multiply-and-Max/Min Layers for Energy-Efficient DNN Inference","authors":"Fanny Spagnolo;Pasquale Corsonello;Stefania Perri","doi":"10.1109/TCSII.2025.3581784","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3581784","url":null,"abstract":"This Brief presents HIMAM: the first hardware implementation of the Multiply-and-Max/Min (MAM) layers, recently proposed as an effective alternative to the traditional Multiply-and-Accumulate (MAC) paradigm used in Deep Neural Networks (DNNs). The proposed design relies on a specialized hardware architecture that uses floating-point arithmetic and was devised to implement the unconventional multiply then compare-and-add pipeline involved in MAM layers. Based on the observation that such a paradigm actually requires just few product operations to be accurately computed, we propose to replace the most computational intensive components with approximate ones. The FPGA-based implementation carried out on a Zynq Ultrascale+ device and operating in 32-bit floating-point mode exhibits 10.91 GFLOPS/W. When implemented on a 28-nm FDSOI technology process, such an architecture dissipates only 5.3 mW running at 250 MHz, which is at least 41.7% lower than the MAC-based state-of-the-art hardware architectures.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1083-1087"},"PeriodicalIF":4.9,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11045655","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digitally Calibrated Redundancy-Based String DAC: A Novel Architecture for Enhanced Static Linearity 基于数字校准冗余的字符串DAC：一种增强静态线性度的新架构
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-20 DOI: 10.1109/TCSII.2025.3581545
Isaac Bruce;Emmanuel Nti Darko;Ekaniyere Oko Odion;Matthew Crabb;Degang Chen
{"title":"Digitally Calibrated Redundancy-Based String DAC: A Novel Architecture for Enhanced Static Linearity","authors":"Isaac Bruce;Emmanuel Nti Darko;Ekaniyere Oko Odion;Matthew Crabb;Degang Chen","doi":"10.1109/TCSII.2025.3581545","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3581545","url":null,"abstract":"This brief introduces a three-segment resistor string ladder DAC featuring built-in redundancy and sub-radix transfer characteristics. The architecture implements digital calibration to optimize the linearity-resolution tradeoff, achieving substantial area reduction compared to conventional string DAC designs. Measurement and simulation results are presented validating the architecture’s performance. Mathematical analysis is presented revealing a fundamental 1 LSB lower bound on the best achievable post-calibration differential nonlinearity (DNL) for 1-bit redundancy cases. To address this limitation, we present two alternative architectures that demonstrate improved post-calibration DNL performance.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1343-1347"},"PeriodicalIF":4.9,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-GHz CMOS Power Amplifier With Adaptive Bias and Phase Compensation for Gain and Phase Linearity Enhancement 一种具有自适应偏置和相位补偿的28 ghz CMOS功率放大器，用于增益和相位线性增强
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-19 DOI: 10.1109/TCSII.2025.3581383
Liang-Chen Tsai;Zheng-Jie Li;Liang-Hung Lu
{"title":"A 28-GHz CMOS Power Amplifier With Adaptive Bias and Phase Compensation for Gain and Phase Linearity Enhancement","authors":"Liang-Chen Tsai;Zheng-Jie Li;Liang-Hung Lu","doi":"10.1109/TCSII.2025.3581383","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3581383","url":null,"abstract":"This brief presents a 28-GHz PA fabricated in the TSMC 90-nm CMOS process for 5G wireless communication phased-array transmitters. The proposed PA incorporates adaptive bias and phase compensation techniques to effectively mitigate AM-AM and AM-PM distortions, achieving high linearity and efficiency. The design features an envelope detector for dynamic bias adjustment, enhancing transconductance to reduce AM-AM distortion. Furthermore, a varactor-based phase correction mechanism is implemented to minimize AM-PM distortion. This brief improves both gain and phase control networks, resulting in significant improvements in key performance metrics, including <inline-formula> <tex-math>$OP_{1dB}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$PAE_{P1dB}$ </tex-math></inline-formula>, and maximum phase distortion before <inline-formula> <tex-math>$P_{1dB}$ </tex-math></inline-formula>. The proposed PA achieves an <inline-formula> <tex-math>$OP_{1dB}$ </tex-math></inline-formula> of 14.4 dBm, a <inline-formula> <tex-math>$PAE_{P1dB}$ </tex-math></inline-formula> of 33.6%, and a maximum AM-PM distortion of 1.5°, demonstrating exceptional performance and scalability for phased-array applications in next-generation millimeter-wave systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1028-1032"},"PeriodicalIF":4.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Calibration-Free Edge-Computing IMC Macro With Direct Current-to-Digital Conversion 具有直流数字转换的免校准边缘计算IMC宏
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-19 DOI: 10.1109/TCSII.2025.3581384
Andrea Fasolino;Rosalba Liguori;Luigi Di Benedetto;Alfredo Rubino;Gian Domenico Licciardo
{"title":"Calibration-Free Edge-Computing IMC Macro With Direct Current-to-Digital Conversion","authors":"Andrea Fasolino;Rosalba Liguori;Luigi Di Benedetto;Alfredo Rubino;Gian Domenico Licciardo","doi":"10.1109/TCSII.2025.3581384","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3581384","url":null,"abstract":"In-memory computing (IMC) has emerged as a promising solution to the “memory wall” problem of traditional Von Neumann architectures by integrating computation directly within the memory. This brief presents a novel current-mode IMC macro that leverages a nanoampere-range temperature-independent reference current and direct current-to-digital conversion. The proposed design mitigates power inefficiencies and thermal instability of previous architectures without the need for calibration. Implemented in TSMC LP 65 nm CMOS technology, the design achieves an energy efficiency of 310.7 TOPS/W and an area efficiency of 18.93 TOPS/mm2. The reference current generator ensures a temperature coefficient of just 363 ppm/°C over a temperature <inline-formula> <tex-math>$in $ </tex-math></inline-formula> [-10; 115]° C. Using a VGG-6 model on the CIFAR-10 dataset with 87.93% accuracy, the drop between the software baseline model and IMC hardware (1bA/1bW/5bO) at TT@27°C/FF@115°C/SS@-10°C is 0.17/0.32/0.51%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1018-1022"},"PeriodicalIF":4.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mamba-Unet-Depth: Enhancing Long-Range Dependency for Photon-Efficient Imaging Mamba-Unet-Depth：增强光子高效成像的远程依赖性
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-18 DOI: 10.1109/TCSII.2025.3580670
Yanyun Pu;Chengyuan Zhu;Gongxin Yao;Yu Pan;Kaixiang Yang;Qinmin Yang
{"title":"Mamba-Unet-Depth: Enhancing Long-Range Dependency for Photon-Efficient Imaging","authors":"Yanyun Pu;Chengyuan Zhu;Gongxin Yao;Yu Pan;Kaixiang Yang;Qinmin Yang","doi":"10.1109/TCSII.2025.3580670","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580670","url":null,"abstract":"With the rapid development of single-photon LiDAR, accurate depth recovery remains a key challenge. Conventional deep learning methods, such as CNNs and ViTs, leverage convolution and self-attention to extract local and global features, respectively. However, these models struggle to capture long-range dependencies in depth images, especially under low signal-to-background ratio (SBR) conditions. To address this, we propose Mamba-Unet-Depth, a novel network inspired by the Mamba architecture, which models long sequences and global context efficiently. By combining the hierarchical representation capability of U-Net with Mamba’s sequential modeling strength, the proposed model uses skip connections to retain spatial details across scales, facilitating richer feature learning. This enables more effective extraction of both fine-grained and contextual depth cues in challenging LiDAR data. Experimental results on the NYU Depth v2 dataset show that Mamba-Unet-Depth outperforms existing baselines in depth prediction accuracy and robustness, achieving state-of-the-art performance.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1123-1127"},"PeriodicalIF":4.9,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Discharge Correction Under Asymmetric Electrode-Electrolyte Interfaces in Bipolar Stimulation 双极刺激中不对称电极-电解质界面下的放电校正
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-18 DOI: 10.1109/TCSII.2025.3580714
Jialei Wu;Simeng Yin;Yixin Zhou;Keping Wang
{"title":"Discharge Correction Under Asymmetric Electrode-Electrolyte Interfaces in Bipolar Stimulation","authors":"Jialei Wu;Simeng Yin;Yixin Zhou;Keping Wang","doi":"10.1109/TCSII.2025.3580714","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580714","url":null,"abstract":"Neural electrical stimulators have been widely used in biomedical applications, especially those with multiple channels. However, the electrode-electrolyte interfaces are usually not identical, which is rarely discussed in stimulator design. This brief first analyzes the stimulation and discharge phases in bipolar stimulation when the interfaces are not identical, proving that the asymmetry will lead to incomplete discharge. To address this issue, we propose a tripolar stimulator by introducing a return electrode to discharge the working and counter electrodes separately. The prototype of a 4-channel tripolar stimulator is designed and fabricated in a 180-nm CMOS technology, with each stimulation channel occupying 0.176 mm2. The maximum stimulation current is 2.8 mA. After discharge, residual voltages are near-zero in both electrical and in vitro tests.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1013-1017"},"PeriodicalIF":4.9,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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