IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第8页

A 1.8–5.5-V LDO–BGR System With LACM Buffer for High PSRR in Camera Applications 一种1.8 - 5.5 v带LACM缓冲的LDO-BGR系统，用于相机的高PSRR应用

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-11 DOI: 10.1109/TCSII.2025.3578616

Won-Gyu Kim;Sang-Yun Nam;Young-Jun Jeon;Sung-Wan Hong

引用次数: 0

Privacy-Preserving Optimal Battery Control for Energy Storage Systems Using Adaptive Dynamic Programming 基于自适应动态规划的储能系统保隐私最优电池控制

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-11 DOI: 10.1109/TCSII.2025.3578944

Jiaoni Wang;Jiayue Sun

引用次数: 0

A Switch-as-Resistor Self-Adaptive Gate-Biasing Technique for Optimized Forward and Reverse Conduction in a CMOS Rectifier 开关电阻自适应门偏置技术优化CMOS整流器正反导通

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-10 DOI: 10.1109/TCSII.2025.3578345

Yi Chen Lee;Harikrishnan Ramiah;Tian Siang Ho;Fu Qi Chua;Wen Xun Lian;Kishore Kumar Pakkirisami Churchill;Yong Chen

{"title":"A Switch-as-Resistor Self-Adaptive Gate-Biasing Technique for Optimized Forward and Reverse Conduction in a CMOS Rectifier","authors":"Yi Chen Lee;Harikrishnan Ramiah;Tian Siang Ho;Fu Qi Chua;Wen Xun Lian;Kishore Kumar Pakkirisami Churchill;Yong Chen","doi":"10.1109/TCSII.2025.3578345","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578345","url":null,"abstract":"This brief proposes a switch-as-resistor self-adaptive gate-biasing technique implemented in a 900 MHz single-stage cross-coupled rectifier for IoT and WSN applications. The proposed method employs NMOS switches as the resistive component (RRES), which are controlled by a rectangular signal from a CMOS inverter. This configuration adaptively enables (disables) the NMOS switches during reverse (forward) conduction phases, and self-adaptively provides gate-biasing, resulting in conserved forward charge with mitigated reverse charge. As a result, the output power is enhanced with higher charge accumulation at the output terminal. The circuit gives a measured result of 84.3% in peak power conversion efficiency (PCE) at an input power (PIN) of –21 dBm through a 100 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> load. The proposed circuit also achieves a 25 dB DR with a PCE of over 20%. With a compact chip area of 0.0105 mm2, the rectifier achieves the widest PDR of 25 dB and a sensitivity of –18 dBm under a 100 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> load. Compared to other state-of-the-art rectifiers, the proposed scheme demonstrates higher performance in terms of PDR and PCE.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1103-1107"},"PeriodicalIF":4.9,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Encoding–Decoding-Based State Estimation Scheme for State-Saturated Systems Under Buffer-Aided Mechanism 缓冲辅助下状态饱和系统的一种基于编解码的状态估计方案

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-10 DOI: 10.1109/TCSII.2025.3578535

Cong Huang;Li Zhu;Weiping Ding;Peng Mei;Shichun Yang;Quan Shi

{"title":"An Encoding–Decoding-Based State Estimation Scheme for State-Saturated Systems Under Buffer-Aided Mechanism","authors":"Cong Huang;Li Zhu;Weiping Ding;Peng Mei;Shichun Yang;Quan Shi","doi":"10.1109/TCSII.2025.3578535","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578535","url":null,"abstract":"In this brief, the encoding-decoding-based state estimation problem is investigated for a class of state-saturated systems under buffer-aided mechanism where the wireless communication is unreliable. The buffer-aided mechanism is exploited to improve the data utilization and estimation performance with the capability of storing the undelivered signals and then transmits them to the remote estimator at each transmission instant. To overcome inherent communication limitations, a novel probabilistic encoding-decoding scheme is introduced to compress the sensor measurements. The objective of this brief is to develop an encoding-decoding-based estimator such that the estimation error covariance is minimized in certain sense for all possible state saturations as well as the effects induced by buffer-aided mechanism. The estimation error covariance conditioned on the transmission intervals is first obtained in recursions and then is minimized by the choice of the appropriate estimator gain. Finally, simulation results are presented to demonstrate the validity of the proposed estimation scheme.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1043-1047"},"PeriodicalIF":4.9,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector 一种1.58 pJ/b 9gbps无参考时钟和数据恢复电路与Sigma距离检测器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-09 DOI: 10.1109/TCSII.2025.3577785

Jongchan An;Seung-Myeong Yu;Gwangmyeong An;Songi Cheon;Hyunsu Jang;Junyoung Song

引用次数: 0

A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network 基于t圈匹配网络的0.2-19GHz零中频可重构正交发射机

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-09 DOI: 10.1109/TCSII.2025.3577994

An Sun;Yaxin Zeng;Haoqi Qin;Hao Xu;Rui Yin;Xiaoliang Shen;Lifeng Bian;Na Yan

{"title":"A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network","authors":"An Sun;Yaxin Zeng;Haoqi Qin;Hao Xu;Rui Yin;Xiaoliang Shen;Lifeng Bian;Na Yan","doi":"10.1109/TCSII.2025.3577994","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3577994","url":null,"abstract":"This brief presents a 0.2-19GHz ultra-wideband reconfigurable transmitter in 28nm CMOS process. This brief is based on the analysis of the T-coil matching network, which defines the design boundaries for achieving wideband gain flatness in T-coil voltage transfer. The T-coil with capacitive and resistive loads is applied separately in the matching networks of the mixer and power amplifier (PA), enabling the proposed transmitter to achieve wideband frequency coverage. To achieve the image rejection ratio (IRR) across a wideband, two structures of divide-by-2 circuits are utilized to generate low phase error quadrature LO signals. Driven by the feedforward compensation transconductance amplifier (OTA), the analog baseband low pass filter(LPF) achieves a wide reconfigurable bandwidth(BW) and gain range. The proposed transmitter achieves 8.1-13.4dBm saturation output power(Psat) in a compact area of 1.08mm<inline-formula> <tex-math>${times }1.92$ </tex-math></inline-formula>mm(2.07mm2). The measured IRR and LO leakage suppression are better than 41dBc/38dBc. The baseband LPF BW is configurable from 100 to 500MHz and gain adjustment range is 20dB in 1.5dB step.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1023-1027"},"PeriodicalIF":4.9,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Ku-Band Broadband 8-Channel 8-Beam Phased-Array Receiver With Polarization Agility and Beam Reconfiguration for SATCOM Applications 一种具有极化敏捷性和波束重构的ku波段宽带8通道8波束相控阵接收机

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-09 DOI: 10.1109/TCSII.2025.3578020

Zhuoheng Xie;Yue Feng;Bo Huang;Zihan Zhang;Heng Zhao;Lan Liu;Zhihao Liu;Zhigang Li;Xiulong Wu

{"title":"A Ku-Band Broadband 8-Channel 8-Beam Phased-Array Receiver With Polarization Agility and Beam Reconfiguration for SATCOM Applications","authors":"Zhuoheng Xie;Yue Feng;Bo Huang;Zihan Zhang;Heng Zhao;Lan Liu;Zhihao Liu;Zhigang Li;Xiulong Wu","doi":"10.1109/TCSII.2025.3578020","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578020","url":null,"abstract":"This brief presents a Ku-band broadband 8-channel 8-beam phased-array receiver with polarization agility and dynamic beam reconfiguration, addressing the growing demand for Low Earth Orbit (LEO) and high-throughput satellite communications (SATCOM). The receiver chip integrates 32 independently controlled amplitude and phase channels, utilizing an innovatively designed reconfigurable power divider network to flexibly support single-beam, dual-beam, four-beam, and eight-beam modes, while enabling dynamic selection between horizontal and vertical polarization. Furthermore, the receiver system adopts a hybrid architecture combining a 6-bit active vector-modulated phase shifter and a 6-bit passive attenuator to achieve high-precision amplitude and phase control. Measurement results demonstrate a wide operational frequency range from 10 GHz to 15 GHz, achieving a remarkable channel gain of 24.5 dB and an input 1-dB gain compression point (IP1dB) exceeding 15.8 dBm. The root mean square (RMS) phase and amplitude errors are below 5.19° and 0.24 dB, respectively. Fabricated using a 0.18 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m SiGe Bi-CMOS process, the chip features a compact area of <inline-formula> <tex-math>$6.7 times 5.3,text {mm}^{2}$ </tex-math></inline-formula> and a total power consumption of less than 465 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"893-897"},"PeriodicalIF":4.0,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved Disturbance Rejection and Noise Suppression Properties for PMSM Speed Control Systems Using Different Order Fast Finite-Time Extended State Observers 利用不同阶快速有限时间扩展状态观测器改善PMSM速度控制系统的抗扰和噪声抑制性能

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-05 DOI: 10.1109/TCSII.2025.3577129

Qiankang Hou;Huanzhi Wang;Shihong Ding;Chen Ding;Christopher H. T. Lee

引用次数: 0

Memory Optimized, High Signal Quality Direct Digital Frequency Synthesizer on an FPGA 基于FPGA的内存优化、高信号质量直接数字频率合成器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-03 DOI: 10.1109/TCSII.2025.3576310

Kalle I. Palomäki;Jari Nurmi

{"title":"Memory Optimized, High Signal Quality Direct Digital Frequency Synthesizer on an FPGA","authors":"Kalle I. Palomäki;Jari Nurmi","doi":"10.1109/TCSII.2025.3576310","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3576310","url":null,"abstract":"Direct digital frequency synthesis is a method for generating digital samples of periodic analog signals. It has been broadly used for decades in applications such as digital radios and radars. The common approaches utilize read-only memory (ROM) for creating amplitude values, and a lot of research focus has been put into reducing the required ROM size. In this brief, we are presenting a memory optimized Direct Digital Frequency Synthesizer (DDFS) architecture that applies the <inline-formula> <tex-math>$3{^{text {rd}}}$ </tex-math></inline-formula> order Taylor series approximation for amplitude computation. To evaluate the architecture performance, also traditional ROM-based architecture is introduced. Both approaches are implemented using VHDL code on a field programmable gate array (FPGA). The FPGA resource utilization, memory consumption, and signal quality are analyzed and compared with other recently published DDFS approaches. Based on the simulation and implementation results, the proposed new architecture consumes only 270 bits of memory and has the output signal spurious free dynamic range (SFDR) of –103.6 dBc.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"958-962"},"PeriodicalIF":4.0,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11022740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Reconfigurable Wireless Charging System Achieving Constant Current and Constant Voltage Conversion by a Single Secondary-Side Switch 一种利用单次侧开关实现恒流恒压转换的新型可重构无线充电系统

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-03 DOI: 10.1109/TCSII.2025.3576132

Tao Li;Yijie Wang;Yang Li;Jianwei Mai;Zhichao Sun;Jian Cui;Ao Yang;Dianguo Xu

引用次数: 0