IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第7页

IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information 电气和电子工程师学会电路与系统论文集--II：特快摘要》出版信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3477191

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Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium 2024 年国际科学与应用科学会议特邀编辑特刊：中国科学院期刊专题讨论会

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-29 DOI: 10.1109/TCSII.2024.3467908

Antonio Liscidini

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Reachable Set Estimation of Inertial Complex-Valued Memristive Neural Networks 惯性复值记忆神经网络的可达集估计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-28 DOI: 10.1109/TCSII.2024.3486746

Jiemei Zhao;Yi Shen;Leimin Wang;Liqi Yu

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An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN 使用高精度转换算法的高效大脑启发加速器用于峰值可变形CNN

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-28 DOI: 10.1109/TCSII.2024.3487266

Haonan Zhang;Siyu Zhang;Wendong Mao;Zhongfeng Wang

{"title":"An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN","authors":"Haonan Zhang;Siyu Zhang;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TCSII.2024.3487266","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3487266","url":null,"abstract":"Spiking Neural Network (SNN), inspired by the brain, has shown promising potential in terms of low-power deployment on resource-constrained devices. The SNN can be obtained by two approaches: training from scratch or conversion from existing Artificial Neural Network (ANN). However, the directly training SNN often leads to suboptimal accuracy. Therefore, methods based on converting existing ANN have become the preferred choice for achieving high accuracy. To enhance the feature-capturing capability of the converted SNNs, various operations, such as transposed convolution and deformable convolution, have been introduced, which bring multiple challenges to conversion algorithms and hardware designs. In this brief, we propose a universal SNN conversion method for deformable convolution to enhance the modeling capability of receptive fields for spatial information. The proposed conversion algorithm not only maintains high accuracy but also makes converted deformable convolutions highly hardware-efficient. Building upon the deformable SNN, we develop a low-complexity processing element and computing array, enabling flexible execution of complex and heterogeneous operations within deformable SNNs without requiring any multipliers. In addition, the overall architecture with energy-efficient dataflow is designed for our deformable SNN model and is implemented in TSMC 28-nm HPC+ technology node. Experiments show that the proposed conversion algorithm suffers negligible accuracy degradation in the challenging object detection task. The accelerator achieves at least \u0000<inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula>\u0000 higher energy efficiency compared to previous designs while maintaining 47.9% mAP.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"288-292"},"PeriodicalIF":4.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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An X-Band 7-Bit High Resolution and Ultra-Low Amplitude Variations Phase Shifter With Current Correction Technique 采用电流校正技术的x波段7位高分辨率超低幅度变化移相器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-25 DOI: 10.1109/TCSII.2024.3486569

Dongwei Pang;Jun Wang;Zongming Duan

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A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7% 一个12v输入0.3 V至0.6 V输出不平衡电感电流变换器，达到90.7%的峰值效率

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-25 DOI: 10.1109/TCSII.2024.3486362

Chan-Ho Lee;Jeong-Hun Kim;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong

{"title":"A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7%","authors":"Chan-Ho Lee;Jeong-Hun Kim;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/TCSII.2024.3486362","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3486362","url":null,"abstract":"This brief proposed an imbalanced inductor-current buck (IIB) converter. The proposed IIB converter has two inductor current paths. The IIB converter provides majority of the load current through a current path composed of low voltage transistors and minority of the load current through the current path composed of high voltage transistors, which becomes further as voltage conversion ratio decreases. Therefore, the IIB converter reduces conduction loss as the voltage conversion ratio decreases, which is considerably important in low voltage applications. In addition, since this converter uses a flying capacitor network behind the inductor, it is invulnerable to the input voltage variation. The proposed converter has peak efficiencies of 90.7% at \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { IN}} {=} 12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { O}} {=} 0.6$ </tex-math></inline-formula>\u0000 V, and 85.6% at \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { IN}} {=} 12$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { O}} {=} 0.3$ </tex-math></inline-formula>\u0000 V. The chip was fabricated in 130-nm BCD process with an area of 6.177 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"338-342"},"PeriodicalIF":4.0,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors 采用嵌套缠绕尾电感的面积高效CMOS交叉耦合LC-VCO

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-24 DOI: 10.1109/TCSII.2024.3485921

Hyogyoung An;Hyeonjun Nam;Sungjin Kim;Younghyun Lim;Heein Yoon

{"title":"An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors","authors":"Hyogyoung An;Hyeonjun Nam;Sungjin Kim;Younghyun Lim;Heein Yoon","doi":"10.1109/TCSII.2024.3485921","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485921","url":null,"abstract":"An area-efficient CMOS cross-coupled LC-VCO, operating from 5.74 GHz to 8.02 GHz and featuring a tail noise filter with two tail inductors integrated inside the main inductor, is presented for the first time. The tail noise filter comprised two nested intertwined tail inductors (NITIs) and a tail capacitor bank, effectively suppressing phase noise (PN) while generating negligible magnetic couplings between the main inductor and the NITIs. The proposed architecture enables area-efficient CMOS cross-coupled design, even with the two NITIs, but has no performance degradation, i.e., it eliminates the additional area for the tail noise filter. Implemented in 28-nm CMOS process, it consumed 11 mA current from 0.73 V power supply. The LC-VCO achieved PN of −116.38 dBc/Hz at 1 MHz offset frequency for an output frequency of 5.747 GHz. 37% and 27% reductions in silicon area were achieved, over the conventional LC-VCO and an LC-VCO using intertwined tail inductors (ITIs), respectively, without compromising on performance. The proposed design has the smallest area among state-of-the-art LC-VCOs that include a tail noise filter along with competitive PN and frequency tuning range (FTR).","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"143-147"},"PeriodicalIF":4.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Parasitic-Aware Analysis and Design of a Wideband gm-Boost Low Noise Amplifier at K-Band k波段宽带gm-Boost低噪声放大器的寄生感知分析与设计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-24 DOI: 10.1109/TCSII.2024.3485649

Hongjie Zeng;Zemeng Huang;Tao Tan;Yubing Li;Xiuping Li

{"title":"Parasitic-Aware Analysis and Design of a Wideband gm-Boost Low Noise Amplifier at K-Band","authors":"Hongjie Zeng;Zemeng Huang;Tao Tan;Yubing Li;Xiuping Li","doi":"10.1109/TCSII.2024.3485649","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485649","url":null,"abstract":"This brief presents a wideband low noise amplifier (LNA) at K-band. A parasitic-aware analysis focused on gain is proposed in the transformer feedback \u0000<inline-formula> <tex-math>$g_{mathrm {m}}$ </tex-math></inline-formula>\u0000-boost common-gate (CG) stage. This analysis models parasitic components as grounded equivalents, decoupling the amplifier into active circuitry and passive components. It addresses the design challenges of wideband amplifiers with complex capacitive networks, offering a more accurate representation of the amplifier’s characteristics and providing valuable guidance for parasitic-sensitive designs. The designed amplifier consists of a gm-boost transformer feedback CG stage followed by a capacitor-neutralized common source (CS) stage. An adapted interstage matching network is developed to compensate for the unbalanced transimpedance, which contributes to a flat overall wideband gain with a low noise figure (NF). The input and output of the LNA are well-matched and the LNA achieves a maximum gain of 14.6 dB, 3-dB bandwidth of 9.5 GHz (19-28.5 GHz), a minimum NF of 2.3 dB, and an input 1-dB compression point (IP1dB) exceeding -10.3 dBm across 19-28.5 GHz. The proposed LNA is implemented in a 110-nm CMOS process, occupying a compact chip area of 0.258 mm2 and consuming 25.6 mW at a supply voltage of 1.2 V. To the best of our knowledge, this brief represents the first comprehensive, parasitic-aware gain analysis of the transformer feedback \u0000<inline-formula> <tex-math>$g_{mathrm {m}}$ </tex-math></inline-formula>\u0000-boost CG stage.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"138-142"},"PeriodicalIF":4.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration 前置开环增益校准的59.6fsrms抖动子采样锁相环

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485011

Yu-Chi Yen;Shen-Iuan Liu

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Source Number Estimation in 2D Uniform Circular and L-Shaped Arrays With Unknown Nonuniform Noise 含未知非均匀噪声的二维均匀圆形和l形阵列的源数估计

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-10-23 DOI: 10.1109/TCSII.2024.3485468

Mengxia He;S. C. Chan

{"title":"Source Number Estimation in 2D Uniform Circular and L-Shaped Arrays With Unknown Nonuniform Noise","authors":"Mengxia He;S. C. Chan","doi":"10.1109/TCSII.2024.3485468","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3485468","url":null,"abstract":"Classical source number estimators are usually derived under the assumption of uniform white noise, which may degrade substantially with unknown nonuniform sensor noise. Advanced estimators designed for nonuniform noise are however computationally expensive with limited performance in unfavorable conditions, such as low signal-to-noise ratio, small number of snapshots, close angular separations and sources with different transmitter powers. This brief proposes a new likelihood ratio statistics-based method for source number estimation under uncorrelated nonuniform noise. Using the asymptotic theory, it is shown that the likelihood ratio follows a chi-square distribution. Hence, the number of sources can be estimated via a sequence of hypothesis tests using maximum likelihood estimators (MLEs) of the covariance matrix with different assumed source numbers. The low complexity subspace algorithm is proposed to obtain the ML estimates. Theoretical analysis demonstrates that the proposed estimator is consistent in the general asymptotic regime. Simulation results on 2D arrays such as uniform circular and L-shaped arrays show that the proposed estimator achieves a higher correct detection probability in unfavorable conditions and is more robust against nonuniformity of noise than state-of-the-art estimators.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"348-352"},"PeriodicalIF":4.0,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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