IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

{"title":"Fixed-Time Synchronization of Second-Order Kuramoto Oscillators With Energy Disparity Bound","authors":"Hao Ding;Bohui Jia;Jingxuan He;Jiasi Li;Xuefeng Piao;Zhenzhou Ji","doi":"10.1109/TCSII.2026.3690117","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3690117","url":null,"abstract":"This brief addresses phase locking and frequency synchronization in undirected networks of second-order Kuramoto oscillators with bounded intrinsic-frequency heterogeneity. Existing fixed-time designs for oscillator networks often rely on nonsmooth feedback and rarely quantify how regulation effort is distributed across nodes. We propose a smooth fully distributed controller that reinforces coupling and applies a two-regime fixed-time injection with hyperbolic-tangent smoothing, enabling practical fixed-time convergence without discontinuous switching. A sharp pseudoinverse-based tuning condition is derived to guarantee entry into and invariance of a phase-cohesive region, which yields uniform sector bounds for the sinusoidal coupling along the closed-loop trajectory. Within this cohesive regime, we establish a uniform practical fixed-time settling-time bound independent of initial conditions and characterize the tunable residual accuracy induced by smoothing and heterogeneity. We further derive an explicit tunable upper bound on the disparity of accumulated control energy across nodes, linking fast synchronization to balanced actuation burden. Numerical examples demonstrate multi-trajectory synchronization, cohesiveness preservation, and the resulting energy-disparity behavior.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"658-662"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Ultra-Compact Doherty Power Amplifier Based on Reciprocal Three-Coil-Coupled-Network","authors":"Lei Zhang;Jianhua Zhu;Qian Zhang;Xiaoxian Liu;Zhangming Zhu","doi":"10.1109/TCSII.2026.3691243","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3691243","url":null,"abstract":"This brief presents an ultra-compact Doherty PA based on the three-coil-coupling-network (TCCN). The TCCN supports load modulation while satisfying impedance matching, and imposes minimal constraints on the output parasitic capacitance of the transistors. Moreover, a detailed parametric analysis is conducted, clarifying the relationship between the traditional 90° equivalent lumped matching network and the specific parameters of the TCCN. A Ka-band Doherty PA prototype is fabricated in 65nm CMOS process to validate the effectiveness of this method, with a total core area of 0.074 mm². At 27GHz, the proposed DPA achieves a peak power output of 21.9 dBm, a peak power-added efficiency of 27.8%, a power-added efficiency at 6dB power back-off of 18.76%, with a maximum power density of 2.09 W/mm².","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"638-642"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver With Ping-Pong Self-Referencing Technique","authors":"Seongcheol Kim;Changmin Sim;Seungwoo Park;Junseob So;Hwaseok Shin;Taewhan Kim;Seon-Been Lee;Chulwoo Kim","doi":"10.1109/TCSII.2026.3663182","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3663182","url":null,"abstract":"This brief presents a 20-Gb/s/pin single-ended receiver (RX) utilizing a proposed ping-pong self-referencing (PPSR) technique. The prior self-referenced (SR) RXs suffer from a fundamental challenge in handling consecutive identical digits (CIDs), since their correction mechanism relies on detecting an unstable blind zone and requires complex digital overhead. The PPSR overcomes this by implementing two primary solutions. First, an analog CID-restoring feedback loop is integrated to actively secure a stable vertical margin even under long-term CID sequences. Second, the PPSR exploits the non-ideal low-pass filter (LPF) characteristic of the sample-and-hold (S&H) circuits. By intentionally adjusting the time constant (<inline-formula> <tex-math>$tau _{mathrm {SH}}$ </tex-math></inline-formula>), a robust horizontal margin is achieved. Fabricated in 28 nm CMOS, the RX achieves a data rate of 20 Gb/s/pin while compensating–15 dB channel loss. The RX consumes 8.42 mW (0.42 pJ/bit) and demonstrates strong immunity to 100 MHz supply noise up to 200 mVpp.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"438-442"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a Tank-Optimized 20 GHz VCO With Fourth Harmonic Extraction Achieving 193.8 dBc/Hz Peak FoM in 22 nm FDSOI","authors":"S. Koop-Brinkmann;V. Lasserre;A. Dossanov;F. Padovan;A. Mazzanti;V. Issakov","doi":"10.1109/TCSII.2026.3669299","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3669299","url":null,"abstract":"In this brief, we present design considerations on achieving highest figure of merit (FoM) for a class-B LC VCO in CMOS. Following aspects are addressed: a) systematic analysis of choosing the optimal fundamental oscillation frequency <inline-formula> <tex-math>$f_{text {O}}$ </tex-math></inline-formula> for achieving simultaneously low phase noise (PN) and high power efficiency, i.e., highest FoM. We show that the optimal <inline-formula> <tex-math>$f_{text {O}}$ </tex-math></inline-formula> is directly related to the frequency tuning range (FTR). E.g., in the given technology, an FTR of 3% results in an optimal operating range of 10 GHz to 20 GHz. A wider FTR narrows down the operation range for optimal PN and FOM; and b) we present an LC-tank step-by-step dimensioning procedure. The proposed approach is based on iterative electromagnetic (EM)-simulations of the resonant circuit components and optimization with respect to technology-independent design degrees of freedom. The terms <inline-formula> <tex-math>$mathbf {10{,}mathrm {mathbf {log_{10}}}(L/(CR_{mathrm {T}}))}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$mathbf {20{,}mathrm {mathbf {log_{10}}}(R_{mathrm {T}}sqrt {C/L})}$ </tex-math></inline-formula> derived from analytical expressions for PN and FoM are optimized over frequency for various <inline-formula> <tex-math>$mathbf {{C_{max }}/{C_{min }}}$ </tex-math></inline-formula> ratios. We use these considerations to design a multi-harmonic class-B LC-VCO in 22 nm FDSOI CMOS, which offers two outputs - one at the fundamental (H1) and another at the fourth harmonic (H4), extracted directly from the core. The VCO achieves a highly competitive FoM at 1 MHz offset with 0.4 V supply of 193.8 dBc/Hz and 188.2 dBc/Hz at 20 GHz and 80 GHz, respectively. We demonstrate that class-B VCO can achieve PN and FoM outperforming class-C or class-F. It is achieved only by means of the proposed systematic LC-tank design, without any additional circuitry, such as waveform shaping, core coupling etc. Thus, core area is only <inline-formula> <tex-math>$mathbf {0.05{,}mathrm {mathbf {mm^{2}}}}$ </tex-math></inline-formula>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"418-422"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11417974","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"VOS-NN: An Efficient Bitonic-Based Voxel-Enhanced Octree Nearest Neighbor Search Accelerator for Large-Scale Point Cloud","authors":"Hao Sun;Yaotang Wu;Yongming Tang;Yajun Ha","doi":"10.1109/TCSII.2026.3662664","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3662664","url":null,"abstract":"K-Nearest Neighbor (KNN) search is essential for large-scale point cloud perception in autonomous driving and robotics. However, existing accelerators are hindered by inefficient data structures, high memory consumption, and limited scalability, leading to significant performance bottlenecks in real-time applications. To address these challenges, we present VOS-NN, a scalable and high-performance FPGA-based KNN search framework that integrates a novel Voxel-enhanced Octree Structure (VOS) with a dataflow-driven accelerator architecture. First, the proposed VOS combines adaptive voxel partitioning and octree subdivision with a hybrid memory layout, enabling efficient, fine-grained organization of large-scale point clouds and improved memory locality for rapid neighbor search. Second, we develop a pipelined VOS-NN accelerator that incorporates spatial locality-aware candidate reuse and a parallel bitonic sorting network tailored to the VOS structure, achieving low-latency, high-throughput top-K selection. Experimental results on ZCU104 and XCU50 FPGAs with the KITTI dataset demonstrate that VOS-NN delivers up to 25<inline-formula> <tex-math>$times $ </tex-math></inline-formula> speedup over CPU implementations and <inline-formula> <tex-math>$9.06times $ </tex-math></inline-formula> acceleration over state-of-the-art KNN accelerators, while maintaining real-time performance for reference sets exceeding three million points. The code is available at: <uri>https://github.com/WuYaOTG/VOSNN</uri>","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"458-462"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2026.3674375","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3674375","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"C2-C2"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11457183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 12-bit 10 GS/s Pre-Sampling Pipelined ADC With Split-Capacitor-Based Parasitic Compensation Technique","authors":"Yu Liu;Mingliang Chen;Yupeng Shen;Yao Yang;Xubin Chen;Jiarui Liu;Zhiyu Wang;Faxin Yu","doi":"10.1109/TCSII.2026.3666826","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3666826","url":null,"abstract":"Pre-sampling multiplying digital-to-analog converters (MDACs) feature high speed and energy efficiency. However, the parasitic capacitance between the sampling capacitor and the reference capacitor in the pre-sampling MDAC can induce gain and intercept errors in the pipeline stage, which significantly degrades the linearity of the entire pipelined ADC. This work presents a pre-sampling MDAC with parasitic compensation using a split-capacitor technique in the analog domain, combined with an intercept calibration method to correct the gain and intercept errors. Employing this technique, a 12-bit pre-sampling pipelined ADC fabricated in a 28nm CMOS process consumes 495mW at a 10GS/s sampling rate, achieving a signal-to-noise-and-distortion ratio (SNDR) of 50.8dB and a spurious-free dynamic range (SFDR) of 60.7dB with a Nyquist input signal.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"388-392"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact 2–19.5-GHz 150-ps True Time Delay Circuit With High Area Efficiency of 882.4-ps/mm2","authors":"Yanting Chen;Xiangyu Meng;Weijia Qiu;Chaojie Zeng;Junbin Ouyang;Yuwen Tao;Baoyong Chi","doi":"10.1109/TCSII.2026.3669200","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3669200","url":null,"abstract":"In this brief, a novel switched true-time-delay (TTD) circuit is presented using a 65-nm CMOS process. It employs cascaded series-capacitor all-pass networks (SCAPNs) for delay compensation, along with a novel layout based on an 8-shaped transformer, to construct a compact and broadband delay unit. The design leverages the self-canceling coupling property of an 8-shaped transformer to integrate the inductors required for both APN stages into a single component, achieving an ultra-compact footprint. To verify the proposed structure, a 5-bit switched-line TTD is constructed using two single-pole double-throw (SPDT) and four double-pole double-throw (DPDT) switches. Experimental results show that, with a core size of only <inline-formula> <tex-math>$0.209times 0.816$ </tex-math></inline-formula> mm², the proposed TTD circuit achieves a maximum delay tuning range of 150 ps and a minimum delay step of 4.838 ps from 2 to 19.5 GHz, while maintaining RMS delay error below 3.7 ps. The corresponding area efficiency of 882.4 ps/mm² represents a record high for switched-line TTDs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"413-417"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Dynamic Range Charge-Sensitive Amplifier","authors":"Filippo Mele;Jacopo Quercia;Giuseppe Bertuccio","doi":"10.1109/TCSII.2026.3666278","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3666278","url":null,"abstract":"Charge sensitive amplifiers (CSA) are key elements for the readout of charge signals produced by ionizing radiation and particle detectors. In nuclear microelectronics, these circuits are characterized by stringent requirements in terms of equivalent noise charge (<inline-formula> <tex-math>$ENC$ </tex-math></inline-formula>), and maximum input charge specification, which is tied to the voltage output swing capability of the amplifier itself. The need for periodic or continuous discharge of the feedback capacitance further constrains the design choices. In this work, a circuital solution that acts on the feedback discharge path to optimize the quiescent operating point of the CSA is presented, allowing an increase in the effective dynamic range of the CSA without affecting the spectroscopic resolution of the system. In addition, the proposed reset architecture allows to use a single power supply, avoiding the double supply generally used to increase the dynamic range, gaining in system compactness. Experimental measurements show an increase of + 107% in the dynamic range with respect to standard reset architectures of state-of-the-art CSAs for low-capacitance (<inline-formula> <tex-math>$le 0.1$ </tex-math></inline-formula> pF) semiconductor radiation detectors, achieving a total maximum input charge of <inline-formula> <tex-math>$simeq 3times 10 ^{5}$ </tex-math></inline-formula> el. (47 fC), corresponding to 1.08 MeV equivalent energy in silicon or 1.31 MeV in cadmium-zinc-telluride detectors. The preamplifier implements a fast feedback capacitance discharge rate of 2.5 fC/ns (t <inline-formula> <tex-math>${}^{90-10}_{fall} =18.8$ </tex-math></inline-formula> ns over the full output range), and preserves an excellent intrinsic noise performance of 3.7 electrons rms, making it suitable for high-speed, high-energy-resolution spectroscopy applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"383-387"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11400590","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 56-Gb/s 10.46- $text{pA}{/}$ ${!}sqrt{text{Hz}}$ Input Noise Linear TIA With 31-dB Dynamic Range in 22-nm CMOS","authors":"Yizhou Zhao;Xinyu Zhao;Yuan Shen;Chengxiang Zheng;En Zhu;Yingmei Chen","doi":"10.1109/TCSII.2026.3669591","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3669591","url":null,"abstract":"This brief proposes a novel optical receiver featuring wide bandwidth and low noise, with a flat frequency response across a large dynamic range without bandwidth peaking. A wide dynamic range transimpedance input stage (WDR-TIS) is proposed as the input-stage amplifier of proposed transimpedance amplifier (TIA). This structure maintains a relatively constant bandwidth during high transimpedance gain dynamic range while delivering adequate noise performance. A three-stage variable gain amplifier (VGA) provides a dynamic range up to 22 dB with excellent linearity, and can accommodate an input current up to <inline-formula> <tex-math>$2.8~{text {mA}}_{text {pp}}$ </tex-math></inline-formula>. Measurement results show that the proposed optical receiver provides an electrical transimpedance gain (<inline-formula> <tex-math>$boldsymbol {Z}_{text {T}}$ </tex-math></inline-formula>) of 40.9 to 72.6 dB<inline-formula> <tex-math>$boldsymbol {Omega }$ </tex-math></inline-formula> with bandwidth beyond 18.8 GHz and input-referred noise density (IRND) current of <inline-formula> <tex-math>$10.46~{text {pA}{/}{!}sqrt {text {Hz}}}$ </tex-math></inline-formula>. The total harmonic distortion (THD) is less than 4% for the output amplitude up to <inline-formula> <tex-math>$450~{{text {mV}}_{text {ppd}}}$ </tex-math></inline-formula>. The core of proposed optical receiver achieves a power dissipation of 85 mA from 1.5 V supply and occupies an area of <inline-formula> <tex-math>$0.53times 0.36$ </tex-math></inline-formula> mm² in 22 nm standard CMOS process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 4","pages":"448-452"},"PeriodicalIF":4.6,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}