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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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A 36 mJ/Inf Convolution Accelerator With Reduced Memory Access and Regrouped Sparse Kernels for Environment Sound Classification on Edge Devices 基于减少内存访问和稀疏核重组的36mj /Inf卷积加速器在边缘设备上的环境声音分类
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-03 DOI: 10.1109/TCSII.2025.3585516
Lichen Feng;Tao Wang;Rundong Cai;Feng Min;Zhangming Zhu
{"title":"A 36 mJ/Inf Convolution Accelerator With Reduced Memory Access and Regrouped Sparse Kernels for Environment Sound Classification on Edge Devices","authors":"Lichen Feng;Tao Wang;Rundong Cai;Feng Min;Zhangming Zhu","doi":"10.1109/TCSII.2025.3585516","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585516","url":null,"abstract":"Efficient environment sound classification (ESC) on edge devices is valuable for applications requiring continuous, long-term monitoring. Existing ESC processors have demonstrated great reductions in latency and resource occupation. However, model sparsity and computation flow still require further optimization. In this brief, we propose an end-to-end ultra-lightweight Depthwise Separable Convolution (DSC) neural network, E2E-ULDSC-Pruned, which is made publicly available as an open-source release. To implement this model, a customized accelerator featuring pipelined DSC computation and regrouped sparse kernels is developed, achieving 36mJ/Inference in ZCU102 FPGA (254ms latency and 143mW power consumption), which is superior to recent works.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1258-1262"},"PeriodicalIF":4.9,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Switchable Sub-3GHz/Sub-6GHz LNA With 0.4-1.1dB NF Using Triple-Feedback and Tunable Inter-Stage Matching Strategies 基于三反馈和可调级间匹配策略的0.4-1.1dB可切换Sub-3GHz/Sub-6GHz LNA
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3585444
Zhihao Zhang;Xiaolin Zhou;Jiehai Zhou;Zhixia Du;Gary Zhang
{"title":"A Switchable Sub-3GHz/Sub-6GHz LNA With 0.4-1.1dB NF Using Triple-Feedback and Tunable Inter-Stage Matching Strategies","authors":"Zhihao Zhang;Xiaolin Zhou;Jiehai Zhou;Zhixia Du;Gary Zhang","doi":"10.1109/TCSII.2025.3585444","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585444","url":null,"abstract":"A broadband switchable low noise amplifier (LNA), supporting Sub-3GHz and Sub-6GHz modes for a wide range of wireless communication applications, is proposed. To achieve broadband simultaneous noise and impedance matching, a triple-feedback technique combined with a strategically designed inter-stage matching network (ISMN), is analyzed and developed. The dual-mode switchable functionality, offering wideband flat gain performance, is enabled through a switch-based tunable capacitor configuration within the ISMN with adjustable load impedance. Additionally, a current-reuse amplification topology is employed to enhance both gain and linearity while reducing power consumption. Fabricated using 250nm GaAs pHEMT technology, the proposed switchable LNA achieves gain of 21.7-24.2/18.7-21.7dB, noise figure (NF) of 0.4-0.96/0.65-1.1dB, output 1-dB compression point of 15.7-19.7/14.2-19.4dBm, and output third-order intercept point of 25.6-35.1/25.4-34dBm in Mode 1 (0.6-3.5GHz) and Mode 2 (0.6-5.5GHz), respectively. In comparison to Mode 1, the LNA operating in Mode 2 extends the 3-dB gain bandwidth by an additional 2GHz, at the cost of a 3 dB reduction in average gain, an increase of 0.15–0.25dB in NF, and a slight degradation in linearity.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1128-1132"},"PeriodicalIF":4.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area-Efficient Modular Multiplication on FPGA 基于FPGA的面积高效模块化乘法
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3585441
Yujun Xie;Yuan Liu
{"title":"Area-Efficient Modular Multiplication on FPGA","authors":"Yujun Xie;Yuan Liu","doi":"10.1109/TCSII.2025.3585441","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585441","url":null,"abstract":"Modular multiplication (MM) involves multiplication and modular reduction. In this brief, we explore an area-efficient modular reduction for MM on FPGA. We analyze and compare the equivalent LUT6 (ELUT6) cost when implementing modular reduction using different memory strategies (BRAM/LUT6/LUT5), and adopt LUT5 (lowest ELUT6 cost) as the memory for this design. Then we propose an area-efficient compression strategy with a new (1,5;3) Generalized Parallel Counter (GPC), which reduces the LUT6 cost of compression operation in modular reduction compared to previous methods. Finally, we adopt the 4-term Karatsuba algorithm to reduce the area of multiplication, and explore the balance of hardware delay in MM. The proposed MM is implemented on the Xilinx Virtex-7 platform. Compared to the previous state-of-art pipeline design, the area of proposed MM is only 41.7%/47.6%/47.6%/50.0% of them when word-size <inline-formula> <tex-math>$w {=}32$ </tex-math></inline-formula>/64/128/256.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1253-1257"},"PeriodicalIF":4.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of a Hybrid Fractional-Order Fuzzy-PID Controller Applied to a DC-DC Buck Converter 应用于DC-DC降压变换器的分数阶模糊pid混合控制器的研制
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3585464
Michel W. de S. Campos;Edmilson M. Prado;Renan L. P. De Medeiros;Maurício P. Fantesia;Werbeston D. De Oliveira;Venicio C. Conceição;Iago V. Correa;Ozenir F. da R. Dias;Florindo A. de C. Ayres Júnior
{"title":"Development of a Hybrid Fractional-Order Fuzzy-PID Controller Applied to a DC-DC Buck Converter","authors":"Michel W. de S. Campos;Edmilson M. Prado;Renan L. P. De Medeiros;Maurício P. Fantesia;Werbeston D. De Oliveira;Venicio C. Conceição;Iago V. Correa;Ozenir F. da R. Dias;Florindo A. de C. Ayres Júnior","doi":"10.1109/TCSII.2025.3585464","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585464","url":null,"abstract":"This brief focuses on developing a hybrid fractional-order PID (FOPID) controller enhanced with fuzzy logic to regulate the output voltage of a DC-DC Buck converter. The FOPID controller extends traditional PID control by offering improved robustness and more flexible tuning criteria. The controller’s gains are dynamically adjusted using fuzzy logic, enhancing performance across varying operating conditions. The project involved mathematical modeling of the Buck converter and approximating fractional-order operators to integer-order equivalents. Frequency domain analysis was performed using computational tools, including MATLAB, Simulink, and LTspice, to design and simulate the control system. A physical Buck converter was assembled to validate the controller’s experimental performance. The system’s non-linearities were characterized to optimize the hybrid controller, and the best tuning parameters were identified for three distinct operating regions. The experimental results were compared with simulation data, demonstrating the hybrid controller’s enhanced performance in closed-loop operation. The study concludes that the proposed approach outperforms conventional tuning methods, showcasing its potential for advanced industrial control systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1218-1222"},"PeriodicalIF":4.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Benders-Combined Safe Reinforcement Learning Framework for Risk-Averse Dispatch Considering Frequency Security Constraints 考虑频率安全约束的风险规避调度的benders组合安全强化学习框架
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3584894
Jianbing Feng;Zhouyang Ren;Chen Li;Wenyuan Li
{"title":"A Benders-Combined Safe Reinforcement Learning Framework for Risk-Averse Dispatch Considering Frequency Security Constraints","authors":"Jianbing Feng;Zhouyang Ren;Chen Li;Wenyuan Li","doi":"10.1109/TCSII.2025.3584894","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3584894","url":null,"abstract":"Risk-averse dispatch considering frequency security constraints (FSC-RD) mitigates power supply-demand imbalance risks and frequency instability hazards. To effectively address the highly complex, multi-task coupled FSC-RD, this brief proposes a Benders-combined constrained Markov decision process (BC-CMDP) framework, which integrates logic-based Benders decomposition and safe reinforcement learning. A natural policy gradient primal-dual optimization is developed to handle the nonconvex policy optimization within the BC-CMDP. The global non-asymptotic convergence of the BC-CMDP framework is rigorously proven. The proposed framework is validated on the IEEE 118-bus system.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1063-1067"},"PeriodicalIF":4.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-01 DOI: 10.1109/TCSII.2025.3580983
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3580983","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580983","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11061371","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Circuits and Systems Society Information IEEE电路与系统学会信息
IF 4 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-01 DOI: 10.1109/TCSII.2025.3580985
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3580985","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580985","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 7","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11061369","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144536194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel and Pipelined BRAM-Based Matrix Transposition for 6G 基于并行和流水线bram的6G矩阵转置
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-30 DOI: 10.1109/TCSII.2025.3584052
Jierui Chen;Chuang Yang;Xu Zhou;Mugen Peng
{"title":"Parallel and Pipelined BRAM-Based Matrix Transposition for 6G","authors":"Jierui Chen;Chuang Yang;Xu Zhou;Mugen Peng","doi":"10.1109/TCSII.2025.3584052","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3584052","url":null,"abstract":"In this brief, we present a parallel and pipelined algorithm for BRAM-based matrix transposition, along with its corresponding architecture, optimized specifically to meet the stringent throughput and latency demands of 6G. The architecture utilizes a novel address mapping algorithm, which exploits the coprimality between memory parameters to achieve conflict-free parallel access via a simple yet efficient prime-modulo addressing scheme.The architecture achieves conflict-free parallel memory access on BRAM, significantly improving parallelism and enhancing throughput. More importantly, by adopting a ping-pong buffering scheme, it enables fully pipelined and highly parallel matrix transposition, primarily targeting low-latency and high-throughput tasks in 6G. Experimental results show that, compared with existing implementations supporting similar matrix sizes, the architecture in this brief increases throughput significantly from 0.8 GB/s to 25.6 GB/s under a latency of 0.08ms.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1033-1037"},"PeriodicalIF":4.9,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bumpless Transfer Control for Discrete Semi-Markov Switching Power System With Cyber Attack 网络攻击下离散半马尔可夫开关电源系统的无颠簸传输控制
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-24 DOI: 10.1109/TCSII.2025.3582648
Zhenhao Li;Wenhai Qi;Ju H. Park;Zheng-Guang Wu
{"title":"Bumpless Transfer Control for Discrete Semi-Markov Switching Power System With Cyber Attack","authors":"Zhenhao Li;Wenhai Qi;Ju H. Park;Zheng-Guang Wu","doi":"10.1109/TCSII.2025.3582648","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3582648","url":null,"abstract":"In this brief, the bumpless transfer control is studied for power system under cyber attack with stochastic switching rule. Transient failures of power lines and dynamic switching of circuit breakers are accurately modeled by introducing semi-Markov chain. Due to the randomness of denial-of-service attack, a Markov chain is introduced to characterize the attack behavior. In order to solve the issue of stochastic switching in system operation and the impact caused by cyber attack, a comprehensive bumpless transfer rule is proposed, which is applicable to both the switching instant and the switching interval. By combining semi-Markov kernel and Lyapunov function method, a state feedback controller with no disturbance transfer performance is designed and its effectiveness is verified by numerical example.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1118-1122"},"PeriodicalIF":4.9,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SPECTRUM1k – 75 μm Pixels Pitch IC With In-Pixel Histogramming for X-Ray Color Imaging SPECTRUM1k - 75 μm像素间距IC与像素内直方图用于x射线彩色成像
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-23 DOI: 10.1109/TCSII.2025.3579856
P. Kmon;R. Kleczek;R. Szczygiel;G. Wegrzyn
{"title":"SPECTRUM1k – 75 μm Pixels Pitch IC With In-Pixel Histogramming for X-Ray Color Imaging","authors":"P. Kmon;R. Kleczek;R. Szczygiel;G. Wegrzyn","doi":"10.1109/TCSII.2025.3579856","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3579856","url":null,"abstract":"A new single photon-counting IC prototype called SPECTRUM1k with pixel matrix <inline-formula> <tex-math>$40times 24$ </tex-math></inline-formula> and pixel pitch <inline-formula> <tex-math>$75~mu $ </tex-math></inline-formula>m is developed by the Microelectronics Group of the AGH University of Krakow as a solution for X-ray color imaging. The chip, produced in CMOS 40nm technology, is made up of 960 individually configured pixels, each composed of an amplifier, an analog-to-digital converter, and <inline-formula> <tex-math>$64times 12$ </tex-math></inline-formula>-bit memory cells that allow one to perform in-pixel energy histogramming. Thanks to the proposed architecture working with the 200 MHz chip clock and 1 Gcps/mm2 multi energy photon intensities up-to about 23 ms exposition time is feasible (<inline-formula> <tex-math>$365~mu $ </tex-math></inline-formula>s exposition time whenever monoenergetic photons are used only). In-pixel offsets (<inline-formula> <tex-math>${=} 3.5$ </tex-math></inline-formula>%) and gain (<inline-formula> <tex-math>${=} 5.8$ </tex-math></inline-formula>%) spread, the amplifier performance (Equivalent Noise Charge <inline-formula> <tex-math>${=} 95$ </tex-math></inline-formula> e-RMS) and the ADC resolution (Effective Number of Bits <inline-formula> <tex-math>${=} 5.4$ </tex-math></inline-formula> b) allow to convert the incoming photons’ energy with FWHM <inline-formula> <tex-math>${=} 3.7$ </tex-math></inline-formula> ke @134.2 keV upon <inline-formula> <tex-math>$81~mu $ </tex-math></inline-formula>W or <inline-formula> <tex-math>$48~mu $ </tex-math></inline-formula>W per pixel power consumption. In this publication, we present a description of the ASIC’s architecture as well as characterization results. The threshold dispersions, gain spread as well as noise and energy measurement performance of the SPECTRUM1k are presented.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1003-1007"},"PeriodicalIF":4.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11046196","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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