IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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A 28-GHz CMOS Power Amplifier With Adaptive Bias and Phase Compensation for Gain and Phase Linearity Enhancement 一种具有自适应偏置和相位补偿的28 ghz CMOS功率放大器,用于增益和相位线性增强
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-19 DOI: 10.1109/TCSII.2025.3581383
Liang-Chen Tsai;Zheng-Jie Li;Liang-Hung Lu
{"title":"A 28-GHz CMOS Power Amplifier With Adaptive Bias and Phase Compensation for Gain and Phase Linearity Enhancement","authors":"Liang-Chen Tsai;Zheng-Jie Li;Liang-Hung Lu","doi":"10.1109/TCSII.2025.3581383","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3581383","url":null,"abstract":"This brief presents a 28-GHz PA fabricated in the TSMC 90-nm CMOS process for 5G wireless communication phased-array transmitters. The proposed PA incorporates adaptive bias and phase compensation techniques to effectively mitigate AM-AM and AM-PM distortions, achieving high linearity and efficiency. The design features an envelope detector for dynamic bias adjustment, enhancing transconductance to reduce AM-AM distortion. Furthermore, a varactor-based phase correction mechanism is implemented to minimize AM-PM distortion. This brief improves both gain and phase control networks, resulting in significant improvements in key performance metrics, including <inline-formula> <tex-math>$OP_{1dB}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$PAE_{P1dB}$ </tex-math></inline-formula>, and maximum phase distortion before <inline-formula> <tex-math>$P_{1dB}$ </tex-math></inline-formula>. The proposed PA achieves an <inline-formula> <tex-math>$OP_{1dB}$ </tex-math></inline-formula> of 14.4 dBm, a <inline-formula> <tex-math>$PAE_{P1dB}$ </tex-math></inline-formula> of 33.6%, and a maximum AM-PM distortion of 1.5°, demonstrating exceptional performance and scalability for phased-array applications in next-generation millimeter-wave systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1028-1032"},"PeriodicalIF":4.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Calibration-Free Edge-Computing IMC Macro With Direct Current-to-Digital Conversion 具有直流数字转换的免校准边缘计算IMC宏
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-19 DOI: 10.1109/TCSII.2025.3581384
Andrea Fasolino;Rosalba Liguori;Luigi Di Benedetto;Alfredo Rubino;Gian Domenico Licciardo
{"title":"Calibration-Free Edge-Computing IMC Macro With Direct Current-to-Digital Conversion","authors":"Andrea Fasolino;Rosalba Liguori;Luigi Di Benedetto;Alfredo Rubino;Gian Domenico Licciardo","doi":"10.1109/TCSII.2025.3581384","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3581384","url":null,"abstract":"In-memory computing (IMC) has emerged as a promising solution to the “memory wall” problem of traditional Von Neumann architectures by integrating computation directly within the memory. This brief presents a novel current-mode IMC macro that leverages a nanoampere-range temperature-independent reference current and direct current-to-digital conversion. The proposed design mitigates power inefficiencies and thermal instability of previous architectures without the need for calibration. Implemented in TSMC LP 65 nm CMOS technology, the design achieves an energy efficiency of 310.7 TOPS/W and an area efficiency of 18.93 TOPS/mm2. The reference current generator ensures a temperature coefficient of just 363 ppm/°C over a temperature <inline-formula> <tex-math>$in $ </tex-math></inline-formula> [-10; 115]° C. Using a VGG-6 model on the CIFAR-10 dataset with 87.93% accuracy, the drop between the software baseline model and IMC hardware (1bA/1bW/5bO) at TT@27°C/FF@115°C/SS@-10°C is 0.17/0.32/0.51%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1018-1022"},"PeriodicalIF":4.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mamba-Unet-Depth: Enhancing Long-Range Dependency for Photon-Efficient Imaging Mamba-Unet-Depth:增强光子高效成像的远程依赖性
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-18 DOI: 10.1109/TCSII.2025.3580670
Yanyun Pu;Chengyuan Zhu;Gongxin Yao;Yu Pan;Kaixiang Yang;Qinmin Yang
{"title":"Mamba-Unet-Depth: Enhancing Long-Range Dependency for Photon-Efficient Imaging","authors":"Yanyun Pu;Chengyuan Zhu;Gongxin Yao;Yu Pan;Kaixiang Yang;Qinmin Yang","doi":"10.1109/TCSII.2025.3580670","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580670","url":null,"abstract":"With the rapid development of single-photon LiDAR, accurate depth recovery remains a key challenge. Conventional deep learning methods, such as CNNs and ViTs, leverage convolution and self-attention to extract local and global features, respectively. However, these models struggle to capture long-range dependencies in depth images, especially under low signal-to-background ratio (SBR) conditions. To address this, we propose Mamba-Unet-Depth, a novel network inspired by the Mamba architecture, which models long sequences and global context efficiently. By combining the hierarchical representation capability of U-Net with Mamba’s sequential modeling strength, the proposed model uses skip connections to retain spatial details across scales, facilitating richer feature learning. This enables more effective extraction of both fine-grained and contextual depth cues in challenging LiDAR data. Experimental results on the NYU Depth v2 dataset show that Mamba-Unet-Depth outperforms existing baselines in depth prediction accuracy and robustness, achieving state-of-the-art performance.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1123-1127"},"PeriodicalIF":4.9,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Discharge Correction Under Asymmetric Electrode-Electrolyte Interfaces in Bipolar Stimulation 双极刺激中不对称电极-电解质界面下的放电校正
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-18 DOI: 10.1109/TCSII.2025.3580714
Jialei Wu;Simeng Yin;Yixin Zhou;Keping Wang
{"title":"Discharge Correction Under Asymmetric Electrode-Electrolyte Interfaces in Bipolar Stimulation","authors":"Jialei Wu;Simeng Yin;Yixin Zhou;Keping Wang","doi":"10.1109/TCSII.2025.3580714","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580714","url":null,"abstract":"Neural electrical stimulators have been widely used in biomedical applications, especially those with multiple channels. However, the electrode-electrolyte interfaces are usually not identical, which is rarely discussed in stimulator design. This brief first analyzes the stimulation and discharge phases in bipolar stimulation when the interfaces are not identical, proving that the asymmetry will lead to incomplete discharge. To address this issue, we propose a tripolar stimulator by introducing a return electrode to discharge the working and counter electrodes separately. The prototype of a 4-channel tripolar stimulator is designed and fabricated in a 180-nm CMOS technology, with each stimulation channel occupying 0.176 mm2. The maximum stimulation current is 2.8 mA. After discharge, residual voltages are near-zero in both electrical and in vitro tests.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1013-1017"},"PeriodicalIF":4.9,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Three-Stage Identification Method of the Sandwich Model With Hysteresis 含滞后夹层模型的三阶段辨识方法
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-17 DOI: 10.1109/TCSII.2025.3580551
Ya Gu;Haiyan Hou;Yonghong Tan
{"title":"The Three-Stage Identification Method of the Sandwich Model With Hysteresis","authors":"Ya Gu;Haiyan Hou;Yonghong Tan","doi":"10.1109/TCSII.2025.3580551","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580551","url":null,"abstract":"This brief investigates the identification of sandwich systems exhibiting hysteresis behavior. To address the problem that the filtering effect of the previous-stage subsystem on the input signal results in the filtered excitation input causing insufficient excitation of the subsequent-stage subsystems, thus reducing the identification accuracy, a new robust three-stage identification method is proposed to ensure the sufficient excitation of the entire system and enhance the identification accuracy. The key to this method lies in the staged estimation of subsystem parameters. In each stage, parameter estimation is carried out using the key-item separation principle combined with an iterative process. Then, based on the previously estimated submodel parameters, an inverse model is developed to filter the input excitation signal. Therefore, the insufficient excitation of the subsequent-stage subsystem caused by the filtering effect of the previous-stage subsystem on the input signal is counteracted, enhancing parameter estimation accuracy. Finally, this method is applied to the parameter identification of an electromagnetic micromirror.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1058-1062"},"PeriodicalIF":4.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM 面向KV-Cache的查询感知稀疏注意力加速器与跨阶段精度可配置的数字CIM
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-17 DOI: 10.1109/TCSII.2025.3580135
Yang Zhang;Xilong Kang;Weixuan Wang;Yizhi Ding;Lizheng Ren;Yiran Zhang;Ruiqi Tan;Zhen Wang;Hao Cai;Bo Liu
{"title":"KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM","authors":"Yang Zhang;Xilong Kang;Weixuan Wang;Yizhi Ding;Lizheng Ren;Yiran Zhang;Ruiqi Tan;Zhen Wang;Hao Cai;Bo Liu","doi":"10.1109/TCSII.2025.3580135","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580135","url":null,"abstract":"This brief proposes KV-CIM, a KV-Cache oriented Digital Compute-In-Memory (DCIM) sparse attention accelerator, to address computational and memory bottlenecks in autoregressive inference for large language models. Key innovations include: a) A query-aware pre-compute architecture, which dynamically selects and accesses KV-Cache for critical tokens at the pre-compute stage (Stage1) and deploys KV-Cache segmentally on memory-constrained edge devices while maintaining computational accuracy at the formal computation stage (Stage2); b) A cross-stage DCIM macro featuring precision-configurable adder trees, which works in approximate mode at Stage1 and changes to full precision mode at Stage2; c) A query-stationary dataflow that retains the current query tensors in q-CIM across stages to eliminate data movement. Under 28-nm CMOS technology, the proposed KV-CIM achieves 35.16 TOPS/W and 82% reduction of external memory access with negligible degradation in LLaMA2 expressiveness.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1073-1077"},"PeriodicalIF":4.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Hardware Architecture Design of K-Means Clustering Algorithm for AV1 Palette Mode Coding AV1调色板模式编码中k -均值聚类算法的高效硬件架构设计
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-17 DOI: 10.1109/TCSII.2025.3580435
Xiaofeng Huang;Jiaqing Lin;Fengguang Liu;Wen Ji;Haibing Yin;Siwei Ma
{"title":"Efficient Hardware Architecture Design of K-Means Clustering Algorithm for AV1 Palette Mode Coding","authors":"Xiaofeng Huang;Jiaqing Lin;Fengguang Liu;Wen Ji;Haibing Yin;Siwei Ma","doi":"10.1109/TCSII.2025.3580435","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580435","url":null,"abstract":"The palette mode is a specialized coding tool for coding screen content video in Alliance for Open Media Video 1 (AV1), and K-means clustering is a necessary step in the palette mode. However, the high computational complexity and the strong data dependency in K-means clustering impede real-time processing. To address these issues, we propose an efficient hardware architecture design for the K-means clustering algorithm. Firstly, we propose a fully pipelined hardware architecture with two data-interleaving optimization methods, including K-interleaving and block-interleaving. Then, we propose a novel method for reusing original pixel data, which is motivated by the fact that the input original pixels are the same for different coding blocks. Finally, we propose a parallelized architecture that features three “K-means Engine” modules, with reusing of the “Euclidean distance calculate” module to minimize area. Experimental results show that the proposed hardware architecture can process all K-means clustering for pixels in a superblock in 10246 cycles under 650MHz working frequency, which can achieve 4K@30fps real-time processing. To the best of our knowledge, our work is the first attempt to design a K-means clustering hardware accelerator for palette mode in AV1.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1078-1082"},"PeriodicalIF":4.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Neural Network-Enhanced Digital Background Calibration Algorithm for Residue Amplifier Nonlinearity in Pipelined ADCs 一种针对流水线adc中剩余放大器非线性的神经网络增强数字背景校正算法
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-16 DOI: 10.1109/TCSII.2025.3580062
Yutao Peng;Ziwei Lai;Hu Wang;Jun Zhang;Dongbing Fu;Yabo Ni;Tao Liu;Zhifei Lu;Xizhu Peng;He Tang
{"title":"A Neural Network-Enhanced Digital Background Calibration Algorithm for Residue Amplifier Nonlinearity in Pipelined ADCs","authors":"Yutao Peng;Ziwei Lai;Hu Wang;Jun Zhang;Dongbing Fu;Yabo Ni;Tao Liu;Zhifei Lu;Xizhu Peng;He Tang","doi":"10.1109/TCSII.2025.3580062","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3580062","url":null,"abstract":"This brief proposes a neural network-enhanced digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. A customized convolutional neural network (CNN) is designed to extract the information of the linear and the third-order nonlinear gain errors of RA with dither injection. Compared to traditional correlation-based calibration algorithms, the proposed method can significantly improve convergence speed and robustness against dither capacitor mismatch. Compared with previous neural network-based calibration techniques which are commonly used for foreground calibration, the proposed method can operate in background to follow error variations without any risk of signal fidelity problems. Off-chip validation with a silicon-proven 14-bit 1.3 GS/s pipelined ADC shows that, after calibration, the SNDR and SFDR are improved from 46.6 dB and 55.2 dB to 63.1 dB and 80.4 dB, respectively. Moreover, the proposed method takes only 75K samples to reach convergence, whereas traditional algorithms require several to hundreds of millions of samples to achieve convergence (<inline-formula> <tex-math>$10{^{{2}}} sim 10{^{{4}}}$ </tex-math></inline-formula> times faster). The implementation result shows that the power consumption of the proposed calibrator is 34.8 mW at 1.3 GHz clock frequency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1008-1012"},"PeriodicalIF":4.9,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144750869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28.4-to-39.2 GHz Low-Power Injection-Locked Frequency Quadrupler With Reconfigurable Pre-Filter-Amplifier 带可重构预滤波器放大器的28.4 ~ 39.2 GHz低功率注入锁频四倍器
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-13 DOI: 10.1109/TCSII.2025.3579551
Kai Li;Zhipeng Wang;Fanyi Meng;Kaixue Ma;Keping Wang
{"title":"A 28.4-to-39.2 GHz Low-Power Injection-Locked Frequency Quadrupler With Reconfigurable Pre-Filter-Amplifier","authors":"Kai Li;Zhipeng Wang;Fanyi Meng;Kaixue Ma;Keping Wang","doi":"10.1109/TCSII.2025.3579551","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3579551","url":null,"abstract":"In this brief, a 28.4 to 39.2 GHz injection-locked frequency quadrupler (ILFQ) is fabricated in a 65nm CMOS process. A reconfigurable pre-filter-amplifier (RPFA) structure is proposed to pre-process the output current of the harmonic generator. By switching between two modes, the RPFA effectively filters out the undesired harmonics and amplifies the desired 4th harmonic. Therefore, both the harmonic rejection and locking range of the ILFQ are improved. In addition, a load tank based on a three-coil coupled transformer and an impedance-boosting transformer is designed to further extend the locking range, increase the output power, and reduce the DC power consumption. The measured results show that the proposed ILFQ achieves a 31.9% locking range (28.4 GHz to 39.2 GHz). Across the whole locking range, the measured 1st/2nd/3rd harmonic rejection ratio (HRR) is better than 42.4/37.4/15 dBc, respectively. Within the range of 28.4 to 36.2 GHz, >29 dBc 1st/2nd/3rd HRR is achieved. The measured maximum DC power consumption is 13.3 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"998-1002"},"PeriodicalIF":4.9,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hybrid Scheduling-Based Asynchronous H∞ Control for Markov Jump Power Systems With Cyber Attacks 网络攻击下马尔可夫跳变电力系统的混合调度异步H∞控制
IF 4.9 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-06-11 DOI: 10.1109/TCSII.2025.3578663
Yi Lu;Xiru Wu;Yaonan Wang;Rili Wu;Yuhai Zhong;Jiexin Xie
{"title":"Hybrid Scheduling-Based Asynchronous H∞ Control for Markov Jump Power Systems With Cyber Attacks","authors":"Yi Lu;Xiru Wu;Yaonan Wang;Rili Wu;Yuhai Zhong;Jiexin Xie","doi":"10.1109/TCSII.2025.3578663","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3578663","url":null,"abstract":"This brief investigates the asynchronous <inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula> control problem of discrete-time hidden Markov jump power systems (hMJPSs) under cyber attacks. To precisely capture the dynamic characteristics of transient faults and circuit breaker switching in power systems, a hidden Markov jump process with unknown information is introduced. A hybrid scheduling protocol via event triggering is proposed to enhance the utilization of communication resources. By dynamically adjusting the data transmission frequency of sensor nodes, the protocol significantly reduces communication resource usage while maintaining <inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula> performance of the system. Additionally, considering the mode mismatched behavior between the power systems and the controllers, the asynchronous state-feedback controller is designed. Through the mode-dependent Lyapunov function, the sufficient conditions for the mean-square stability of hMJPSs are derived. Finally, the effectiveness and practicality of the proposed method are validated via simulation examples.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1048-1052"},"PeriodicalIF":4.9,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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