Digitally Calibrated Redundancy-Based String DAC: A Novel Architecture for Enhanced Static Linearity

Abstract

This brief introduces a three-segment resistor string ladder DAC featuring built-in redundancy and sub-radix transfer characteristics. The architecture implements digital calibration to optimize the linearity-resolution tradeoff, achieving substantial area reduction compared to conventional string DAC designs. Measurement and simulation results are presented validating the architecture’s performance. Mathematical analysis is presented revealing a fundamental 1 LSB lower bound on the best achievable post-calibration differential nonlinearity (DNL) for 1-bit redundancy cases. To address this limitation, we present two alternative architectures that demonstrate improved post-calibration DNL performance.