Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang
{"title":"UniPRE:具有统一最大池预测和冗余消除的SNN-ANN加速器","authors":"Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang","doi":"10.1109/TCSII.2025.3582265","DOIUrl":null,"url":null,"abstract":"The integration of Spiking Neural Networks (SNNs) and Artificial Neural Networks (ANNs) for specific tasks has attracted considerable interest due to their potential for high energy efficiency and accuracy. In SNN-ANN fused hardware, many works focus on neuron-level fusion of operators. Though some have explored optimizations at the dataflow level, they are restricted to only one kind of networks. This brief introduces a dataflow-level unified predicting method to eliminate redundant computations resulted from max-pooling operations for both SNN and ANN by exploiting Channel-wise Importance (CI). An accelerator with online sorting of Channel-wise Importance (CI) to support this optimization is also proposed, named as UniPRE. Results show that UniPRE reduces 44.77% and 31.85% overall computations with negligible accuracy loss for SNN and ANN using 37.5% channels for prediction. Implemented in the standard 28-nm CMOS technology, UniPRE can reach an energy efficiency of 19.32 TSOPS/W and 4.26 TOPS/W, with an area efficiency of 370.10 GSOPS/mm2 and 92.52 GOPS/mm2 for SNN and ANN paradigms of 8-bit weight precision, respectively. In layer-wise evaluation of real networks, up to <inline-formula> <tex-math>$1.79\\times $ </tex-math></inline-formula> energy reduction is achieved with 25% channels used for prediction.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1088-1092"},"PeriodicalIF":4.9000,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination\",\"authors\":\"Tao Zhang;Yi Zhong;Youming Yang;Zilin Wang;Zhaotong Zhang;Yuan Wang\",\"doi\":\"10.1109/TCSII.2025.3582265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The integration of Spiking Neural Networks (SNNs) and Artificial Neural Networks (ANNs) for specific tasks has attracted considerable interest due to their potential for high energy efficiency and accuracy. In SNN-ANN fused hardware, many works focus on neuron-level fusion of operators. Though some have explored optimizations at the dataflow level, they are restricted to only one kind of networks. This brief introduces a dataflow-level unified predicting method to eliminate redundant computations resulted from max-pooling operations for both SNN and ANN by exploiting Channel-wise Importance (CI). An accelerator with online sorting of Channel-wise Importance (CI) to support this optimization is also proposed, named as UniPRE. Results show that UniPRE reduces 44.77% and 31.85% overall computations with negligible accuracy loss for SNN and ANN using 37.5% channels for prediction. Implemented in the standard 28-nm CMOS technology, UniPRE can reach an energy efficiency of 19.32 TSOPS/W and 4.26 TOPS/W, with an area efficiency of 370.10 GSOPS/mm2 and 92.52 GOPS/mm2 for SNN and ANN paradigms of 8-bit weight precision, respectively. In layer-wise evaluation of real networks, up to <inline-formula> <tex-math>$1.79\\\\times $ </tex-math></inline-formula> energy reduction is achieved with 25% channels used for prediction.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 8\",\"pages\":\"1088-1092\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11048618/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11048618/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination
The integration of Spiking Neural Networks (SNNs) and Artificial Neural Networks (ANNs) for specific tasks has attracted considerable interest due to their potential for high energy efficiency and accuracy. In SNN-ANN fused hardware, many works focus on neuron-level fusion of operators. Though some have explored optimizations at the dataflow level, they are restricted to only one kind of networks. This brief introduces a dataflow-level unified predicting method to eliminate redundant computations resulted from max-pooling operations for both SNN and ANN by exploiting Channel-wise Importance (CI). An accelerator with online sorting of Channel-wise Importance (CI) to support this optimization is also proposed, named as UniPRE. Results show that UniPRE reduces 44.77% and 31.85% overall computations with negligible accuracy loss for SNN and ANN using 37.5% channels for prediction. Implemented in the standard 28-nm CMOS technology, UniPRE can reach an energy efficiency of 19.32 TSOPS/W and 4.26 TOPS/W, with an area efficiency of 370.10 GSOPS/mm2 and 92.52 GOPS/mm2 for SNN and ANN paradigms of 8-bit weight precision, respectively. In layer-wise evaluation of real networks, up to $1.79\times $ energy reduction is achieved with 25% channels used for prediction.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.