{"title":"具有高偏置容限的体偏混合感测放大器,用于低压sram","authors":"Minglong Jia;Pengyuan Zhao;Linnan Li;Xiang Li;Zhi Li;Huidong Zhao;Shushan Qiao","doi":"10.1109/TCSII.2025.3582549","DOIUrl":null,"url":null,"abstract":"The offset voltage (VOS) of the Sense Amplifier (SA) is a critical parameter that affects sensing delay and energy consumption in SRAM. This brief proposes a Body-Biased Hybrid Sense Amplifier (BHSA) that effectively reduces the standard deviation (<inline-formula> <tex-math>$\\sigma {_{\\text {OS}}}$ </tex-math></inline-formula>) of VOS in low-voltage SRAM applications without need for the additional capacitors or auxiliary control circuits. Results of post-simulation demonstrate that the BHSA shows an average 44% reduction in <inline-formula> <tex-math>$\\sigma {_{\\text {OS}}}$ </tex-math></inline-formula> compared to the VLSA across the 0.3-0.9 V supply voltage range, with a specific reduction of 49.4% achieved at 0.3 V. Two 16 kb SRAMs with integrated BHSA and VLSA, respectively, were fabricated under the 22 nm FDSOI technology. Measurements indicates that the SRAM with integrated BHSA achieves a 48.2% reduction in bitline discharge delay and a 13.7% decrease in read power consumption at 0.45 V compared to traditional designs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 8","pages":"1098-1102"},"PeriodicalIF":4.9000,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs\",\"authors\":\"Minglong Jia;Pengyuan Zhao;Linnan Li;Xiang Li;Zhi Li;Huidong Zhao;Shushan Qiao\",\"doi\":\"10.1109/TCSII.2025.3582549\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The offset voltage (VOS) of the Sense Amplifier (SA) is a critical parameter that affects sensing delay and energy consumption in SRAM. This brief proposes a Body-Biased Hybrid Sense Amplifier (BHSA) that effectively reduces the standard deviation (<inline-formula> <tex-math>$\\\\sigma {_{\\\\text {OS}}}$ </tex-math></inline-formula>) of VOS in low-voltage SRAM applications without need for the additional capacitors or auxiliary control circuits. Results of post-simulation demonstrate that the BHSA shows an average 44% reduction in <inline-formula> <tex-math>$\\\\sigma {_{\\\\text {OS}}}$ </tex-math></inline-formula> compared to the VLSA across the 0.3-0.9 V supply voltage range, with a specific reduction of 49.4% achieved at 0.3 V. Two 16 kb SRAMs with integrated BHSA and VLSA, respectively, were fabricated under the 22 nm FDSOI technology. Measurements indicates that the SRAM with integrated BHSA achieves a 48.2% reduction in bitline discharge delay and a 13.7% decrease in read power consumption at 0.45 V compared to traditional designs.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 8\",\"pages\":\"1098-1102\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11048660/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11048660/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs
The offset voltage (VOS) of the Sense Amplifier (SA) is a critical parameter that affects sensing delay and energy consumption in SRAM. This brief proposes a Body-Biased Hybrid Sense Amplifier (BHSA) that effectively reduces the standard deviation ($\sigma {_{\text {OS}}}$ ) of VOS in low-voltage SRAM applications without need for the additional capacitors or auxiliary control circuits. Results of post-simulation demonstrate that the BHSA shows an average 44% reduction in $\sigma {_{\text {OS}}}$ compared to the VLSA across the 0.3-0.9 V supply voltage range, with a specific reduction of 49.4% achieved at 0.3 V. Two 16 kb SRAMs with integrated BHSA and VLSA, respectively, were fabricated under the 22 nm FDSOI technology. Measurements indicates that the SRAM with integrated BHSA achieves a 48.2% reduction in bitline discharge delay and a 13.7% decrease in read power consumption at 0.45 V compared to traditional designs.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.