{"title":"一种2.5 ~ 48gb /s 16.6 ns开埠时间NRZ/PAM4脉冲快速开/关波特率话单技术","authors":"Jihee Kim;Yunhee Lee;Hyun-Seok Choi;Yoona Lee;Sanghee Lee;Woo-Seok Choi","doi":"10.1109/TCSII.2025.3594475","DOIUrl":null,"url":null,"abstract":"This brief presents an NRZ/PAM4 rapid-on/off baud-rate clock and data recovery (CDR) for mobile interfaces, featuring power-efficient bandwidth scaling. To minimize power overhead due to large turn-on time, a pulse-based rapid clock recovery method is proposed. This method estimates and immediately compensates for initial phase error based on a pre-trained look-up table, significantly reducing the CDR’s turn-on time. In addition, a background PAM4 eye-climbing algorithm (ECA) addresses the sub-optimal lock point issue of conventional baud-rate phase detectors by adjusting the lock point to maximize the vertical eye margin (VEM). The prototype receiver fabricated in a 28 nm CMOS supports data rates from 2.5 to 48Gb/s, accommodating both legacy and next-generation mobile interfaces. It achieves an energy efficiency of 1.43 pJ/b at 48 Gb/s while demonstrating a fast turn-on time of 16.6 ns, enabling superior energy efficiency across various effective data rates. Moreover, the PAM4 ECA increases VEM of the PAM4 middle eye by 18 mV, ensuring error-free operation.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1193-1197"},"PeriodicalIF":4.9000,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces\",\"authors\":\"Jihee Kim;Yunhee Lee;Hyun-Seok Choi;Yoona Lee;Sanghee Lee;Woo-Seok Choi\",\"doi\":\"10.1109/TCSII.2025.3594475\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents an NRZ/PAM4 rapid-on/off baud-rate clock and data recovery (CDR) for mobile interfaces, featuring power-efficient bandwidth scaling. To minimize power overhead due to large turn-on time, a pulse-based rapid clock recovery method is proposed. This method estimates and immediately compensates for initial phase error based on a pre-trained look-up table, significantly reducing the CDR’s turn-on time. In addition, a background PAM4 eye-climbing algorithm (ECA) addresses the sub-optimal lock point issue of conventional baud-rate phase detectors by adjusting the lock point to maximize the vertical eye margin (VEM). The prototype receiver fabricated in a 28 nm CMOS supports data rates from 2.5 to 48Gb/s, accommodating both legacy and next-generation mobile interfaces. It achieves an energy efficiency of 1.43 pJ/b at 48 Gb/s while demonstrating a fast turn-on time of 16.6 ns, enabling superior energy efficiency across various effective data rates. Moreover, the PAM4 ECA increases VEM of the PAM4 middle eye by 18 mV, ensuring error-free operation.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 9\",\"pages\":\"1193-1197\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-07-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11105515/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11105515/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces
This brief presents an NRZ/PAM4 rapid-on/off baud-rate clock and data recovery (CDR) for mobile interfaces, featuring power-efficient bandwidth scaling. To minimize power overhead due to large turn-on time, a pulse-based rapid clock recovery method is proposed. This method estimates and immediately compensates for initial phase error based on a pre-trained look-up table, significantly reducing the CDR’s turn-on time. In addition, a background PAM4 eye-climbing algorithm (ECA) addresses the sub-optimal lock point issue of conventional baud-rate phase detectors by adjusting the lock point to maximize the vertical eye margin (VEM). The prototype receiver fabricated in a 28 nm CMOS supports data rates from 2.5 to 48Gb/s, accommodating both legacy and next-generation mobile interfaces. It achieves an energy efficiency of 1.43 pJ/b at 48 Gb/s while demonstrating a fast turn-on time of 16.6 ns, enabling superior energy efficiency across various effective data rates. Moreover, the PAM4 ECA increases VEM of the PAM4 middle eye by 18 mV, ensuring error-free operation.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.