{"title":"A D-Band Low-Noise Amplifier With Gm-Boosting Technique Based on Asymmetric Coupling","authors":"Yun Qian;Yizhu Shen;Yifan Ding;Sanming Hu","doi":"10.1109/TCSII.2025.3555310","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3555310","url":null,"abstract":"This brief presents a D-band low noise amplifier (LNA) in a 40 nm bulk CMOS process. The proposed LNA includes five stages of single-ended common-gate amplifiers. The input and interstage matching networks are realized by asymmetric transformers, which effectively enhance the equivalent transconductance <inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula> of the subsequent transistor. The asymmetric transformer features the segmented structure, offering enhanced design flexibility, and exhibits characteristics of low loss and low parasitic parameters, enabling broadband matching. Leveraging the asymmetric transformer, the LNA achieves simultaneous matching of impedance and noise. The measured power gain is 18.4 dB, with a 3-dB bandwidth of 26.8 GHz from 139.9 to 166.7 GHz. Within the effective bandwidth, the measured minimum noise figure is 5.7 dB. The LNA operates with a power consumption of 17.3 mW under a 0.9 V supply, featuring a total area of <inline-formula> <tex-math>$0.184~{mathrm {mm}}^{2}$ </tex-math></inline-formula> and a core area of 0.062 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"708-712"},"PeriodicalIF":4.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs","authors":"Xing Wang;Chaoyang Xing;Yi Zhong;Lu Jie;Nan Sun","doi":"10.1109/TCSII.2025.3554617","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3554617","url":null,"abstract":"Data weighted averaging (DWA) is a frequently used dynamic element matching (DEM) technique to shape the mismatch error in <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADCs. However, DWA faces a weak noise-shaping capability issue and introduces harmonic distortion under small signal inputs. By contrast, 2nd-order DEM solves these problems but suffers from the high hardware complexity issue. To address these issues, this brief presents a first-in-last-out DWA (FILO-DWA) technique for multi-bit <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADCs. This technique combines the merits of DWA and 2nd-order DEM. Compared with DWA, it introduces no harmonics and enhances the mismatch shaping ability. In contrast to the 2nd-order vector-quantizer-based (VQ-based) DEM scheme, it achieves more than 10 times hardware cost reduction with negligible shaping ability loss. This technique offers a feasible DWA alternative for high-accuracy <inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula> ADC design.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"703-707"},"PeriodicalIF":4.0,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 10-Bit 500-MS/s Pipelined SAR ADC With Feedback Factor Compensation in 6-nm FinFET","authors":"Yigi Kwon;Jongyoon Won;Byounghan Min;Dooyeoun Kim;Jihyun Kim;Jeong-Hyu Yang;Youngcheol Chae","doi":"10.1109/TCSII.2025.3554297","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3554297","url":null,"abstract":"This brief introduces an energy-efficient 10-bit 500-MS/s pipelined SAR ADC that uses feedback factor compensation in 6-nm FinFET technology. The design challenges of residue amplifier in FinFET technology are adequately addressed by incorporating feedback factor compensation. This includes a dynamic negative capacitance circuit at the virtual ground that compensates for the feedback factor and relaxes the requirements of the residue amplifier. This enables the use of an inverter-based residue amplifier that can achieve a high-speed operation of 500-MS/s at a low supply voltage of 0.9 V. The prototype ADC is fabricated in a 6-nm FinFET and occupies 0.014 <inline-formula> <tex-math>$text {mm}^{{2}}$ </tex-math></inline-formula>. With a Nyquist input signal, it achieves an SNR of 54.2 dB and an SNDR of 53.6 dB, while consuming 2.7 mW from a 0.9 V supply voltage. This brief achieves a competitive Walden figure of merit (FoM) of 13.8 fJ/conv.-step.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"698-702"},"PeriodicalIF":4.0,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cooperative Resilient Secondary Control for AC/DC Microgrid Under Cyber Attacks","authors":"Kejie Wang;Sha Fan;Mengmeng Chen;Chao Deng","doi":"10.1109/TCSII.2025.3554348","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3554348","url":null,"abstract":"In this brief, the distributed resilient secondary control problems under hybrid attacks involving false data injection (FDI) and denial-of-service (DoS) attacks in hybrid AC/DC microgrids (MGs) are investigated. To address these issues, a distributed iterative observer is first designed to accurately estimate the FDI attack signal as well as the AC bus frequency, the AC main bus voltage, active power, and reactive power of each BIC under hybrid attacks. Then, based on the iterative mean estimation, a distributed resilient secondary controller is designed to compensate for the hybrid attacks, achieving the accurate recovery of AC bus frequency and AC main bus voltage as well as active/reactive power sharing among BICs under hybrid attacks. Compared with existing results, the proposed distributed resilient control strategy enhances the transient performance of AC/DC hybrid MGs during both the injection and disappearance of FDI attacks against hybrid attacks. Finally, through theoretical analysis and a real-time experiment in OPAL-RT, the effectiveness and plug-and-play performance of the proposed method is verified.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"743-747"},"PeriodicalIF":4.0,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ya Zhao;Lingao Huang;Runchen Wang;Jun Yin;Pui-In Mak;Li Geng;Chao Fan
{"title":"A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA","authors":"Ya Zhao;Lingao Huang;Runchen Wang;Jun Yin;Pui-In Mak;Li Geng;Chao Fan","doi":"10.1109/TCSII.2025.3553716","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3553716","url":null,"abstract":"This brief describes an area-efficient LC-ring oscillator featuring an ultra-compact transformer resonator. The series inverters could be equivalent to the negative resistors providing gain compensation. The involved inverters and switched-capacitor banks are fully integrated underneath the transformer resonator. Thus, with a comparable area of the typical ring oscillators, our oscillator shows significantly improved phase noise (PN) and figure-of-merit (FoM). Besides, we implemented the stacked-coupling and distributed-coupling transformer-based LC-ring oscillators for the PN and FoM comparison. The stacked-coupling LC-ring oscillator can lower the PN with the same frequency and power budget. Fabricated in 40-nm CMOS, our stacked-coupling LC-ring oscillator scores a <inline-formula> <tex-math>${mathrm { PN}}_{unicode {0x0040}1{mathrm { MHz}}}$ </tex-math></inline-formula> of -110.4 dBc/Hz across the frequency tuning range from 3.7 to 5.1 GHz with an active area of 0.0019 mm2, corresponding to a superior FoM (FoMA)<inline-formula> <tex-math>${}_{text {@1MHz}}$ </tex-math></inline-formula> of 175.2 dBc/Hz (202.4 dBc/Hz) that is 4.2 dB (6 dB) higher than the distributed-coupling LC-ring oscillator.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"693-697"},"PeriodicalIF":4.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fei Tan;Yujia Wang;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak
{"title":"A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm","authors":"Fei Tan;Yujia Wang;Wei-Han Yu;Ka-Fai Un;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3552970","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552970","url":null,"abstract":"In this brief, we propose an ultra-low-power mel frequency cepstral coefficients (MFCCs)-free keyword switchable KWS system that supports ten sub-classifiers (2 keywords each, 20 keywords in total) through a time-domain transferred training convolutional neural network (TT-CNN). The proposed TT-CNN reduces the model size by sharing the first two convolutional layers with all the keywords with a transferred training approach. Hence, the power budget for memory and computation is largely reduced. The TT-CNN supports flexible keyword demand in different scenes by selecting different kernels in the custom-designed 5T-SRAM. The time-domain feature of the proposed TT-CNN avoids the power-hungry feature extractor (FEx), further reducing the overall power consumption. To benchmark with the state-of-the-art, we demonstrated the proposed system with two cascaded scalable 10-Class KWS chips in 28nm CMOS. Our design achieves a high accuracy of 92.8% on 20 keywords from the Google speech command dataset (GSCD). It also shows that the memory overhead for each keyword can be reduced by 20% with the lowest reported 20-class KWS power consumption of <inline-formula> <tex-math>$1.2~mu $ </tex-math></inline-formula> W.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"803-807"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Reduced Capacitance H-9 Five-Level Switched Boost Capacitor Transformerless Inverter","authors":"Md Sartaj Ahmed;Ravi Raushan;Md Waseem Ahmad","doi":"10.1109/TCSII.2025.3552764","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552764","url":null,"abstract":"Transformerless switched capacitor-based multi-level inverters are well-known for their applications in industrial and renewable energy systems. The primary features of a switched capacitor-based transformerless inverter should be minimizing leakage current for safety and minimizing ripple current for efficiency and reliability. This brief proposes a new single-stage, single-phase, five-level H-9-based transformerless inverter for standalone PV systems. This H-9 inverter, utilizes nine switches to produce the desired output voltage levels. It achieves boost functionalities by combining the switched capacitor (SC) unit with the switched boost (SB) unit in a single design. This topology effectively mitigates the leakage current by virtually grounding the load terminal through the filter capacitor. Furthermore, the ripple current of the capacitors in the switched-capacitor unit is minimized, and it is inherently balanced. To this end, the feasibility of utilizing the modulation technique for control is demonstrated, and the relevant results are experimentally validated using a laboratory prototype of the proposed converter.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"788-792"},"PeriodicalIF":4.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Single-XO Dual-Output Frequency Reference Featuring Adaptive RTC Calibration Achieving 0.63 ppm/°C Temperature Coefficient From –40 °C to 125 °C","authors":"Rui Luo;Ka-Meng Lei;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3552650","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552650","url":null,"abstract":"This brief presents a trimming-free single-crystal dual-output (SXDO) frequency reference featuring adaptive binary-search (ABS)-based real-time clock (RTC) calibration. The on-demand 16-MHz crystal oscillator (XO) can serve as a frequency reference to calibrate the always-on 1-MHz on-chip RTC. To suppress the inaccurate calibration in the wake of the oscillator’s jitter, we propose the ABS-based calibration to adjust the accumulation cycles depending on the frequency difference between the XO and RTC to enhance the comparison accuracy. Further, we reuse the accurately calibrated RTC signal as a reference to generate a 16-MHz pulse train and inject it into the crystal to expedite the XO startup. We implemented the proposed SXDO frequency reference in a 65-nm CMOS process. The RTC achieves a temperature coefficient of 0.63 ppm/°C across -40 to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C. The calibration takes <inline-formula> <tex-math>$720~mu $ </tex-math></inline-formula>s while consuming 40.3 nJ of energy. The XO, benefitting from the RTC-assisted constant injection with improved accuracy, can exert injection of <inline-formula> <tex-math>$60~mu $ </tex-math></inline-formula>s and attain a startup time of <inline-formula> <tex-math>$145~mu $ </tex-math></inline-formula>s, with a startup energy of 9.9 nJ.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"688-692"},"PeriodicalIF":4.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Youming Zhang;Fengyi Huang;Xusheng Tang;Junjie Li;Zhennan Wei;Yunqi Cao
{"title":"A 4 × 4 Fully Integrated RF Transceiver in 6 GHz Frequency Band With Single-Channel Bandwidth of 400 MHz and PHY Data-Rate of 8.8 Gbps","authors":"Youming Zhang;Fengyi Huang;Xusheng Tang;Junjie Li;Zhennan Wei;Yunqi Cao","doi":"10.1109/TCSII.2025.3552472","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3552472","url":null,"abstract":"This brief presents a fully integrated CMOS <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> MIMO RF transceiver (TRX) with single-channel bandwidth (BW) of 400 MHz in the 6 GHz band (5.925-7.125 GHz). In the receiver (RX) frontend, an improved noise-canceling low noise amplifier (LNA) and a cross-coupled transconductance <inline-formula> <tex-math>$(G_{M})$ </tex-math></inline-formula> with IIP2 enhancement is implemented. In the transmitter (TX) frontend, a power amplifier driver (PAD) is integrated with cascade AM-PM distortion compensation to eliminate the AM-PM distortion. A hierarchical LO distribution network is employed in the 1-to-4 LO distribution chain to enhance the consistency among the LO branches. The single-chip TRX is reconfigurable for TDD/FDD operation, with the RX exhibiting a noise figure of 3.5-4.1 dB, a gain control range of 45 dB with 1 dB step and ±0.2 dB gain flatness. The TX output spectrum exhibits >32 dBc signal to noise ratio (SNR). The RX and TX error vector magnitudes (EVMs) are −30.2 dB and −30.5 dB, respectively, with 160 MHz BW 256QAM. A TX-to-RX PHY data-rate of 8.8 Gbps based on <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> MIMO is achieved, with other major parameters comparable to the prior arts without resorting to digital calibration circuits.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"723-727"},"PeriodicalIF":4.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Longning Qi;Jinqi Fan;Tongheng Rao;Meiyan Lv;Jingu Ma;Hao Cai
{"title":"Energy Efficient On-Chip Memory for Next Generation MCU","authors":"Longning Qi;Jinqi Fan;Tongheng Rao;Meiyan Lv;Jingu Ma;Hao Cai","doi":"10.1109/TCSII.2025.3551733","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3551733","url":null,"abstract":"Microcontroller units (MCUs) are increasingly required to be energy-conserving for IoT applications. Emerging devices, such as magnetic tunnel junctions and tunnel field-effect transistors (TFETs), present innovative solutions for ultra-low-power embedded memories. This brief demonstrates MRAM and TFET-SRAM as alternatives to embedded Flash and retention SRAM in MCUs, respectively. A specially designed sense amplifier capable of bidirectional voltage differential amplification enables two readouts during the charge/discharge phase of bit lines. Furthermore, a mismatch-aware latch amplifier is proposed to yield considerable read accuracy of MRAM. The bidirectional read strategy, named Ri-Fa, efficiently eliminates unnecessary error correction process. Under 28-nm CMOS technology, the 512Kb MRAM achieves <15ns> <tex-math>$2.23{mu }$ </tex-math></inline-formula>A/MHz. Furthermore, the TFET/CMOS hybrid bit-cell introduces an extra n-type TFET to gate the supply of SRAM in retention mode, suppressing the leakage current of 1Kb macro to 6nA. The 55-nm MCU with TFET-SRAM presents a record ultra-low standby power of 75nA.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"768-772"},"PeriodicalIF":4.0,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}