IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

{"title":"A 357–706-MHz Low-Pass Filter With Oscillator Mode for Bandwidth Calibration","authors":"Tian Tian;Yanshu Guo;Wenqiang Huang;Guo Wei;Zhihua Wang;Yuanjin Zheng;Hanjun Jiang","doi":"10.1109/TCSII.2025.3550938","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550938","url":null,"abstract":"This brief presents a 357–706 MHz dual-mode low-pass filter featuring an oscillator-based calibration method to address bandwidth deviations caused by process variations and component mismatches, eliminating the need for a high-frequency reference signal. Compared to conventional replica-based approaches, the proposed dual-mode oscillator calibration improves correlation coefficients from 0.922 to 0.978, as demonstrated by Monte Carlo simulations. Fabricated in 28-nm CMOS technology, the 3rd-order Butterworth active-RC filter occupies only 0.03 mm2 and consumes 3.8 mW from a 0.9 V supply. It achieves a bandwidth range of 357–706 MHz, an input-referred noise of <inline-formula> <tex-math>$5.18~{nV/}sqrt {Hz}$ </tex-math></inline-formula>, an in-band IIP3 of 17.65 dBm, and a figure-of-merit (FoM) of 0.015 fJ. Pearson’s correlation coefficients between the filter bandwidth and oscillator frequency are 0.96 and 0.97 across temperature ranges from −60°C to 80°C and supply voltages from 0.8 to 1.4 V, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"673-677"},"PeriodicalIF":4.0,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Power 270-GHz Oscillator With Harmonic Output Power Optimization Using Series Resonance Feedback","authors":"Abdul Qahir;Kyung-Sik Choi;Jong-Phil Hong;Sang-Gug Lee","doi":"10.1109/TCSII.2025.3550870","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550870","url":null,"abstract":"This brief proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the oscillator at the fundamental frequency while increasing the output power at the second harmonic by enabling a larger transistor size and minimizing the common-mode output conductance. Implemented in the 28-nm CMOS technology, the proposed 270-GHz oscillator achieves a peak output power of −3.2 dBm, a peak dc-to-RF efficiency of 0.81% and phase noise values of −56.8, −84.68 and −90.12 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offsets, respectively.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"668-672"},"PeriodicalIF":4.0,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-Bit Capacitance Sensing System Using a-IGZO TFT Technology for Smart Wearables","authors":"Bhawna Tiwari;Suyash Shrivastava;Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/TCSII.2025.3549921","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3549921","url":null,"abstract":"This brief presents a novel multi-bit Capacitance-to-Digital converter (CDC) using unipolar single-gate amorphous-Indium-Gallium-Zinc-Oxide thin-film transistors (a-IGZO TFTs). This circuit is fabricated on a <inline-formula> <tex-math>$30{mathrm {,}} mu $ </tex-math></inline-formula> m thick polyimide substrate with an active area of <inline-formula> <tex-math>$6.5{mathrm {,}}$ </tex-math></inline-formula> mm2. The proposed CDC is designed by employing Charge-Sharing Successive-Approximation Register Analog-to-Digital Converter (CS SAR ADC). Further, the design facilitates integration of capacitance sensor/array directly with the ADC, hence the additional interfacing circuits between the capacitive-sensor and the ADC can be eliminated to make the system compact and energy-efficient. The functionality of the proposed CDC is demonstrated for a sensor capacitance value ranging from <inline-formula> <tex-math>$1{mathrm {,}}$ </tex-math></inline-formula> pF to <inline-formula> <tex-math>$31{mathrm {,}}$ </tex-math></inline-formula> pF. From measurements it is observed that the minimum value of capacitance that can be detected with the proposed CDC is around <inline-formula> <tex-math>$2{mathrm {,}}$ </tex-math></inline-formula> pF, while the state-of-the-art CDC is around <inline-formula> <tex-math>$3.7{mathrm {,}}$ </tex-math></inline-formula> pF, which is reported on a truly flexible substrate. Further, the ADC deployed in the CDC has resulted in an SNR of <inline-formula> <tex-math>$35.57{mathrm {,}}$ </tex-math></inline-formula> dB, figure-of-merit (FoM) of <inline-formula> <tex-math>$19.9{mathrm {,}}$ </tex-math></inline-formula> nJ/c.s., ENOB of <inline-formula> <tex-math>$5.6{mathrm {,}}$ </tex-math></inline-formula> bits, differential non-linearity (DNL) of <inline-formula> <tex-math>$0.52{mathrm {,}}$ </tex-math></inline-formula> LSB and an integral non-linearity (INL) of <inline-formula> <tex-math>$0.81{mathrm {,}}$ </tex-math></inline-formula> LSB. At a sampling frequency of <inline-formula> <tex-math>$2.08{mathrm {,}}$ </tex-math></inline-formula> kHz, the ADC has shown a total power dissipation of <inline-formula> <tex-math>$2.02{mathrm {,}}$ </tex-math></inline-formula> mW with a supply voltage <inline-formula> <tex-math>$(V_{DD})$ </tex-math></inline-formula> of <inline-formula> <tex-math>$4{mathrm {,}}$ </tex-math></inline-formula> V. This capacitance sensing system finds potential applications in areas of biomedical, healthcare, and smart packaging systems etc, which need truly flexible devices.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"663-667"},"PeriodicalIF":4.0,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fixed-Time Adaptive Extended State Observer-Based Enhanced ADRC for Electric Motor Drives","authors":"Haiyang Cao;Yongting Deng;Xiufeng Liu;Yiming Shen;Yang Liu;Christopher H. T. Lee","doi":"10.1109/TCSII.2025.3549070","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3549070","url":null,"abstract":"In order to achieve fast convergence of the estimated state and improve the estimation accuracy, a fixed-time adaptive extended state observer (FAESO) is developed for electric motor drives within the active disturbance rejection control (ADRC) framework. First of all, an error adaptive arctangent function is introduced in the design of the FAESO to dynamically improve the lumped disturbance estimation performance of the motor mechanical dynamics. Then, the fixed-time convergence property of the studied FAESO is demonstrated based on the homogeneous theory and Lyapunov function. After the disturbance is estimated quickly and accurately, the error feedback control law is presented to achieve disturbance rejection of the speed loop. The proposed scheme improves the estimation accuracy and convergence rate and enhances the disturbance rejection performance. Finally, the validity and superiority of the proposed FAESO-based enhanced ADRC are verified through three sets of comparative simulation results.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"738-742"},"PeriodicalIF":4.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly-Efficient Broadband GaAs HBT Doherty Power Amplifier With Harmonic Control Technique for 5G Application","authors":"Shuang Liu;Jingzhou Pang;Ruibin Gao;Zhijiang Dai;Mingyu Li;Shichang Chen;Weimin Shi","doi":"10.1109/TCSII.2025.3549058","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3549058","url":null,"abstract":"This brief presents the design and fabrication of a highly-efficient Doherty power amplifier (DPA) for 5G n77 and n78 bands. The proposed architecture is based on a 2-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaAs heterojunction bipolar transistor (HBT) process to realize a monolithic microwave integrated circuit (MMIC) with an area of <inline-formula> <tex-math>$1.7times 1.4~{{text {mm}}^{{2}}}$ </tex-math></inline-formula>. Additionally, An output network is designed in conjunction with the load modulation network on the Rogers 4350 PCB, which is augmented with high-order harmonic control circuit for efficiency enhancement. The proposed DPA, operating within the 3.1-4.2 GHz range, exhibits a fractional bandwidth over 30%, a saturated output power over 33.8 dBm, a saturated power-added efficiency (PAE) ranging from 39.6% to 44.9%, and a 6 dB power back-off (PBO) PAE of 42.3% to 46.1%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"713-717"},"PeriodicalIF":4.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Depletion-Mode GaN-Based Envelope Tracking Supply Modulator Utilizing a Novel Coupled PWM Generator","authors":"Chenhao Li;Chunyue Bo;Xiaoyu Hu;Xiangcong Zhai;Ke Wei;Xinyu Liu;Weijun Luo","doi":"10.1109/TCSII.2025.3548642","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3548642","url":null,"abstract":"This brief presents a depletion-mode GaN-based envelope tracking supply modulator (ETSM) that employs a novel Coupled Pulse Width Modulation (PWM) Generator. The Coupled PWM Generator consists of an integrated common-source amplifier and several passive components. With the proposed PWM generator, the d-mode GaN-based ETSM can be directly controlled by an input envelope signal instead of a pair of PWM signals, thereby eliminating the demand for an extra PWM process. The measured peak output power of the ETSM is 5.4 W, with a total efficiency of 89% at 100 MHz switching frequency. When tracking a Long Term Evolution (LTE) signal with a 20 MHz bandwidth and a 6.5 dB peak-to-average power ratio (PAPR), the ETSM achieves a total efficiency of 81%, with an average output power of 2.32 W and a Normalized Root Mean Square Error (NRMSE) of 3.9%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"778-782"},"PeriodicalIF":4.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HEAT: Efficient Vision Transformer Accelerator With Hybrid-Precision Quantization","authors":"Pan Zhao;Donghui Xue;Licheng Wu;Liang Chang;Haining Tan;Yinhe Han;Jun Zhou","doi":"10.1109/TCSII.2025.3547340","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3547340","url":null,"abstract":"Quantization is an important technique for the acceleration of transformer-based neural networks. Prior related works mainly consider quantization from the algorithm level. Their hardware implementation is inefficient. In this brief, we propose an efficient vision transformer accelerator with retraining-free and finetuning-free hybrid-precision quantization. At the algorithm level, the features and weights are divided into two parts: normal values and outlier values. These two parts are quantized with different bit widths and scaling factors. We use matrix transformation and group-wise quantization policy to improve hardware utilization. At the hardware level, we propose a two-stage FIFO group structure and a hierarchical interleaving data flow to further improve the utilization of the PE array. As a result, the input and weight matrices are quantized to 5.71 bits on average with 0.526 <inline-formula> <tex-math>${%}$ </tex-math></inline-formula> accuracy loss on Swin-T. The accelerator achieves a frame rate of 118.9 FPS and an energy efficiency of 43.58 GOPS/W on the ZCU102 FPGA board, better than state-of-the-art works.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"758-762"},"PeriodicalIF":4.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust and Reliable Energy-Efficient Level Shifter","authors":"Mahipal Dargupally;Lomash Chandra Acharya;Neha Gupta;Ahrron Kongala;Arvind Sharma;Sudeb Dasgupta;Anand Bulusu","doi":"10.1109/TCSII.2025.3547667","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3547667","url":null,"abstract":"In this brief, we propose an energy-efficient level shifter (LS) for converting a wide range of supply voltages for digital integrated circuit applications. The proposed novel circuit is a two-stage LS comprising of current mirror (CM) based circuit followed by the split inverter. A feedback mechanism, current-limiter PMOS, and pass transistor are used to resolve the current contention, static power dissipation, and improved minimum conversion time. The proposed LS shows a reduced impact of variability across various PVT corners, making it a viable solution for low-voltage digital systems. The proposed LS shows a propagation delay of 3.01 ns (0.67 ns), an energy per transition of 1.84 fJ (0.595 fJ) for converting 0.3 V (0.2 V) to 1.2 V (1 V) in CMOS 65 nm (FDSOI 28 nm) process, and a lower energy-delay product (EDP) compared to current state-of-the-art designs. With static power dissipation of 280 pW at 0.3 V input, it also features an average minimum convertible input level (<inline-formula> <tex-math>$rm V_{DDL}$ </tex-math></inline-formula>) of 100 mV at a 1-MHz (20-MHz) frequency. Simulations were performed in a commercial CMOS 65 nm and FDSOI 28 nm processes with Cadence VIRTUOSO and Synopsys HSPICE environments.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"763-767"},"PeriodicalIF":4.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A V-Band FMCW Signal Generator With Hybrid Dual-Path VCO Technique Achieving 13.6-GHz Chirp Bandwidth","authors":"Jiangbo Chen;Shengjie Wang;Quanyong Li;Wenyan Zhao;Jingwen Xu;Nayu Li;Chunyi Song;Qun Jane Gu;Zhiwei Xu","doi":"10.1109/TCSII.2025.3547342","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3547342","url":null,"abstract":"This brief presents a V-band frequency-modulation continuous wave (FMCW) signal generator for high-resolution radar applications. The proposed hybrid dual-path voltage-controlled oscillator (VCO) employs a digital-assisted capacitance decoding scheme, fully utilizing the tunable capacitance to achieve wideband chirping while maintaining high chirp linearity. To verify the proposed scheme, a radar transceiver with two transmit (TX) channels, and four receive (RX) channels is designed and fabricated in a 65-nm CMOS process. The FMCW signal generator occupies 2.98 mm2 and consumes 120 mW. A measured maximum chirp bandwidth of 13.6 GHz is achieved at TX output with an rms frequency error of 0.008%. The measured phase noise of the VCO is −97.37 dBc/Hz at a 1-MHz offset from a 60-GHz carrier. The proposed FMCW signal generator demonstrates a state-of-the-art chirp bandwidth at V-band.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"658-662"},"PeriodicalIF":4.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3561651","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3561651","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981832","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}