IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第3页

A Compact, Low-Power Voltage-Gap-Based Power-On-Reset Circuit With a Programmable Trip Point for Near-VTH Computing Applications 一种紧凑、低功耗、基于电压间隙的复位电路，具有可编程跳闸点，用于近vth计算应用

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-06 DOI: 10.1109/TCSII.2026.3710478

Yoochang Kim;Inseo Son;Young-Ha Hwang

{"title":"A Compact, Low-Power Voltage-Gap-Based Power-On-Reset Circuit With a Programmable Trip Point for Near-VTH Computing Applications","authors":"Yoochang Kim;Inseo Son;Young-Ha Hwang","doi":"10.1109/TCSII.2026.3710478","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3710478","url":null,"abstract":"This brief presents a compact, low-power voltage-gap-based power-on-reset (POR) circuit for near-<inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula> computing (NVTC) applications. The proposed POR circuit employs a configurable voltage-gap generator (VGG), a trip-point-programmable voltage-gap detector (VGD), and an active-low pulse generator (ALPG). During a power-on sequence, the VGG generates a capacitive reference voltage gap, eliminating dc current in the reference-generation path at steady state. The VGD detects the reference voltage gap and then triggers the ALPG to generate a reliable POR signal. After successful POR operation, the VGD is power-gated to further reduce the quiescent current. In addition, the proposed POR circuit is implemented only with regular-<inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula> MOSFETs, enhancing process portability. Fabricated in a 28-nm CMOS process, the prototype POR circuit supports a supply-voltage range from 0.6 V to 0.8 V and a ramp-time range from <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>s to 10 ms, while occupying a compact area of <inline-formula> <tex-math>$414.7~mu $ </tex-math></inline-formula>m<sup>2</sup>. With VGD power gating, the prototype POR circuit consumes only 5.4 nW of static power at <inline-formula> <tex-math>$V_{mathrm {DD}} =0.6$ </tex-math></inline-formula> V, demonstrating its suitability for low-power NVTC systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"823-827"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148626292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real-Time Gesture Recognition Using Multi-Channel sEMG Signals With Spatial-Temporal Spiking Neural Network 基于时空尖峰神经网络的多通道表面肌电信号实时手势识别

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-16 DOI: 10.1109/TCSII.2026.3704078

Hongxin Li;Qian Zhong;Jingsheng Tang;Lingfeng Yan;Wei Dai;Yaru Liu;Zongtan Zhou

引用次数: 0

An 8.3-to-21.8-GHz 7-mW LNA With Parasitic-Aware Co-Designed Interstage Triple-Coupled Transformer 8.3 ~ 21.8 ghz 7-mW LNA级间三耦合互感器寄生感知

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-22 DOI: 10.1109/TCSII.2026.3706119

Xuan Li;Zenglong Zhao;Nengxu Zhu;Fanyi Meng

引用次数: 0

A Highly Integrated Analog Front-End Combining Level Shifter, Programmable Gain Amplifier, and Low-Pass Filter for Automotive BMS 一种高度集成的模拟前端，结合电平移位器、可编程增益放大器和低通滤波器，用于汽车BMS

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-24 DOI: 10.1109/TCSII.2026.3706487

Xudong Chen;Weipeng He;Ning Li;Rongqing Sheng;Yajuan He;Qiang Li;Haoyu Zhuang

{"title":"A Highly Integrated Analog Front-End Combining Level Shifter, Programmable Gain Amplifier, and Low-Pass Filter for Automotive BMS","authors":"Xudong Chen;Weipeng He;Ning Li;Rongqing Sheng;Yajuan He;Qiang Li;Haoyu Zhuang","doi":"10.1109/TCSII.2026.3706487","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3706487","url":null,"abstract":"This brief presents a highly integrated analog front-end (AFE) for automotive battery management systems (BMS). The proposed AFE combines level shifter (LS), programmable gain amplifier (PGA), and low-pass filter (LPF) functions into a single switched-capacitor architecture. Additionally, an offset cancellation scheme is employed to cancel the amplifier offset. Designed in a 130 nm BCD process, the proposed circuit utilizes capacitively-coupled inputs along with high-voltage (HV) switches realized with 5 V MOS devices placed in isolated N-Buried layer (NBL) pockets to handle input voltages up to 100 V. The circuit simultaneously provides programmable gain from 1 to 5 times and first-order low-pass filtering with a 1.6 kHz cutoff frequency for anti-aliasing. This three-in-one integration significantly reduces component count, system complexity, and power consumption compared to traditional cascade approaches. Designed for 125 kS/s operation, the AFE enables high-precision cell voltage monitoring with over 16-bit effective number of bits (ENOB). Operating at a 5 V supply, the AFE consumes only <inline-formula> <tex-math>$330~mu $ </tex-math></inline-formula>A (not including the ADC), making it a highly efficient solution for electric vehicle BMS applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"803-807"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cryogenic Model-Guided All-CMOS Voltage Reference and LDO for 30–298 K Operation With a 34.5 ppm/K Temperature Coefficient 低温模型引导的全cmos电压基准和LDO为30-298 K操作，温度系数为34.5 ppm/K

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-07-09 DOI: 10.1109/TCSII.2026.3711906

Yiyao Zhu;Chang He;Zewei Wang;Fengyu Liu;Xufeng Kou

引用次数: 0

A 505--613 GHz Radiating Source With 65 GHz 3-dB EIRP Bandwidth in 65-nm CMOS Technology 505- 613 GHz辐射源，65 GHz 3db EIRP带宽，65纳米CMOS技术

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-17 DOI: 10.1109/TCSII.2026.3704610

Huanting Deng;Houyi Yan;Yihan Wang;Kaizhe Guo;Dixian Zhao

{"title":"A 505--613 GHz Radiating Source With 65 GHz 3-dB EIRP Bandwidth in 65-nm CMOS Technology","authors":"Huanting Deng;Houyi Yan;Yihan Wang;Kaizhe Guo;Dixian Zhao","doi":"10.1109/TCSII.2026.3704610","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3704610","url":null,"abstract":"This brief presents a 0.56-THz wideband radiating source implemented in 65-nm CMOS. The stable, wideband signal generation is achieved via an oscillator-multiplier architecture with a high multiplication factor and wideband interstage matching. Broadband transformer-based matching networks are used between the amplifier and multiplier stages to preserve the bandwidth across the chain. A compact second-harmonic trap is introduced to provide a broadband low impedance at the doubler input and improve the conversion gain. An enhanced substrate-integrated-waveguide (SIW) harmonic power extractor (HPE) is employed to provide the required fundamental and third-harmonic impedances, while suppressing undesired lower-order harmonic leakage in a tripler with a large transistor size. The prototype achieves a frequency tuning range of 505–613 GHz, corresponding to a fractional bandwidth of 19.3%, and a 3-dB equivalent isotropic radiated power (EIRP) bandwidth of 65 GHz. The maximum radiated power and EIRP are −10.4 dBm and 15.5 dBm, respectively. The chip consumes a dc power of 128.6 mW at the center operating frequency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 8","pages":"793-797"},"PeriodicalIF":4.6,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A High-Spectral-Efficient Quadrature Ergodic Chaotic Parameter Modulation Based on Code Index Modulation 基于码索引调制的高频谱效率正交遍历混沌参数调制

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-08-01 Epub Date: 2026-06-29 DOI: 10.1109/TCSII.2026.3708016

Ang Zhou;Shilian Wang

引用次数: 0

A Low-Complexity and Fast Time-Domain I/Q Imbalance Calibration Method for Wideband Direct-Conversion Receivers 一种低复杂度、快速的宽带直接转换接收机时域I/Q不平衡校正方法

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-15 DOI: 10.1109/TCSII.2026.3693887

Jie Shao;ShuTong Wu;LiYi Zhang;YingDan Jiang;XiaoFei Chen

{"title":"A Low-Complexity and Fast Time-Domain I/Q Imbalance Calibration Method for Wideband Direct-Conversion Receivers","authors":"Jie Shao;ShuTong Wu;LiYi Zhang;YingDan Jiang;XiaoFei Chen","doi":"10.1109/TCSII.2026.3693887","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3693887","url":null,"abstract":"This brief presents a hardware-efficient and fast-converging time-domain I/Q imbalance calibration method for wideband direct-conversion receivers. A dual-tone excitation scheme combined with an orthogonality-driven frequency planning strategy in a Tx–Rx loopback architecture enforces orthogonality between undesired spectral components and the desired calibration tones. Exploiting this property, imbalance responses at two frequency points are extracted per iteration. In this work, 64 samples per frequency pair are employed, corresponding to 512 samples in total, which significantly reduces calibration latency and computational complexity. The proposed method introduces minimal hardware overhead and is well suited for practical transceiver implementations. MATLAB-based simulations demonstrate an image rejection ratio (IRR) exceeding 71 dB over a 375 MHz bandwidth. Experimental results obtained on an ADRV9026-based platform achieve a statistical mean IRR exceeding 70 dB over a 315 MHz bandwidth at a 3.2 GHz carrier frequency across multiple independent trials. Compared with existing loopback-based approaches, the proposed method achieves faster parameter convergence while maintaining competitive wideband IRR performance.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"758-762"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 69-fJ/b/dB 28-Gb/s Baud-Rate Receiver With Weight-Adaptive Stochastic CDR in 28-nm CMOS 具有重量自适应随机CDR的28纳米CMOS 69-fJ/b/dB 28-Gb/s波特率接收器

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-06-01 DOI: 10.1109/TCSII.2026.3698782

Yoojin Jung;Sinho Lee;Jun-Soo Park;Hohyun Chae;Ho-Joon Shin;Kwanseo Park

引用次数: 0

A High-SNR SRAM-LUT-Based In-Memory-Computing Macro Supporting Energy-Efficient INT8 and FP8 Computation 基于高信噪比sram - lut的内存计算宏支持高效INT8和FP8计算

IF 4.6 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-15 DOI: 10.1109/TCSII.2026.3693836

Xinhang Zou;Yujin Wang;Luchang Lei;Wenbin Jia;Cheng Peng;Yutong An;Xuanshen Shu;Huazhong Yang;Yongpan Liu;Hongyang Jia

{"title":"A High-SNR SRAM-LUT-Based In-Memory-Computing Macro Supporting Energy-Efficient INT8 and FP8 Computation","authors":"Xinhang Zou;Yujin Wang;Luchang Lei;Wenbin Jia;Cheng Peng;Yutong An;Xuanshen Shu;Huazhong Yang;Yongpan Liu;Hongyang Jia","doi":"10.1109/TCSII.2026.3693836","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3693836","url":null,"abstract":"Recent quantized neural networks require various dynamic ranges and resolutions to enable better inference accuracy, necessitating mixed support of energy-efficient integer and floating point computation. This work presents an SRAM look-up table (LUT) based INT8/FP8 dual mode in-memory-computing (IMC) macro which supports configurable FP8 (E4M3 and E5M2) multiply-accumulate (MAC) operation and 2:8 structural sparsity pruning. Instead of suffering either excessive overheads of shifting and alignment logic or accuracy degradation for extreme energy efficiency, this macro exploits fine-grain exponent sharing and efficient LUT-based MAC circuits to balance the two aspects. The key features are: 1) a pipelined and SNR-oriented mantissa and exponent execution circuit for FP8 multiplication; 2) a LUT-based shifter and 1-stage adder to reduce digital logic overhead in FP MAC; 3) an in-macro decoder to support 2:8 structural sparsity pruning. The silicon prototype in 28nm CMOS achieves 81.69% accuracy for DeiT-base model for ImageNet dataset in dense FP8 mode, and 76.15% accuracy for ResNet-34 model in CIFAR100 dataset in sparse FP8 mode. The 2:8 pruning provides a 31.42 TFLOPS/W peak energy efficiency and 3.56 TFLOPS/mm<sup>2</sup> peak area efficiency in sparse FP8 mode.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"723-727"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0