IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第4页

IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-03-01 DOI: 10.1109/TCSII.2025.3561653

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IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息

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IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-27 DOI: 10.1109/TCSII.2025.3541469

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A 10 to 15 GHz Digital Step Attenuator With Robust Temperature Tolerance Across -55 ∘C to 125 ∘C 10至15 GHz数字阶跃衰减器，具有-55°C至125°C的耐温能力

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-27 DOI: 10.1109/TCSII.2025.3546292

Jiang Luo;Yao Peng;Qiang Cheng

{"title":"A 10 to 15 GHz Digital Step Attenuator With Robust Temperature Tolerance Across -55 ∘C to 125 ∘C","authors":"Jiang Luo;Yao Peng;Qiang Cheng","doi":"10.1109/TCSII.2025.3546292","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3546292","url":null,"abstract":"This brief presents an efficient adaptive analog temperature compensation technique that stabilizes the amplitude and phase performance of an RF attenuator over an ultra-wide temperature range without compromising its other metrics. The approach utilizes an adaptive analog temperature-dependent voltage source (AATVS) to supply the binary digital control array, which indirectly biases the gate terminals of MOSFET switches in the attenuation unit. This method effectively mitigates thermal variations in on-resistance and intrinsic capacitance. To validate the technique, a 5-bit digital step attenuator (DSA) was designed and fabricated using a <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m SiGe BiCMOS process. The DSA exhibited excellent consistency in root-mean-square (RMS) amplitude and phase errors across <inline-formula> <tex-math>$- 55~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C, achieving an RMS attenuation error below 0.24 dB, an RMS phase error under 2.3°, and an insertion loss (IL) better than 4.9 dB over 10–15 GHz. To the best of the authors’ knowledge, this letter is the first to implement an AATVS-based compensation mechanism in a 5-bit DSA, ensuring stable amplitude and phase accuracy under extreme thermal variations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"653-657"},"PeriodicalIF":4.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Circuits and Systems Society Information IEEE电路与系统学会信息

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-27 DOI: 10.1109/TCSII.2025.3541471

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PIMSR: An Energy-Efficient Processing-in-Memory Accelerator for 60 FPS 4K Super-Resolution 面向60 FPS 4K超高分辨率的高效内存处理加速器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-25 DOI: 10.1109/TCSII.2025.3545466

Juntao Guan;Qinghui Guo;Huanan Li;Rui Lai;Ruixue Ding;Libo Qian;Zhangming Zhu

{"title":"PIMSR: An Energy-Efficient Processing-in-Memory Accelerator for 60 FPS 4K Super-Resolution","authors":"Juntao Guan;Qinghui Guo;Huanan Li;Rui Lai;Ruixue Ding;Libo Qian;Zhangming Zhu","doi":"10.1109/TCSII.2025.3545466","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3545466","url":null,"abstract":"Due to the huge computational load, CNN-based super-resolution solutions are hard to be deployed on resource-constrained edge devices. In this brief, we proposed a Processing-in-Memory based SR accelerator (PIMSR) that leverages direct simple memory access operations to supersede intensive multiply-add in convolution operators, thus fundamentally improving the energy efficiency. To address the storage explosion problem, we presented an index reparameterized strategy for shrinking the memory requirement of LUT-based PIMSR framework by <inline-formula> <tex-math>$19.58times $ </tex-math></inline-formula>. Furthermore, an address remapping design is putted forward to solve the access conflict in overlap configuration, which greatly boosts the efficiency of memory access. The prototype validation on low-end XC7A200T FPGA indicates that our design yields a new record of energy efficiency up to 671.61 Mpixels/J, over <inline-formula> <tex-math>$5.36times $ </tex-math></inline-formula> higher than existing deep learning based image processors, with extremely low hardware costs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"623-627"},"PeriodicalIF":4.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Nanopower Folded-Cascode EEG Lowpass Filter 一种纳米级折叠级联EEG低通滤波器

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-25 DOI: 10.1109/TCSII.2025.3545968

Surachoke Thanapitak;Khanittha Kaewdang;Xiao Liu;Prajuab Pawarangkoon

{"title":"A Nanopower Folded-Cascode EEG Lowpass Filter","authors":"Surachoke Thanapitak;Khanittha Kaewdang;Xiao Liu;Prajuab Pawarangkoon","doi":"10.1109/TCSII.2025.3545968","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3545968","url":null,"abstract":"This brief presents a continuous-time lowpass biquadratic cell developed from a folded-cascode OTA operating in the subthreshold region. The proposed cell has been implemented by configuring the OTA in a unity-gain feedback manner and inserting two individual capacitors into the output and internal folding nodes. This allows the proposed biquadratic cell to benefit from the high loop gain that maintains good linearity at passband frequencies well below its cutoff. As an application of this biquadratic cell, a pseudo-differential lowpass filter for electroencephalogram detection is designed and implemented in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m standard CMOS technology. The custom filter occupies a silicon area of <inline-formula> <tex-math>$230~mu $ </tex-math></inline-formula> m <inline-formula> <tex-math>$times 300~mu $ </tex-math></inline-formula> m and operates from a 0.8-V dc supply with 7 nA total current consumption. Multi-chip measurements exhibit the average cut-off frequency at 151.2 Hz, input-referred noise of <inline-formula> <tex-math>$35~mu $ </tex-math></inline-formula> Vrms, and linear range of 110 mVP. This brief achieves the best FoM to date among recent relevant nano-power filters.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 5","pages":"643-647"},"PeriodicalIF":4.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143900450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A 1-Mbps 0.7-nJ/Bit Low-Complexity High-Robust FM-UWB Transmitter Under a Sub-1-V Supply 在sub - 1v电源下的1mbps 0.7 nj /Bit低复杂度高鲁棒FM-UWB发射机

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-25 DOI: 10.1109/TCSII.2025.3546077

Yifan Li;Bo Zhou;Yuyang Ding;Yun Hao;Huikai Xie

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Comments on “Dual-Band Branch-Line Couplers With Short/Open-Ended Stubs” 关于“短/开放式管脚双频支路耦合器”的评论

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-24 DOI: 10.1109/TCSII.2025.3545303

Venakata Sitaraman Puram;Vamsi Krishna Velidi;Arijit De

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Asynchronous Reduced-Order Filtering for Markov Jump Systems and its Application in PWM Circuits 马尔可夫跳变系统的异步降阶滤波及其在PWM电路中的应用

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-21 DOI: 10.1109/TCSII.2025.3544818

Yongqian Wang;Zhenghao Ni;Jing Wang;Ju H. Park;Hao Shen

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A 1.46-pJ/bit, 149-KF² RO TRNG Based on Reference-RO-Free Thresholding of Jitter Accumulation 基于无参比RO累积阈值的1.46 pj /bit、149 kf²RO TRNG

IF 4 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-02-19 DOI: 10.1109/TCSII.2025.3543628

Haibiao Zuo;Qingsen Zhuang;Jiacheng Hao;Haochen Zhong;Xiaojin Zhao

{"title":"A 1.46-pJ/bit, 149-KF² RO TRNG Based on Reference-RO-Free Thresholding of Jitter Accumulation","authors":"Haibiao Zuo;Qingsen Zhuang;Jiacheng Hao;Haochen Zhong;Xiaojin Zhao","doi":"10.1109/TCSII.2025.3543628","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3543628","url":null,"abstract":"In this brief, a ring-oscillator-based true random number generator (RO-TRNG) is presented with an energy-efficient on-chip module for temporal thresholding of the accumulated jitter noise. The need of power-hungry reference ring oscillator (RO) for frequency collapse detection in previous implementation can be completely removed. In addition, by setting the RO-TRNG’s enable signal adaptively according to the output of the proposed jitter accumulation thresholding (JAT) module, the redundant oscillations in most cycles of the prior art can be fully eliminated, leading to significant energy saving per each TRNG bit. Based on a 65-nm 1.2 V standard CMOS process, the fabricated TRNG chips feature an ultra-compact silicon area of 149 K<inline-formula> <tex-math>$F^{2}$ </tex-math></inline-formula>. Meanwhile, a high energy efficiency of 1.46 pJ/bit is achieved for the prototype chips operated under a supply voltage of 1.0 V and an overall throughput of 44.7 Mbps. High randomness of the fabricated TRNG chips is well validated by using both National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools. Moreover, high Shannon entropy values over 0.999998 are observed for the TRNG chips operated under an industrial temperature range of −40°C~125°C and a supply voltage range of 1.0 V~1.4 V, showing excellent tolerance to the process-voltage-temperature (PVT) variations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"618-622"},"PeriodicalIF":4.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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