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IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

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A Multi-Phase Multi-Path Hybrid SC Buck Converter With Enhanced DCR-Loss Reduction and Alleviated ICF Gathering for 9-48 V-Input PoL Conversions 一种用于9- 48v输入PoL转换的增强dcr损耗降低和ICF聚集的多相多径混合SC降压变换器
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-25 DOI: 10.1109/TCSII.2026.3696403
Huihua Li;Qiaobo Ma;Jiahao Shi;Sung-Wan Hong;Yang Jiang;Rui P. Martins;Pui-In Mak
{"title":"A Multi-Phase Multi-Path Hybrid SC Buck Converter With Enhanced DCR-Loss Reduction and Alleviated ICF Gathering for 9-48 V-Input PoL Conversions","authors":"Huihua Li;Qiaobo Ma;Jiahao Shi;Sung-Wan Hong;Yang Jiang;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2026.3696403","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3696403","url":null,"abstract":"This article presents a multi-phase multi-path hybrid switched-capacitor (SC) buck converter for 9-48 V-input point-of-load applications. The proposed topology uses interleaved SC cells operating at a higher frequency than the high-voltage stage, resulting in phase-balanced capacitor charge/discharge, thereby mitigating the effects of SC current gathering. In addition, the multi-phase operation decouples the high-voltage-stress power cells from high-current-conduction paths, reducing the inductor current under high-step-down conversions. Fabricated in a 180-nm SOI process with 5.7mm<sup>2</sup>, the proposed converter achieves a measured peak efficiency of 88.3% and a current density of 176 A/cm<sup>3</sup> over an input range of 9-48 V and an output of 0.8-1.2 V, using only 11.35 mm<sup>3</sup> in passive volume.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"678-682"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced Sensorless Control Accuracy for PMSM Using Finite-Time Adaptive Observer and Parallel PLL 利用有限时间自适应观测器和并联锁相环提高永磁同步电机无传感器控制精度
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2025-09-29 DOI: 10.1109/TCSII.2025.3615400
Jia Fu;Yongting Deng;Wenjie Li;Haiyang Cao;He Wang;Yuxin Kang;Xiufeng Liu;Gaolin Wang
{"title":"Enhanced Sensorless Control Accuracy for PMSM Using Finite-Time Adaptive Observer and Parallel PLL","authors":"Jia Fu;Yongting Deng;Wenjie Li;Haiyang Cao;He Wang;Yuxin Kang;Xiufeng Liu;Gaolin Wang","doi":"10.1109/TCSII.2025.3615400","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3615400","url":null,"abstract":"This brief proposes a sensorless control scheme for the permanent magnet synchronous motor (PMSM), which is based on a finite-time adaptive state observer (FTASO) combined with a parallel phase-locked loop (PPLL). In this scheme, an adaptive gain mechanism, a nonlinear compensation term, and the characteristics of the finite-time state observer are integrated to enhance the estimation accuracy and achieve finite-time convergence of the back electromotive force (EMF). Based on the EMF estimated in the initial phase, a parallel PLL is designed to effectively reduce the angle error induced by speed variations during acceleration and deceleration. Finally, the effectiveness of the proposed sensorless control scheme is validated through simulation comparison with the conventional algorithms.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"703-707"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Emulated Peak Current Mode Control DC–DC Converter With Automatic Inductor Compensation for High Step-Down Operation 具有自动电感补偿的模拟峰值电流模式控制DC-DC变换器的高降压运行
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-15 DOI: 10.1109/TCSII.2026.3693878
Minkwang Ji;Jihun Oh;Jiho Jung;Joongho Choi
{"title":"An Emulated Peak Current Mode Control DC–DC Converter With Automatic Inductor Compensation for High Step-Down Operation","authors":"Minkwang Ji;Jihun Oh;Jiho Jung;Joongho Choi","doi":"10.1109/TCSII.2026.3693878","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3693878","url":null,"abstract":"This brief presents a robust emulated peak current mode (EPCM) buck converter with automatic inductor compensation for high step-down applications. While EPCM control effectively addresses the noise susceptibility and minimum on-time limitations of conventional peak current mode control, it suffers from stability degradation due to slope mismatch under inductance variations. To address this, the proposed architecture utilizes a switched-capacitor slope detector and a digital feedback loop to automatically synchronize the emulated slope with the actual inductor current. Measurement results from the 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD prototype verify that the loop maintains stability with decreased inductance and recovers transient speed with increased inductance, demonstrating that the proposed loop ensures optimal loop dynamics across a wide range of operating conditions.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"753-757"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current-Sensor Fault-Tolerant Control for PMSM Drives via Offset-Free Phase Extended Generalized Integrator 基于无偏置相位扩展广义积分器的PMSM驱动电流传感器容错控制
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-27 DOI: 10.1109/TCSII.2026.3697500
Zifeng Chen;Ruiqi Xu;Xijian Lin;Shun Cai;Dianxun Xiao
{"title":"Current-Sensor Fault-Tolerant Control for PMSM Drives via Offset-Free Phase Extended Generalized Integrator","authors":"Zifeng Chen;Ruiqi Xu;Xijian Lin;Shun Cai;Dianxun Xiao","doi":"10.1109/TCSII.2026.3697500","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3697500","url":null,"abstract":"Conventional current sensor fault-tolerant control methods in Permanent Magnet Synchronous Motor (PMSM) drive systems face dual challenges: measurement drift due to current sampling errors and complex nonlinear observer structures. These issues result in inaccurate phase current reconstruction and ambiguous stability characteristics under faulty conditions. This brief proposes an offset-free fault-tolerant control strategy using a single-phase current sensor based on the Offset-free Phase Extended Generalized Integrator (OPEGI) to address these issues. By employing the OPEGI algorithm to reconstruct three-phase currents, the core innovations of this brief include: 1) achieving current reconstruction in the <italic>abc</i> axis during current sensor signal loss faults and remedying the stability defects of conventional schemes; 2) real-time suppression of offset errors in current measurement, enhancing the accuracy of current signal measurement. The effectiveness of this method has been validated through experiments conducted on a three-phase 4 kW PMSM setup.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"713-717"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1280 × 1024 SWIR DROIC With Self-Correcting Phase-Coded TDC-Interpolated Single-Slope ADC 带有自校正相位编码tdc插值单斜率ADC的1280 × 1024 SWIR DROIC
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-06-02 DOI: 10.1109/TCSII.2026.3699387
Xuefei Du;Fei Zhou;Yuze Niu;Zhaofeng Huang;Qingjiang Xia;Hangyu Lu;Wengao Lu;Yi Zhuo;Yacong Zhang;Zhongjian Chen
{"title":"A 1280 × 1024 SWIR DROIC With Self-Correcting Phase-Coded TDC-Interpolated Single-Slope ADC","authors":"Xuefei Du;Fei Zhou;Yuze Niu;Zhaofeng Huang;Qingjiang Xia;Hangyu Lu;Wengao Lu;Yi Zhuo;Yacong Zhang;Zhongjian Chen","doi":"10.1109/TCSII.2026.3699387","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3699387","url":null,"abstract":"This brief presents a <inline-formula> <tex-math>$1280times 1024$ </tex-math></inline-formula> pixel-array, <inline-formula> <tex-math>$10~boldsymbol {mu }$ </tex-math></inline-formula>m-pitch digital readout integrated circuit (DROIC), fabricated in a 180-nm CMOS process and hybrid-integrated with an InGaAs sensor array for megapixel-level short-wave infrared (SWIR) imaging. The DROIC employs a column-parallel analog-to-digital converter (ADC) architecture, in which a 2-bit time-to-digital converter (TDC) is incorporated into a 12-bit single-slope (SS) ADC to quantize the residual signal. A chip-shared multiphase clock generator scheme is adopted to provide uniform phase references with small area and low power overhead. To address coarse-fine stitching errors caused by chip-shared multiphase clock distribution, a self-correcting phase-coded stitching scheme is proposed. The proposed self-correcting phase-coded stitching scheme mitigates SNR degradation and improves column-to-column uniformity by suppressing jump code errors. The hybrid-integrated SWIR focal-plane array (FPA) achieves an array-averaged SNR of 83.44 dB and a random noise of <inline-formula> <tex-math>$4.2~boldsymbol {mathrm {e^{-}_{rms}}}$ </tex-math></inline-formula>, while the measured dark fixed-pattern noise (FPN) is 0.11%. The FPA consumes 408 mW at a frame rate of 60 Hz, achieving a power efficiency of 427.16 fJ/LSB. These results demonstrate excellent noise performance, low FPN, and high energy efficiency for megapixel-level SWIR imaging.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"693-697"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12–18-GHz High-Linearity 7-bit GaN Digital Step Attenuator Using Segmented Topology and RF-Digital Co-Design 基于分段拓扑和RF-Digital协同设计的12 - 18ghz高线性7位GaN数字阶跃衰减器
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-15 DOI: 10.1109/TCSII.2026.3693911
Tong Li;Yang Li;Yahao Wang;Wenbo Guo;Wensheng Pan;Yuetian Zhou;Shihai Shao
{"title":"A 12–18-GHz High-Linearity 7-bit GaN Digital Step Attenuator Using Segmented Topology and RF-Digital Co-Design","authors":"Tong Li;Yang Li;Yahao Wang;Wenbo Guo;Wensheng Pan;Yuetian Zhou;Shihai Shao","doi":"10.1109/TCSII.2026.3693911","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3693911","url":null,"abstract":"This brief presents a 12-18 GHz 7-bit digital step attenuator (DSA) in a 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m gallium nitride (GaN) process. To overcome the severe physical trade-offs among high-power survivability, wideband precision, and switching agility, a segmented topology synthesis and an RF-digital co-design methodology are proposed. Rather than merely cascading uniform cells, tailored compensation networks neutralize bit-specific dominant parasitics, tightly suppressing RMS amplitude and phase errors below 0.23 dB and 4.8° over a 31.75 dB tuning range. Furthermore, a fully integrated active logic driver explicitly addresses the severe <inline-formula> <tex-math>$RC$ </tex-math></inline-formula> gate delay bottleneck. Delivering an exceptional IP1dB of 31.5 dBm concurrently with an ultra-fast 10 ns settling time, this work quantitatively bridges the historical gap between extreme power capacity and dynamic switching speed, establishing a highly competitive component-level advance for Ku-band active phased arrays.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"673-677"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Relaxed Switching Average-Event-Triggered Sliding Mode Control of Cyber-Physical Photovoltaic Microgrid Under False Data Injection Attacks 假数据注入攻击下网络物理光伏微电网的松弛切换平均事件触发滑模控制
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2025-11-03 DOI: 10.1109/TCSII.2025.3627976
Shen Yan;Xinyu Hu;Zehao Dou
{"title":"Relaxed Switching Average-Event-Triggered Sliding Mode Control of Cyber-Physical Photovoltaic Microgrid Under False Data Injection Attacks","authors":"Shen Yan;Xinyu Hu;Zehao Dou","doi":"10.1109/TCSII.2025.3627976","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3627976","url":null,"abstract":"This brief concerns the observer-based sliding mode control issue of cyber-physical photovoltaic microgrid subject to false data injection attacks. To optimize communication efficiency, a novel relaxed switching average-event-triggered protocol is proposed, offering two key advancements. First, by incorporating average historical information, the protocol mitigates unnecessary triggering events caused by data jitter, while a Jensen inequality-based relaxed triggering condition extends the inter-event interval. Second, a waiting period mechanism is embedded to inherently exclude Zeno behavior, eliminating the need for complex theoretical proofs. An attack-resilient sliding mode controller is designed using observed state, and a switched distributed delay system is presented to describe the event-triggered sliding mode control system. Several novel criteria are deduced to figure out the controller, observer and triggering gains to assure the system exponential stability. At last, comparative simulations validate the presented strategy.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"708-712"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact Piecewise-Linear Circuit Unit for Efficient Multi-Wing Attractor Generation 一种高效多翼吸引子生成的紧凑型分段线性电路单元
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-11 DOI: 10.1109/TCSII.2026.3692362
Yi Lian;Chunbiao Li;Wangyu Liu;Guanrong Chen
{"title":"A Compact Piecewise-Linear Circuit Unit for Efficient Multi-Wing Attractor Generation","authors":"Yi Lian;Chunbiao Li;Wangyu Liu;Guanrong Chen","doi":"10.1109/TCSII.2026.3692362","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3692362","url":null,"abstract":"This work presents a novel compact analog circuit unit for implementing piecewise-linear functions. With an integrated ICs-based modular expandable architecture, the circuit unit allows flexible configuration of breakpoints in the piecewise-linear function with external voltages, thereby achieving high precision and scalability. Since dynamics editing can be conveniently applied to reconstruct attractors, this unit is particularly useful for constructing multi-wing attractors. Using the editing function, multi-dimensional multi-wing attractors of the diffusionless Lorenz system are reconstructed and realized. Experiments demonstrate the efficiency of cell attractor selection and multi-wing organization. By adjusting the threshold voltages of the module, any number of multi-wing attractors in different dimensions can be obtained. This circuit unit can be readily applied to the construction of multi-wing/multi-scroll attractors, offering a valuable analog circuit schematic for chaotic signal generation and chaos-based secure communication.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"728-732"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Tile-Based Feature Map Compression Method for Multi-Stride Winograd Algorithm 多步Winograd算法中基于tile的特征映射压缩方法
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-03-15 DOI: 10.1109/TCSII.2026.3693787
Ge Li;Yishuo Meng;Siwei Xiang;Jianfei Wang;Li Geng;Chen Yang
{"title":"A Tile-Based Feature Map Compression Method for Multi-Stride Winograd Algorithm","authors":"Ge Li;Yishuo Meng;Siwei Xiang;Jianfei Wang;Li Geng;Chen Yang","doi":"10.1109/TCSII.2026.3693787","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3693787","url":null,"abstract":"In this brief, a Tile-based Feature map Compression Method (TFCM) was proposed to accelerate both convolutions with filter (3,2) (i.e., filter size is 3 and stride is 2) and (3,1) by using Winograd. Furthermore, the feasibility of TFCM was also discussed based on some popular CNNs. In addition, a Winograd-based Acceleration Unit (WAU) was designed to implement TFCM. The evaluation results show that our proposed methods can achieve 45.93%~75.28% multiplication savings when applied to VGG16, MobileNetV1. Moreover, our accelerator can accomplish 1.71 TOPS while deploying VGG16, achieving a <inline-formula> <tex-math>$1.27times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> improvement in DSP efficiency per MHz compared with the state-of-the-art accelerators.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"718-722"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information IEEE电路与系统汇刊——II：快报简报出版信息
IF 4.6 2区 工程技术
IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2026-07-01 Epub Date: 2026-06-24 DOI: 10.1109/TCSII.2026.3703153
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2026.3703153","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3703153","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"C2-C2"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11578121","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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