IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第4页

A Fractional Momentum Enhanced Fractional Filter for the Memristor-Based Volume Controller 基于忆阻器的体积控制器分数阶动量增强分数阶滤波器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-17 DOI: 10.1109/TCSII.2025.3589991

Xuetao Xie;Yi-Fei Pu;Jian Wang

引用次数: 0

Contrastive Learning-Based Dual Autoencoder for Anomaly Detection in Loader Gearboxes 基于对比学习的双自编码器在装载机变速箱异常检测中的应用

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-17 DOI: 10.1109/TCSII.2025.3590139

Ruonan Lu;Da Zheng;Chengyuan Zhu;Weiwei Cao;Qinmin Yang

{"title":"Contrastive Learning-Based Dual Autoencoder for Anomaly Detection in Loader Gearboxes","authors":"Ruonan Lu;Da Zheng;Chengyuan Zhu;Weiwei Cao;Qinmin Yang","doi":"10.1109/TCSII.2025.3590139","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590139","url":null,"abstract":"Anomaly detection (AD) of gearboxes is essential for ensuring the operational safety and reliability of the loader. However, identifying anomalies in non-stationary signals remains challenging as anomalies often emerge within the normal fluctuation, especially when normal and abnormal samples exhibit high similarity. This brief proposes a contrastive learning-based dual autoencoder (AE) AD method for loader gearboxes. Specifically, the continuous wavelet transform is employed to capture dynamic characteristics of non-stationary signals. A compound scaling network is then designed into the unified encoder to extract complex features while maintaining a lightweight architecture. Subsequently, a sparse representation channel is integrated into the second AE framework, complementing the basis for contrastive mechanisms and promoting the learning of consistency across normal samples with the reconstruction channel. By minimizing the contrastive loss between two samples from different channels, the model learns the inherent consistency of normal samples. Finally, the contrastive loss of the second AE and the reconstruction error of the first AE serve as indicators for detecting abnormalities. Experimental results on real-world loader gearbox data demonstrate that the proposed method achieves a high fault detection rate, a low false alarm rate, and robust reliability, validating its effectiveness.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1223-1227"},"PeriodicalIF":4.9,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Swing- and Gain-Enhanced Mirrored Dynamic Amplifier 摆幅增益增强镜像动态放大器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-17 DOI: 10.1109/TCSII.2025.3590144

Ali Rezapour;Omid Shoaei

{"title":"A Swing- and Gain-Enhanced Mirrored Dynamic Amplifier","authors":"Ali Rezapour;Omid Shoaei","doi":"10.1109/TCSII.2025.3590144","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590144","url":null,"abstract":"This brief presents a Mirrored Dynamic Amplifier (MDA) to enhance the swing and gain of prior art dynamic amplifiers (DAs). Instead of compensating the charge loss in the load capacitors due to the common-mode current, this technique resolves the dependency between common-mode and differential-mode currents. The differential and regulated common-mode currents are mirrored to the output branch for integration on the load capacitors. Furthermore, the output branch is made of only one transistor, which makes the proposed architecture to benefit from large output swing. An output swing of 1.272Vppdiff can be achieved with a supply voltage of 1.2V. In addition, a pre-discharge linearization technique is presented to compensate for nonlinearity induced by the current regulation mechanism, that results in an average improvement of 6 dB in THD. The proposed DA is designed and verified in a 65nm CMOS process. Post-layout simulation results show that gains of <inline-formula> <tex-math>$16times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$32times $ </tex-math></inline-formula> can be achieved, along with output swings of 640 mVppdiff and 800 mVppdiff, respectively, while maintaining THDs better than −62 dB. A noise analysis and a detailed comparison of the proposed MDA with a few state-of-the-art designs are also elaborated.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1158-1162"},"PeriodicalIF":4.9,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Energy-Efficient CPU–FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2 基于Minimap2的第三代基因组测序高效CPU-FPGA异构加速系统

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-15 DOI: 10.1109/TCSII.2025.3588409

Jialei Sun;Lingyi Liu;Kunyue Li;Shuaipeng Li;Sai Gao;Zizheng Dong;Jianfei Jiang;Fangzhen Wu

{"title":"An Energy-Efficient CPU–FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2","authors":"Jialei Sun;Lingyi Liu;Kunyue Li;Shuaipeng Li;Sai Gao;Zizheng Dong;Jianfei Jiang;Fangzhen Wu","doi":"10.1109/TCSII.2025.3588409","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3588409","url":null,"abstract":"Minimap2 has become a widely used software for third-generation long-read genomic sequencing. Due to the increasing complexity of data processing with long-read sequences, the analysis is computationally intensive and energy-consuming. This brief presents an end-to-end CPU-FPGA heterogeneous acceleration system for Minimap2 focusing on chaining operation, in which multi-threaded software is on the CPU, and a multi-kernel accelerator for chaining operation is on the FPGA. This brief can hold the high thread number of modern CPUs to maximize performance and energy efficiency. Hardware-efficient kernel design, software-hardware co-optimization, and memory access fusion techniques have been applied to achieve higher computational performance with less power consumption. This brief achieves at most <inline-formula> <tex-math>$2.01times $ </tex-math></inline-formula> acceleration against software and <inline-formula> <tex-math>$1.65times $ </tex-math></inline-formula> against the baseline, and EDP reduction of 72% against software and 59% against the baseline, outperforming state-of-the-art designs. The code of our acceleration system is available on GitHub, together with FPGA bitstream.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1278-1282"},"PeriodicalIF":4.9,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 8.1 dB SNRMIN, 17.8 pJ/Conv-Step, Code-Domain Noise Suppression Baseband Scheme for Ultra-Low-Power Receiver 一种8.1 dB信噪比、17.8 pJ/反阶跃、超低功耗接收机码域噪声抑制基带方案

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-15 DOI: 10.1109/TCSII.2025.3588918

Jianhang Yang;Rong Zhou;Hongjian Lan;Zhen Li;Xianlong Xiong;Bowen Wang;Zhangming Zhu

{"title":"An 8.1 dB SNRMIN, 17.8 pJ/Conv-Step, Code-Domain Noise Suppression Baseband Scheme for Ultra-Low-Power Receiver","authors":"Jianhang Yang;Rong Zhou;Hongjian Lan;Zhen Li;Xianlong Xiong;Bowen Wang;Zhangming Zhu","doi":"10.1109/TCSII.2025.3588918","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3588918","url":null,"abstract":"This brief investigates the minimum signal-to-noise-ratio requirement (<inline-formula> <tex-math>${SNR} {_{text {MIN}}}$ </tex-math></inline-formula>) for reliable baseband decoding as a function of code length and oversampling rate. Based on this analysis, we propose a baseband processing scheme for code-domain noise suppression that leverages a level-crossing ADC (LC-ADC) front end. Compared with conventional comparator-based architectures, the proposed design significantly reduces the <inline-formula> <tex-math>${SNR} {_{text {MIN}}}$ </tex-math></inline-formula>, thereby improving receiver sensitivity. A prototype circuit was fabricated in a 65 nm CMOS process to validate the proposed approach. Measurement results at 100 bps with a 10-bit wake-up code demonstrate an <inline-formula> <tex-math>${SNR} {_{text {MIN}}}$ </tex-math></inline-formula> of only 8.1 dB and an energy efficiency of 17.8 pJ per conversion step. Beyond ultra-low-power radios, this proposed technique is applicable to a broad range of low-power, weak-signal detection systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1153-1157"},"PeriodicalIF":4.9,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2-MHz BW 64.5-dB SNDR 0.45-1.05 GHz Direct IF/RF Digitization Subsampling Bandpass DSM Utilizing a Capacitive-Stacking N-Path Filter 基于电容堆叠n路滤波器的2 mhz BW 64.5 db SNDR 0.45-1.05 GHz直接中频/射频数字化子采样带通DSM

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587662

Xiao Wang;Runkun Li;Xin Sun;Kong-Pang Pun

{"title":"A 2-MHz BW 64.5-dB SNDR 0.45-1.05 GHz Direct IF/RF Digitization Subsampling Bandpass DSM Utilizing a Capacitive-Stacking N-Path Filter","authors":"Xiao Wang;Runkun Li;Xin Sun;Kong-Pang Pun","doi":"10.1109/TCSII.2025.3587662","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587662","url":null,"abstract":"This brief presents a novel subsampling bandpass Delta-Sigma modulator (BPDSM) based on transconductor (Gm) - N-path filters (NPF) for direct radio-frequency (RF) / intermediate-frequency (IF) digitization. The proposed architecture introduces two key innovations. First, a subsampling technique is applied that places the input center frequency at <inline-formula> <tex-math>$(3/4) f_{S}$ </tex-math></inline-formula> (versus conventional <inline-formula> <tex-math>$f_{S}/4$ </tex-math></inline-formula> operation), where <inline-formula> <tex-math>$f_{S}$ </tex-math></inline-formula> is the sampling frequency. Second, a capacitive-stacking NPF that provides 6-dB passive gain is utilized for: (1) suppressing the amplifier’s thermal noise when referred to the modulator’s input; (2) improving the quantization noise shaping by eliminating redundant notches at even multiples of <inline-formula> <tex-math>$f_{S}/4$ </tex-math></inline-formula> in the modulator’s noise transfer function. Fabricated in 65-nm CMOS, the modulator prototype occupies 0.11 mm2 and achieves 0.45 - 1.05 GHz tunability, the highest upper frequency reported for Gm-NPF BPDSMs to the best of the authors’ knowledge. When clocked at 800-MHz, it demonstrates a 64.5-dB peak SNDR over 2-MHz bandwidth centered at 601-MHz, consuming 0.37 mW from a 1.2-V supply. The design records state-of-the-art figure of merit (FoM) values of 161.8 dB Schreier’s FoM and 67.4 fJ/conversion-step Walden’s FoM for BPDSMs operating above 450 MHz.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1138-1142"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 26.5–29.5 GHz Doherty Phased-Array Transceiver Front-End With 7-Bit Phase Shifter and 16% Back-Off Drain Efficiency 26.5-29.5 GHz Doherty相控阵收发前端，7位移相器和16%回退漏极效率

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587850

Shaogang Wang;Huiyan Gao;Hang Lu;Yiwei Liu;Nayu Li;Chunyi Song;Zhiwei Xu

引用次数: 0

A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors 用于超大像素阵列CMOS图像传感器的高速双反馈环路列缓冲器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587906

Liu Suiyang;Guo Zhongjie;Xu Ruiming;Yu Ningmei

{"title":"A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors","authors":"Liu Suiyang;Guo Zhongjie;Xu Ruiming;Yu Ningmei","doi":"10.1109/TCSII.2025.3587906","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3587906","url":null,"abstract":"With the development of stitching processes, the resolution of CMOS image sensors has significantly improved, especially in applications such as earth observation and deep space exploration. Although the column-parallel, row-serial readout has numerous advantages and is considered the ideal sensor architecture, it still has frame rate issues caused by the long length of the serial output bus, which leads to large parasitic parameters of the metal lines. Therefore, this brief proposes a dual feedback loop column buffer that implements parallel-serial conversion while introducing the switching on-resistance within the loop to reduce the settling time of the output signal and stabilize the phase margin. A chip containing <inline-formula> <tex-math>$12288{times }12288$ </tex-math></inline-formula> pixels was fabricated using CMOS 55nm 1P4M technology. With a 48-channel output, the chip achieves a frame rate of 10.36 fps. Compared to the single feedback loop column buffer, the risetime of the output signal is reduced by 23.4%, the falltime by 21.9%, and the overall frame rate is improved by 29.6%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1143-1147"},"PeriodicalIF":4.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs 一个位级双计数器，支持低功耗高带宽vco - adc

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-10 DOI: 10.1109/TCSII.2025.3587495

Simon Ooghe;Brendan Saux;Tobias Cromheecke;Johan Raman;Pieter Rombouts

引用次数: 0

An I/Q Imbalance Calibration Scheme for 5G Direct-Conversion Transmitter 一种5G直接转换发射机I/Q不平衡校正方案

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-08 DOI: 10.1109/TCSII.2025.3586873

Seunghoon Lee;Sungbeom Kim;Donghun Lee;Inho Choi;Ho-Jin Song

引用次数: 0