IEEE Transactions on Circuits and Systems II: Express Briefs最新文献

{"title":"A Fully Integrated Dual-Phase Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting With High Power Extraction Enhancement","authors":"Honglei Xu;Yuzhou Mao;Quan Sun;Yanzhao Ma","doi":"10.1109/TCSII.2026.3691068","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3691068","url":null,"abstract":"This brief presents a fully integrated dual-phase switched-capacitor (DPSC) rectifier for piezoelectric energy harvesting (PEH). An on-chip reconfigurable switched-capacitor (SC) converter is implemented to eliminate the need for external inductors and capacitors, significantly reducing the overall system volume. The efficiency is enhanced by reusing the inherent capacitance (<inline-formula> <tex-math>$C_{text {p}}$ </tex-math></inline-formula>) of the transducer as a flying capacitor of the SC converter through a dual-phase charge transfer technique. Furthermore, an all-digital flipping control scheme is employed to minimize system power consumption. The proposed circuit was fabricated in a <inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>m BCD process. The measurement results show that a 76% flipping efficiency and a <inline-formula> <tex-math>$6.7times $ </tex-math></inline-formula> energy extraction enhancement are achieved.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"743-747"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2026.3703155","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3703155","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"C3-C3"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11589489","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Untrimmed Cryogenic Voltage Reference Based on Saturation-to-Linear Transition Achieving 60.3-ppm/K TC and 0.56% Inaccuracy","authors":"Sungbin Park;Youngwoo Ji;Jae-Yoon Sim","doi":"10.1109/TCSII.2026.3696631","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3696631","url":null,"abstract":"This brief presents a cryogenic voltage reference (VR) employing a saturation-to-linear transition scheme and a 1/<inline-formula> <tex-math>$mu C_{mathrm {ox}}$ </tex-math></inline-formula>-based proportional-to-absolute-temperature (PTAT) generation. Unlike conventional diode-connected architectures that restrict the core transistor to a single operating region, the proposed design independently controls the drain-to-source voltage (<inline-formula> <tex-math>$V_{mathrm {DS}}$ </tex-math></inline-formula>) via feedback, enabling temperature-dependent region transition near 100 K. The saturation-mode square law suppresses strong device nonlinearity below ~100 K, while linear-region operation above ~100 K provides inherent linearity. Fabricated in 180-nm CMOS, 15 untrimmed chips achieve mean temperature coefficients (TCs) of 60.3 ppm/K in the wide-range mode (5.2–300 K) and 105.8 ppm/K in the cryogenic-range mode (5.2–100 K), with <inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> of 0.56% and 0.52%, respectively, configured by an on-chip (<inline-formula> <tex-math>$n$ </tex-math></inline-formula>, <inline-formula> <tex-math>$R$ </tex-math></inline-formula>) selection. At 5.2 K, the VR achieves 0.073%/V line regulation, a power-supply rejection ratio (PSRR) of −56.3 dB at 100 Hz, and integrated noise of <inline-formula> <tex-math>$23.6~mu $ </tex-math></inline-formula>V_rms (1–10 Hz), while consuming <inline-formula> <tex-math>$15.2~mu $ </tex-math></inline-formula>W in an active area of 0.063 mm².","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"683-687"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact 3~13-GHz Injection-Locked-and-PI-Based Quadrature Clock Generator With 28.9-fs Jitter and 1120 μm2 Core Area","authors":"Ruixi Yu;Qiyuan Liu;Li Wang;Zunsong Yang;Yunbo Huang;Xuan Guo;Xiaoyu Shan;Kai Cheng;Hongyu Ren;Bo Li","doi":"10.1109/TCSII.2026.3692823","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3692823","url":null,"abstract":"This work presents a compact quadrature clock generator (QCG) for wireline transceivers, with a core area of <inline-formula> <tex-math>$1120~mu $ </tex-math></inline-formula>m². The design achieves a quadrature error of less than 0.7° across a frequency range of 3 to 13 GHz, delivering integrated jitter of 28.9 fs at 13 GHz. It employs a two-stage coarse-fine architecture: the coarse stage consists of an injection-locked ring oscillator with interdigitated cross-coupled pairs to isolate the output from the injection nodes. This configuration enables a relatively accurate initial quadrature relation, low power consumption, and a correct duty cycle over a wide frequency range. The fine stage incorporates an integration-mode phase interpolator, effectively correcting the quadrature relationship through I/Q phase blending. An inverter-based closed-loop biasing circuit regulates the output DC level within the saturation region, ensuring linear phase blending. The complete QCG consumes less than 7.0 mW across the frequency range.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"668-672"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quadrilateral Discontinuous Current Modulation to Enhance Light Load Efficiency for FSBB Converters","authors":"Wei Huang;Caifeng Liu;Shiying Zhou;Yang Zhang;Xudong Zou;Yong Kang","doi":"10.1109/TCSII.2026.3683546","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3683546","url":null,"abstract":"This brief proposes a quadrilateral discontinuous current modulation (QDCM) method for four-switch buck-boost (FSBB) converters, effectively mitigating the inherent light-load efficiency degradation in conventional quadrilateral current modulation (QCM). The proposed QDCM achieves full-range zero voltage switching (ZVS) or zero current switching (ZCS) operation and reduces the inductor RMS current by 54.1% at 10% load. Its efficiency enhancement mechanism has been rigorously validated via resonance modeling and loss analysis. Experimental results from a 250 W prototype demonstrate a peak efficiency of 98.2%, superior to conventional QCM.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"738-742"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Harmonic-Based Simultaneous Wireless Power and Data Transfer Method Using Improved DPPM","authors":"Bo Liang;Zhaoyong Mao;Peizhou Liu;Bo Cheng;Shengzhao Pang;Zhengchao Yan;Yayu Ma;Jiale Wang;Yiming Zhang","doi":"10.1109/TCSII.2026.3693085","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3693085","url":null,"abstract":"This brief proposes a Simultaneous Wireless Power and Data Transfer (SWPDT) method utilizing the third-harmonic component of a phase-shift modulated inverter for downlink communication. By dynamically adjusting the phase-shift angle, data is modulated via improved Differential Pulse Position Modulation (DPPM). A secondary-side harmonic isolation network is designed to suppres harmonic currents in the load. Theoretical analysis validates the load-independent nature of the transmission. Experimental results demonstrate a 310.45 W power transfer with 91.05% peak efficiency and a 36.3 kbps data rate.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"748-752"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Band-Limited Digital Predistortion Based on Iterative Learning Control With Input Signal Reconstruction for Wideband RFPAs","authors":"Wenhua Zhao;Gaoming Xu;Jinghao Chen;Jun Hua;Taijun Liu;Fadhel M. Ghannouchi","doi":"10.1109/TCSII.2026.3699941","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3699941","url":null,"abstract":"To address the analog-to-digital converter (ADC) sampling rate bottleneck in wideband, a novel band-limited (BL) digital predistortion (DPD) method based on iterative learning control (ILC) with input signal reconstruction (ISR) is proposed. Unlike conventional approaches, this method updates the BL input signal in the BL domain and subsequently reconstructs the full band input using a forward model. Notably, the regression matrix of the forward model is consistently constructed from the original baseband signal, thereby ensuring numerical stability throughout the iterative process. Experimental results demonstrate that the proposed ISR-ILC strategy outperforms existing algorithms. Moreover, under a relaxed oversampling rate, it achieves superior linearization performance while significantly reducing computational complexity.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"763-767"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 24–32 GHz CMOS Power Amplifier Linearized With Source-Degeneration Inductance Control and 2nd-/4th-Order Harmonic Trap","authors":"Gyuha Lee;Songcheol Hong","doi":"10.1109/TCSII.2026.3691945","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3691945","url":null,"abstract":"A two-stage wideband linear power amplifier (PA) using a 40-<bold>n</b>m CMOS process is presented. It is proposed that the source-degeneration inductance (SDI) of the common source power stage is adaptively controlled to provide a high linearity. This reduces gain and phase distortions with the output power. In addition, a harmonic trap (HT) circuit is also introduced at the driver stage output to suppress the 2nd-/4th-order harmonics simultaneously. Due to source-degeneration inductor in the power stage and a RC feedback in the driver stage, the overall PA achieves a 6.9 GHz gain 3-dB bandwidth (BW). Owing to a wideband output power matching, it achieves OP<inline-formula> <tex-math>${}_{textbf {1dB}}~1$ </tex-math></inline-formula>-dB BW of 8 GHz, while maintaining OP<inline-formula> <tex-math>${}_{textbf {1dB}}$ </tex-math></inline-formula> above 17.1-dBm from 24 to 32 GHz. With a 5G New Radio (NR) 64-quadrature amplitude modulation (QAM) 400-MHz modulated signal (9.66-dB PAPR), it achieves average output powers of 12.5/11.7/12/12.4 dBm with power-added efficiencies (PAEs) of 14.4/12.8/13.9/14.9% at 25/27/29/31 GHz, respectively, while satisfying an error vector magnitude (EVM) less than -25 dB. The core size is <inline-formula> <tex-math>$0.135~textbf {m}$ </tex-math></inline-formula>m<inline-formula> <tex-math>${}^{textbf {2}}$ </tex-math></inline-formula>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"698-702"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Distance-Encoding Spiking Sensory Neuron Based on Optimized NbO2 Memristor","authors":"Jiapei Liu;Bin Yan;Peipei Jin;Guangyi Wang;Long Chen","doi":"10.1109/TCSII.2026.3696044","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3696044","url":null,"abstract":"NbO₂ threshold-switch memristors exhibit S-shaped negative differential resistance (S-NDR) and relaxation dynamics, making them attractive building blocks for compact spiking neurons. However, widely used moving-boundary electro-thermal models (e.g., the Pickett benchmark) are numerically stiff and computationally expensive, limiting circuit-level design-space exploration and neuromorphic sensing simulations. This brief presents a physics-constrained lumped electro-thermal compact model for NbO₂ locally active memristors (LAMs), termed the Optimized NbO₂ LAM. The model replaces the moving boundary with a single lumped temperature state and a smooth phase mapping while preserving key switching invariants (<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$V_{hold}$ </tex-math></inline-formula>) that define the locally active S-NDR window. When embedded in a Pearson–Anson RC oscillator, the proposed model reproduces quasi-static <inline-formula> <tex-math>$V$ </tex-math></inline-formula>–<inline-formula> <tex-math>$I$ </tex-math></inline-formula> characteristics and relaxation oscillations consistent with the Pickett benchmark, while achieving a median <inline-formula> <tex-math>$sim 3.92times $ </tex-math></inline-formula> simulation speedup. We demonstrate a distance-encoding spiking sensory neuron in which a light detection and ranging (LiDAR)-inspired input-amplitude proxy monotonically modulates the output spike frequency. A field-programmable gate array (FPGA) register-transfer level (RTL) implementation, verified via Vivado XSim functional simulation, confirms a mean frequency error of 0.90% over the 15-point FPGA validation range relative to a discrete Optimized NbO₂ LAM reference. A PySpice transient cross-check further validates the waveform fidelity of the Optimized NbO₂ LAM against a Python ODE solver. A dynamic distance-tracking experiment additionally provides temporal evidence for spike-based distance perception (RMSE <inline-formula> <tex-math>$approx 6.9{,}mathrm {cm}$ </tex-math></inline-formula>), indicating feasibility for edge spiking neural network (SNN) interfaces.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 7","pages":"733-737"},"PeriodicalIF":4.6,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3.5-ppm/°C High-Precision Current Reference for 4–20-mA Transmitters Based on On-Chip Temperature Sensor","authors":"Meng Li;Yue Qu;Mingxi Liu;Bin Liu;Jian Ren","doi":"10.1109/TCSII.2026.3690485","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3690485","url":null,"abstract":"This brief presents a high-precision, low-temperature-drift on-chip temperature sensor-based current reference (OCTS-CR) for loop-powered 4-20 mA transmitters. The architecture innovatively leverages an integrated on-chip temperature sensor to achieve a profound synergy between real-time thermal data and the “time-for-precision” design strategy. By mapping resistance characteristics from the spatial domain into the time domain, the system utilizes temperature sensor monitoring data to drive a 16-bit <inline-formula> <tex-math>$Sigma $ </tex-math></inline-formula>-<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> DAC to generate pulse density modulation (PDM) signals. This enables quasi-continuous adjustment of equivalent resistance, which effectively neutralizes temperature fluctuations while circumventing the parasitic effects and area constraints inherent in traditional resistor arrays. Additionally, a robust dual-stage calibration mechanism combining offline parameter pre-loading with sensor-based online digital compensation is implemented to enhance compensation resolution. Fabricated in a <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS process with a core area of 0.144 mm², experimental results from -40°C to +125°C demonstrate that the <inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>A primary current yields an average temperature coefficient (TC) of 3.5 ppm/°C with a relative standard deviation (RSD) under 0.05%, achieving a state-of-the-art precision level. Simultaneously, the system provides a proportional replica current source of <inline-formula> <tex-math>$32~mu $ </tex-math></inline-formula>A featuring a TC of 29.3 ppm/°C and an RSD below 0.3% for versatile application requirements.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 6","pages":"618-622"},"PeriodicalIF":4.9,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148059701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}