IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第5页

An Ultra-Compact Ka-Band Folded Phased-Array Transceiver Front-End With Bidirectional 20-dB Gain Control 具有双向20db增益控制的超紧凑ka波段折叠相控阵收发器前端

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-08 DOI: 10.1109/TCSII.2025.3586977

Shiwei Wu;Dongfang Pan;Laifu Jin;Lin Cheng

引用次数: 0

An Energy-Efficient Image Deblurring Accelerator With Quad-Base-Quad-Scale Quantized Format and Layer Normalization-Aware Optimization 基于四基四尺度量化格式和层归一化感知优化的节能图像去模糊加速器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-07 DOI: 10.1109/TCSII.2025.3586657

Jinhoon Jo;Jueun Jung;Kyuho Jason Lee

{"title":"An Energy-Efficient Image Deblurring Accelerator With Quad-Base-Quad-Scale Quantized Format and Layer Normalization-Aware Optimization","authors":"Jinhoon Jo;Jueun Jung;Kyuho Jason Lee","doi":"10.1109/TCSII.2025.3586657","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3586657","url":null,"abstract":"This brief proposes a novel data-format-based image deblurring accelerator with layer normalization and UNet architecture optimization for mobile cameras. As the demand for photography in dynamic environments continues to grow and the limitations of physical stabilization are tightening, post-processing methods to restore sharp images have gained increasing attention, notably deblurring methods based on convolutional neural networks. However, their heavy computational cost hinders their integration into mobile computing platforms. The proposed accelerator enables energy-efficient acceleration of deblurring through the following three key features: 1) A Quad-base-Quad-scale Quantized format that maintains image quality with only 8-bit, reducing external memory access (EMA) by 33% and achieving 75.7% higher multiply-and-accumulation (MAC) energy efficiency compared to conventional 12-bit precision; 2) A Layer Normalization-Aware Optimization technique, enabling parallel normalization and fusion of affine transformation; 3) A dual-stationary systolic array architecture that selects the optimal dataflow for each UNet block based on processing element (PE) utilization. As a result, the proposed accelerator achieves 2.49 TOPS/W, which is <inline-formula> <tex-math>$2.23times $ </tex-math></inline-formula> higher than prior work, enabling energy-efficient deblurring for mobile applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1273-1277"},"PeriodicalIF":4.9,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead ZRHDC：一个轻量级的HDC架构，零ROM开销

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-04 DOI: 10.1109/TCSII.2025.3585931

Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao

{"title":"ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead","authors":"Baoying Yu;Xiaoqin Wang;Dingyi Wang;Qiang Li;Shushan Qiao","doi":"10.1109/TCSII.2025.3585931","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585931","url":null,"abstract":"Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2-<inline-formula> <tex-math>$8 times $ </tex-math></inline-formula> dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3-<inline-formula> <tex-math>$6 times $ </tex-math></inline-formula> area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1263-1267"},"PeriodicalIF":4.9,"publicationDate":"2025-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Chaotic Nature of Integer Sequences From Primitive Linear Feedback Shift Registers 原始线性反馈移位寄存器中整数序列的混沌性质

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-04 DOI: 10.1109/TCSII.2025.3585913

Hyojeong Choi;Gangsan Kim;Hong-Yeop Song;Hongjun Noh

引用次数: 0

High-Throughput Pseudo-Random Number Generators Over Discrete Chaos 离散混沌上的高吞吐量伪随机数发生器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-03 DOI: 10.1109/TCSII.2025.3585809

Carlos E. C. Souza;Davi Moreno;Matheus H. S. Sousa;Daniel P. B. Chaves;Cecilio Pimentel

引用次数: 0

A 36 mJ/Inf Convolution Accelerator With Reduced Memory Access and Regrouped Sparse Kernels for Environment Sound Classification on Edge Devices 基于减少内存访问和稀疏核重组的36mj /Inf卷积加速器在边缘设备上的环境声音分类

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-03 DOI: 10.1109/TCSII.2025.3585516

Lichen Feng;Tao Wang;Rundong Cai;Feng Min;Zhangming Zhu

引用次数: 0

A Switchable Sub-3GHz/Sub-6GHz LNA With 0.4-1.1dB NF Using Triple-Feedback and Tunable Inter-Stage Matching Strategies 基于三反馈和可调级间匹配策略的0.4-1.1dB可切换Sub-3GHz/Sub-6GHz LNA

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3585444

Zhihao Zhang;Xiaolin Zhou;Jiehai Zhou;Zhixia Du;Gary Zhang

{"title":"A Switchable Sub-3GHz/Sub-6GHz LNA With 0.4-1.1dB NF Using Triple-Feedback and Tunable Inter-Stage Matching Strategies","authors":"Zhihao Zhang;Xiaolin Zhou;Jiehai Zhou;Zhixia Du;Gary Zhang","doi":"10.1109/TCSII.2025.3585444","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585444","url":null,"abstract":"A broadband switchable low noise amplifier (LNA), supporting Sub-3GHz and Sub-6GHz modes for a wide range of wireless communication applications, is proposed. To achieve broadband simultaneous noise and impedance matching, a triple-feedback technique combined with a strategically designed inter-stage matching network (ISMN), is analyzed and developed. The dual-mode switchable functionality, offering wideband flat gain performance, is enabled through a switch-based tunable capacitor configuration within the ISMN with adjustable load impedance. Additionally, a current-reuse amplification topology is employed to enhance both gain and linearity while reducing power consumption. Fabricated using 250nm GaAs pHEMT technology, the proposed switchable LNA achieves gain of 21.7-24.2/18.7-21.7dB, noise figure (NF) of 0.4-0.96/0.65-1.1dB, output 1-dB compression point of 15.7-19.7/14.2-19.4dBm, and output third-order intercept point of 25.6-35.1/25.4-34dBm in Mode 1 (0.6-3.5GHz) and Mode 2 (0.6-5.5GHz), respectively. In comparison to Mode 1, the LNA operating in Mode 2 extends the 3-dB gain bandwidth by an additional 2GHz, at the cost of a 3 dB reduction in average gain, an increase of 0.15–0.25dB in NF, and a slight degradation in linearity.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1128-1132"},"PeriodicalIF":4.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Area-Efficient Modular Multiplication on FPGA 基于FPGA的面积高效模块化乘法

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3585441

Yujun Xie;Yuan Liu

引用次数: 0

Development of a Hybrid Fractional-Order Fuzzy-PID Controller Applied to a DC-DC Buck Converter 应用于DC-DC降压变换器的分数阶模糊pid混合控制器的研制

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3585464

Michel W. de S. Campos;Edmilson M. Prado;Renan L. P. De Medeiros;Maurício P. Fantesia;Werbeston D. De Oliveira;Venicio C. Conceição;Iago V. Correa;Ozenir F. da R. Dias;Florindo A. de C. Ayres Júnior

{"title":"Development of a Hybrid Fractional-Order Fuzzy-PID Controller Applied to a DC-DC Buck Converter","authors":"Michel W. de S. Campos;Edmilson M. Prado;Renan L. P. De Medeiros;Maurício P. Fantesia;Werbeston D. De Oliveira;Venicio C. Conceição;Iago V. Correa;Ozenir F. da R. Dias;Florindo A. de C. Ayres Júnior","doi":"10.1109/TCSII.2025.3585464","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3585464","url":null,"abstract":"This brief focuses on developing a hybrid fractional-order PID (FOPID) controller enhanced with fuzzy logic to regulate the output voltage of a DC-DC Buck converter. The FOPID controller extends traditional PID control by offering improved robustness and more flexible tuning criteria. The controller’s gains are dynamically adjusted using fuzzy logic, enhancing performance across varying operating conditions. The project involved mathematical modeling of the Buck converter and approximating fractional-order operators to integer-order equivalents. Frequency domain analysis was performed using computational tools, including MATLAB, Simulink, and LTspice, to design and simulate the control system. A physical Buck converter was assembled to validate the controller’s experimental performance. The system’s non-linearities were characterized to optimize the hybrid controller, and the best tuning parameters were identified for three distinct operating regions. The experimental results were compared with simulation data, demonstrating the hybrid controller’s enhanced performance in closed-loop operation. The study concludes that the proposed approach outperforms conventional tuning methods, showcasing its potential for advanced industrial control systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1218-1222"},"PeriodicalIF":4.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Benders-Combined Safe Reinforcement Learning Framework for Risk-Averse Dispatch Considering Frequency Security Constraints 考虑频率安全约束的风险规避调度的benders组合安全强化学习框架

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-02 DOI: 10.1109/TCSII.2025.3584894

Jianbing Feng;Zhouyang Ren;Chen Li;Wenyuan Li

引用次数: 0