IEEE Transactions on Circuits and Systems II: Express Briefs最新文献_第5页

A Novel Voltage-Sensorless Grid Voltage Full Feedforward Estimator-Based Current Control Strategy for a Grid-Connected Inverter 一种新的无电压传感器并网逆变器电压全前馈估计电流控制策略

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-21 DOI: 10.1109/TCSII.2025.3590699

Qifan Wang;Qiangsong Zhao;Yuanqing Xia

引用次数: 0

Data-Driven Near-Optimal Reduced Tracking Control of SPSs With Application to PMSM SPSs数据驱动的近最优简化跟踪控制及其在永磁同步电机中的应用

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-21 DOI: 10.1109/TCSII.2025.3590689

Yao Xu;Chunyu Yang;Gonghe Li;Ju H. Park

引用次数: 0

A 3.9-8.2-GHz Wideband Frequency Synthesizer With an Inductive Multiplexing Output Network for SATCOM Applications 一种用于卫星通信应用的带电感复用输出网络的3.9-8.2 ghz宽带频率合成器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-18 DOI: 10.1109/TCSII.2025.3590593

Xiaofei Liao;Dixian Zhao;Chenyu Xu;Hao Gong;Wendi Chen;Xiaohu You

{"title":"A 3.9-8.2-GHz Wideband Frequency Synthesizer With an Inductive Multiplexing Output Network for SATCOM Applications","authors":"Xiaofei Liao;Dixian Zhao;Chenyu Xu;Hao Gong;Wendi Chen;Xiaohu You","doi":"10.1109/TCSII.2025.3590593","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590593","url":null,"abstract":"This brief presents a wideband frequency synthesizer with 3.9 to 8.2 GHz continuous frequency coverage for satellite communication applications. The core fractional-N phase locked loop utilizes four LC-VCOs achieving a 4.3 GHz tuning range with a 50-MHz reference frequency. The frequency mapping of the four VCOs, along with module-level parameter optimization, is performed to maintain a stable figure of merit and minimize loop jitter across the entire tuning range. A high-isolation low-loss inductive multiplexing output technique is proposed, which uses only one active buffer to drive both the internal loop and the external load, significantly reducing power consumption. Moreover, an on-chip active loop filter is implemented, reducing the capacitance area by 80% and enhancing chip integration. Fabricated in a 65-nm CMOS technology, the frequency synthesizer occupies a chip area of 2.28 mm2 while consumes power of 25–33.5 mW. The phase noise reaches –123.72 dBc/Hz and –116.31 dBc/Hz at 1-MHz offset under 3.9- and 8.2-GHz carriers, respectively. Measured reference and fractional spurs remain below –65 and –55 dBc.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1163-1167"},"PeriodicalIF":4.9,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms 一种用于注意力机制的特征级稀疏的CAM-SRAM混合内存处理架构

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-18 DOI: 10.1109/TCSII.2025.3590432

Haiqiu Huang;Mingyu Wang;Xiaojie Li;Baiqing Zhong;Zeqi Yang;Tao Lu;Yicong Zhang;Zhiyi Yu

{"title":"A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms","authors":"Haiqiu Huang;Mingyu Wang;Xiaojie Li;Baiqing Zhong;Zeqi Yang;Tao Lu;Yicong Zhang;Zhiyi Yu","doi":"10.1109/TCSII.2025.3590432","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590432","url":null,"abstract":"The attention mechanism has become increasingly popular due to its ability to capture complex dependencies, enabling models like transformers to achieve remarkable performance in large language models (LLMs), computer vision, and other domains. However, the mechanism faces challenges such as low arithmetic intensity, leading to frequent data movement, and long sequence lengths, which introduce a large amount of redundant information. To mitigate both data movement and computational overhead in attention mechanisms, we propose a hybrid CAM-SRAM processing-in-memory architecture. By leveraging the parallel search and sort capabilities of content-addressable memory (CAM) arrays, we achieve dynamic fine-grained sparsification on features with varying variance, reducing the number of multiply-accumulate (MAC) operations in the matrix multiplication (MatMul). Furthermore, an approximate booth encoding is employed in our MAC unit to reduce the number of partial products and maintain the consistency of their signs. This eliminates the need for negation operations, simplifying the logic design. Experimental results show that, in different configurations, our feature-level sparsification scheme achieves over 80% sparsity with an acceptable accuracy drop. With sparsity up to 80%, our design achieves a performance of 0.252-1.26 TOPS and a power efficiency of 4.71-21.72 TOPS/W, operating at 1000 MHz on the TSMC 40nm process.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1283-1287"},"PeriodicalIF":4.9,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Fractional Momentum Enhanced Fractional Filter for the Memristor-Based Volume Controller 基于忆阻器的体积控制器分数阶动量增强分数阶滤波器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-17 DOI: 10.1109/TCSII.2025.3589991

Xuetao Xie;Yi-Fei Pu;Jian Wang

引用次数: 0

Contrastive Learning-Based Dual Autoencoder for Anomaly Detection in Loader Gearboxes 基于对比学习的双自编码器在装载机变速箱异常检测中的应用

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-17 DOI: 10.1109/TCSII.2025.3590139

Ruonan Lu;Da Zheng;Chengyuan Zhu;Weiwei Cao;Qinmin Yang

{"title":"Contrastive Learning-Based Dual Autoencoder for Anomaly Detection in Loader Gearboxes","authors":"Ruonan Lu;Da Zheng;Chengyuan Zhu;Weiwei Cao;Qinmin Yang","doi":"10.1109/TCSII.2025.3590139","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590139","url":null,"abstract":"Anomaly detection (AD) of gearboxes is essential for ensuring the operational safety and reliability of the loader. However, identifying anomalies in non-stationary signals remains challenging as anomalies often emerge within the normal fluctuation, especially when normal and abnormal samples exhibit high similarity. This brief proposes a contrastive learning-based dual autoencoder (AE) AD method for loader gearboxes. Specifically, the continuous wavelet transform is employed to capture dynamic characteristics of non-stationary signals. A compound scaling network is then designed into the unified encoder to extract complex features while maintaining a lightweight architecture. Subsequently, a sparse representation channel is integrated into the second AE framework, complementing the basis for contrastive mechanisms and promoting the learning of consistency across normal samples with the reconstruction channel. By minimizing the contrastive loss between two samples from different channels, the model learns the inherent consistency of normal samples. Finally, the contrastive loss of the second AE and the reconstruction error of the first AE serve as indicators for detecting abnormalities. Experimental results on real-world loader gearbox data demonstrate that the proposed method achieves a high fault detection rate, a low false alarm rate, and robust reliability, validating its effectiveness.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1223-1227"},"PeriodicalIF":4.9,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Swing- and Gain-Enhanced Mirrored Dynamic Amplifier 摆幅增益增强镜像动态放大器

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-17 DOI: 10.1109/TCSII.2025.3590144

Ali Rezapour;Omid Shoaei

{"title":"A Swing- and Gain-Enhanced Mirrored Dynamic Amplifier","authors":"Ali Rezapour;Omid Shoaei","doi":"10.1109/TCSII.2025.3590144","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3590144","url":null,"abstract":"This brief presents a Mirrored Dynamic Amplifier (MDA) to enhance the swing and gain of prior art dynamic amplifiers (DAs). Instead of compensating the charge loss in the load capacitors due to the common-mode current, this technique resolves the dependency between common-mode and differential-mode currents. The differential and regulated common-mode currents are mirrored to the output branch for integration on the load capacitors. Furthermore, the output branch is made of only one transistor, which makes the proposed architecture to benefit from large output swing. An output swing of 1.272Vppdiff can be achieved with a supply voltage of 1.2V. In addition, a pre-discharge linearization technique is presented to compensate for nonlinearity induced by the current regulation mechanism, that results in an average improvement of 6 dB in THD. The proposed DA is designed and verified in a 65nm CMOS process. Post-layout simulation results show that gains of <inline-formula> <tex-math>$16times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$32times $ </tex-math></inline-formula> can be achieved, along with output swings of 640 mVppdiff and 800 mVppdiff, respectively, while maintaining THDs better than −62 dB. A noise analysis and a detailed comparison of the proposed MDA with a few state-of-the-art designs are also elaborated.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1158-1162"},"PeriodicalIF":4.9,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Wideband Frequency-Independent IQ Calibration Scheme With 3-GHz-UGB Amplifiers 基于3ghz - ugb放大器的宽带频率无关IQ校准方案

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-16 DOI: 10.1109/TCSII.2025.3589886

Yunyou Pu;Wei Li;Qiaoan Li;Xingyu Ma;Hongtao Xu

引用次数: 0

An Energy-Efficient CPU–FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2 基于Minimap2的第三代基因组测序高效CPU-FPGA异构加速系统

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-15 DOI: 10.1109/TCSII.2025.3588409

Jialei Sun;Lingyi Liu;Kunyue Li;Shuaipeng Li;Sai Gao;Zizheng Dong;Jianfei Jiang;Fangzhen Wu

{"title":"An Energy-Efficient CPU–FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2","authors":"Jialei Sun;Lingyi Liu;Kunyue Li;Shuaipeng Li;Sai Gao;Zizheng Dong;Jianfei Jiang;Fangzhen Wu","doi":"10.1109/TCSII.2025.3588409","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3588409","url":null,"abstract":"Minimap2 has become a widely used software for third-generation long-read genomic sequencing. Due to the increasing complexity of data processing with long-read sequences, the analysis is computationally intensive and energy-consuming. This brief presents an end-to-end CPU-FPGA heterogeneous acceleration system for Minimap2 focusing on chaining operation, in which multi-threaded software is on the CPU, and a multi-kernel accelerator for chaining operation is on the FPGA. This brief can hold the high thread number of modern CPUs to maximize performance and energy efficiency. Hardware-efficient kernel design, software-hardware co-optimization, and memory access fusion techniques have been applied to achieve higher computational performance with less power consumption. This brief achieves at most <inline-formula> <tex-math>$2.01times $ </tex-math></inline-formula> acceleration against software and <inline-formula> <tex-math>$1.65times $ </tex-math></inline-formula> against the baseline, and EDP reduction of 72% against software and 59% against the baseline, outperforming state-of-the-art designs. The code of our acceleration system is available on GitHub, together with FPGA bitstream.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1278-1282"},"PeriodicalIF":4.9,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 8.1 dB SNRMIN, 17.8 pJ/Conv-Step, Code-Domain Noise Suppression Baseband Scheme for Ultra-Low-Power Receiver 一种8.1 dB信噪比、17.8 pJ/反阶跃、超低功耗接收机码域噪声抑制基带方案

IF 4.9 2区工程技术

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-15 DOI: 10.1109/TCSII.2025.3588918

Jianhang Yang;Rong Zhou;Hongjian Lan;Zhen Li;Xianlong Xiong;Bowen Wang;Zhangming Zhu

{"title":"An 8.1 dB SNRMIN, 17.8 pJ/Conv-Step, Code-Domain Noise Suppression Baseband Scheme for Ultra-Low-Power Receiver","authors":"Jianhang Yang;Rong Zhou;Hongjian Lan;Zhen Li;Xianlong Xiong;Bowen Wang;Zhangming Zhu","doi":"10.1109/TCSII.2025.3588918","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3588918","url":null,"abstract":"This brief investigates the minimum signal-to-noise-ratio requirement (<inline-formula> <tex-math>${SNR} {_{text {MIN}}}$ </tex-math></inline-formula>) for reliable baseband decoding as a function of code length and oversampling rate. Based on this analysis, we propose a baseband processing scheme for code-domain noise suppression that leverages a level-crossing ADC (LC-ADC) front end. Compared with conventional comparator-based architectures, the proposed design significantly reduces the <inline-formula> <tex-math>${SNR} {_{text {MIN}}}$ </tex-math></inline-formula>, thereby improving receiver sensitivity. A prototype circuit was fabricated in a 65 nm CMOS process to validate the proposed approach. Measurement results at 100 bps with a 10-bit wake-up code demonstrate an <inline-formula> <tex-math>${SNR} {_{text {MIN}}}$ </tex-math></inline-formula> of only 8.1 dB and an energy efficiency of 17.8 pJ per conversion step. Beyond ultra-low-power radios, this proposed technique is applicable to a broad range of low-power, weak-signal detection systems.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1153-1157"},"PeriodicalIF":4.9,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0