一种用于卫星通信应用的带电感复用输出网络的3.9-8.2 ghz宽带频率合成器

IF 4.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Xiaofei Liao;Dixian Zhao;Chenyu Xu;Hao Gong;Wendi Chen;Xiaohu You
{"title":"一种用于卫星通信应用的带电感复用输出网络的3.9-8.2 ghz宽带频率合成器","authors":"Xiaofei Liao;Dixian Zhao;Chenyu Xu;Hao Gong;Wendi Chen;Xiaohu You","doi":"10.1109/TCSII.2025.3590593","DOIUrl":null,"url":null,"abstract":"This brief presents a wideband frequency synthesizer with 3.9 to 8.2 GHz continuous frequency coverage for satellite communication applications. The core fractional-N phase locked loop utilizes four LC-VCOs achieving a 4.3 GHz tuning range with a 50-MHz reference frequency. The frequency mapping of the four VCOs, along with module-level parameter optimization, is performed to maintain a stable figure of merit and minimize loop jitter across the entire tuning range. A high-isolation low-loss inductive multiplexing output technique is proposed, which uses only one active buffer to drive both the internal loop and the external load, significantly reducing power consumption. Moreover, an on-chip active loop filter is implemented, reducing the capacitance area by 80% and enhancing chip integration. Fabricated in a 65-nm CMOS technology, the frequency synthesizer occupies a chip area of 2.28 mm2 while consumes power of 25–33.5 mW. The phase noise reaches –123.72 dBc/Hz and –116.31 dBc/Hz at 1-MHz offset under 3.9- and 8.2-GHz carriers, respectively. Measured reference and fractional spurs remain below –65 and –55 dBc.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 9","pages":"1163-1167"},"PeriodicalIF":4.9000,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 3.9-8.2-GHz Wideband Frequency Synthesizer With an Inductive Multiplexing Output Network for SATCOM Applications\",\"authors\":\"Xiaofei Liao;Dixian Zhao;Chenyu Xu;Hao Gong;Wendi Chen;Xiaohu You\",\"doi\":\"10.1109/TCSII.2025.3590593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents a wideband frequency synthesizer with 3.9 to 8.2 GHz continuous frequency coverage for satellite communication applications. The core fractional-N phase locked loop utilizes four LC-VCOs achieving a 4.3 GHz tuning range with a 50-MHz reference frequency. The frequency mapping of the four VCOs, along with module-level parameter optimization, is performed to maintain a stable figure of merit and minimize loop jitter across the entire tuning range. A high-isolation low-loss inductive multiplexing output technique is proposed, which uses only one active buffer to drive both the internal loop and the external load, significantly reducing power consumption. Moreover, an on-chip active loop filter is implemented, reducing the capacitance area by 80% and enhancing chip integration. Fabricated in a 65-nm CMOS technology, the frequency synthesizer occupies a chip area of 2.28 mm2 while consumes power of 25–33.5 mW. The phase noise reaches –123.72 dBc/Hz and –116.31 dBc/Hz at 1-MHz offset under 3.9- and 8.2-GHz carriers, respectively. Measured reference and fractional spurs remain below –65 and –55 dBc.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 9\",\"pages\":\"1163-1167\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11084881/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11084881/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本文介绍了一种用于卫星通信应用的具有3.9至8.2 GHz连续频率覆盖的宽带频率合成器。核心分数n锁相环利用4个lc - vco实现4.3 GHz调谐范围,参考频率为50 mhz。执行四个vco的频率映射以及模块级参数优化,以保持稳定的性能值,并在整个调谐范围内最大限度地减少环路抖动。提出了一种高隔离低损耗的电感复用输出技术,该技术仅使用一个有源缓冲器同时驱动内环和外部负载,从而显著降低了功耗。此外,还实现了片上有源环路滤波器,使电容面积减少了80%,提高了芯片集成度。频率合成器采用65纳米CMOS技术制造,芯片面积为2.28 mm2,功耗为25-33.5 mW。在3.9 ghz和8.2 ghz载波下,相位噪声在1 mhz偏移时分别达到- 123.72 dBc/Hz和- 116.31 dBc/Hz。测量的参考杂散和分数杂散保持在-65和-55 dBc以下。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 3.9-8.2-GHz Wideband Frequency Synthesizer With an Inductive Multiplexing Output Network for SATCOM Applications
This brief presents a wideband frequency synthesizer with 3.9 to 8.2 GHz continuous frequency coverage for satellite communication applications. The core fractional-N phase locked loop utilizes four LC-VCOs achieving a 4.3 GHz tuning range with a 50-MHz reference frequency. The frequency mapping of the four VCOs, along with module-level parameter optimization, is performed to maintain a stable figure of merit and minimize loop jitter across the entire tuning range. A high-isolation low-loss inductive multiplexing output technique is proposed, which uses only one active buffer to drive both the internal loop and the external load, significantly reducing power consumption. Moreover, an on-chip active loop filter is implemented, reducing the capacitance area by 80% and enhancing chip integration. Fabricated in a 65-nm CMOS technology, the frequency synthesizer occupies a chip area of 2.28 mm2 while consumes power of 25–33.5 mW. The phase noise reaches –123.72 dBc/Hz and –116.31 dBc/Hz at 1-MHz offset under 3.9- and 8.2-GHz carriers, respectively. Measured reference and fractional spurs remain below –65 and –55 dBc.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程:电子与电气
CiteScore
7.90
自引率
20.50%
发文量
883
审稿时长
3.0 months
期刊介绍: TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信