A Calibration-Free 12-Bit 1.5-GS/s Pipelined ADC With Merged Sub-ADC Quantization Technique

IF 4.9 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2025-07-24 DOI:10.1109/TCSII.2025.3592475

Chun-Tse Su;Chao-Yen Hsu;Tai-Cheng Lee

引用次数: 0

Abstract

This brief presents a calibration-free 12-bit 1.5-GS/s pipelined ADC employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique can extend the amplification time, thereby relaxing the design of the inner-stage residue amplifier. A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figure of merits (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively.

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采用合并子ADC量化技术的免校准12位1.5-GS/s流水线ADC

本文介绍了一种采用合并子ADC量化（MSAQ）技术的免校准12位1.5 gs /s流水线ADC。在传统流水线ADC架构的基础上，该技术可以延长放大时间，从而简化了内级残留放大器的设计。采用28纳米CMOS技术实现的原型ADC在Nyquist输入下的SFDR为70.52 dB， SNDR为58.03 dB，而来自1 v电源的功耗为18.5 mW。它产生164.1 dB和18.9 fJ/conv的Schreier和Walden优点系数（FoM）。一步一步,分别。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程：电子与电气

CiteScore

7.90

自引率

20.50%

发文量

883

审稿时长

3.0 months

期刊介绍： TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.