{"title":"A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis","authors":"Bram Veraverbeke;Filip Tavernier","doi":"10.1109/TCSII.2025.3596708","DOIUrl":null,"url":null,"abstract":"Dopant freeze-out severely increases the bulk resistance of cryogenic bulk CMOS transistors by up to <inline-formula> <tex-math>$10{^{{6}}} {\\times }$ </tex-math></inline-formula> at 4.2K compared to room temperature. This brief describes, for the first time in the literature, how this increased bulk resistance introduces a memory effect in the latch of dynamic comparators, which leads to hysteresis. To measure this hysteresis reliably in the presence of noise, a statistical characterization procedure is developed. For a 40nm bulk CMOS strongARM comparator with an input-referred noise voltage of 348<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula> VRMS, a hysteresis voltage >898<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula> V is measured at 6K, substantially deteriorating the precision. Therefore, this brief introduces a triple tail comparator with capacitive over-neutralization to increase the preamplification gain, suppressing the hysteresis ><inline-formula> <tex-math>$6{\\times }$ </tex-math></inline-formula> to only 141<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula> V.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1358-1362"},"PeriodicalIF":4.9000,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11119638/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Dopant freeze-out severely increases the bulk resistance of cryogenic bulk CMOS transistors by up to $10{^{{6}}} {\times }$ at 4.2K compared to room temperature. This brief describes, for the first time in the literature, how this increased bulk resistance introduces a memory effect in the latch of dynamic comparators, which leads to hysteresis. To measure this hysteresis reliably in the presence of noise, a statistical characterization procedure is developed. For a 40nm bulk CMOS strongARM comparator with an input-referred noise voltage of 348$\mu $ VRMS, a hysteresis voltage >898$\mu $ V is measured at 6K, substantially deteriorating the precision. Therefore, this brief introduces a triple tail comparator with capacitive over-neutralization to increase the preamplification gain, suppressing the hysteresis >$6{\times }$ to only 141$\mu $ V.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.