ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead

Abstract

Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2- $8 \times $ dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3- $6 \times $ area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.