A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs

Abstract

In this brief, a counter structure which facilitates the design of a coarse-fine voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) at high bandwidths is presented. A key challenge is the asynchrony between the coarse and fine counters for which it is quantitatively proven that effective ambiguity resolution is necessary to obtain a sufficient performance. To achieve this, a latch-based, bit-level redundant coarse counter featuring fast ambiguity resolution and operating at high VCO frequencies is presented. Using this novel counter structure a power-efficient VCO-ADC with a core area of 0.007 mm2 and a post-layout simulated figure-of-merit of 168 dB at a bandwidth of 100 MHz is demonstrated.