A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors

Abstract

With the development of stitching processes, the resolution of CMOS image sensors has significantly improved, especially in applications such as earth observation and deep space exploration. Although the column-parallel, row-serial readout has numerous advantages and is considered the ideal sensor architecture, it still has frame rate issues caused by the long length of the serial output bus, which leads to large parasitic parameters of the metal lines. Therefore, this brief proposes a dual feedback loop column buffer that implements parallel-serial conversion while introducing the switching on-resistance within the loop to reduce the settling time of the output signal and stabilize the phase margin. A chip containing $12288{\times }12288$ pixels was fabricated using CMOS 55nm 1P4M technology. With a 48-channel output, the chip achieves a frame rate of 10.36 fps. Compared to the single feedback loop column buffer, the risetime of the output signal is reduced by 23.4%, the falltime by 21.9%, and the overall frame rate is improved by 29.6%.