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A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 194.6-TOPS/W流水全电流域混合信号的28纳米CMOS内存计算
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-28 DOI: 10.1109/LSSC.2026.3697990
Saideep Cherukuri;N. V. Kidambi;W. C. Wang;I. Chakraborty;S. Zhang;L. Shamieh;J. B. Steinberg;S. Mukhopadhyay
{"title":"A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS","authors":"Saideep Cherukuri;N. V. Kidambi;W. C. Wang;I. Chakraborty;S. Zhang;L. Shamieh;J. B. Steinberg;S. Mukhopadhyay","doi":"10.1109/LSSC.2026.3697990","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3697990","url":null,"abstract":"Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A <inline-formula> <tex-math>$256{,}times {,}256$ </tex-math></inline-formula> SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS peak throughput, 194.59-TOPS/W compute efficiency, 40.46-TOPS/mm2 density, and maintains RMSE of 4.3% at 300 MHz and 5.6% at 620 MHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"174-177"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology 采用灵活的A - igzo TFT技术集成曼彻斯特编码器的6位串行器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-06-25 DOI: 10.1109/LSSC.2026.3707465
Suyash Shrivastava;Pydi Ganga Bahubalindruni
{"title":"A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology","authors":"Suyash Shrivastava;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2026.3707465","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3707465","url":null,"abstract":"This article presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with a Manchester encoder. The system comprises an on-chip digital logic block that generates six mutually nonoverlapping control signals (<inline-formula> <tex-math>$phi _{0-5}$ </tex-math></inline-formula>) and three 120° phase-shifted clock signals to drive the switching transistors in the serializer and the Manchester encoder (MCE), respectively. This system was fabricated on a 27-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick flexible polyimide substrate using an NMOS-only, single-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) technology. From measurements, the system has shown a reliable functionality up to a clock frequency of 2 MHz with a power dissipation of 750 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W at a supply voltage (V<inline-formula> <tex-math>${}_{DD}$ </tex-math></inline-formula>) of 2 V. This system’s active area is 6.16 mm2. To validate the proposed system functionality in biomedical applications of practical importance, it was deployed at the output of a 6-bit charge-sharing analog-to-digital converter (CS-ADC), which was also fabricated on the same flexible foil under the same conditions. Here, the digital output of the CS-ADC has been serialized and encoded with the proposed system, where an ECG signal is an input to the SAR-ADC. The encoded outputs from the serializer were further postprocessed in MATLAB to recover the original signal, validating the system’s functionality. This work serves as a proof-of-concept for a fully integrated, compact, and low-power data interface suitable for flexible health-monitoring systems in wearable applications.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"194-197"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148491625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology 基于0.18 μm CMOS技术的1.1 nj /转换rc放电电阻传感器，误差为±0.65% (3σ) 1点
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-25 DOI: 10.1109/LSSC.2026.3677301
Mu Wu;Yihang Cheng;Xingli Cui;Sining Pan;Huaqiang Wu
{"title":"A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology","authors":"Mu Wu;Yihang Cheng;Xingli Cui;Sining Pan;Huaqiang Wu","doi":"10.1109/LSSC.2026.3677301","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3677301","url":null,"abstract":"This letter presents an energy-efficient RC discharge-based sensor readout circuit for sub-kilo-ohm resistance measurements. An SAR logic is implemented to adjust the DAC capacitor array to equalize the RC time constants of the resistance-sensing and DAC branches, thereby eliminating the high static current required to bias the small sensing resistor. To further reduce power consumption, the sensing branch with a large discharging capacitor is triggered only once per conversion. Fabricated in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology, the sensor achieves a competitive energy efficiency of 1.1 nJ/conversion and a fast conversion time of <inline-formula> <tex-math>$2.4~mu $ </tex-math></inline-formula>s. With the auto-zeroing (AZ) technique, it achieves a <inline-formula> <tex-math>$3sigma $ </tex-math></inline-formula> inaccuracy of ±0.65% after 1-point calibration over a resistance range from 150 to <inline-formula> <tex-math>$250~Omega $ </tex-math></inline-formula>.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"109-112"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator 一个实时多领域多任务扩展现实感知加速器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-12 DOI: 10.1109/LSSC.2026.3673168
Kathleen Feng;Kai Bartolone;Kartik Prabhu;Brianna McColm;Xingyu Ni;Siddhant Gupta;Priyanka Raina
{"title":"Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator","authors":"Kathleen Feng;Kai Bartolone;Kartik Prabhu;Brianna McColm;Xingyu Ni;Siddhant Gupta;Priyanka Raina","doi":"10.1109/LSSC.2026.3673168","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3673168","url":null,"abstract":"Birch is a system-on-chip (SoC) that efficiently and accurately accelerates the multi-task multi-domain extended reality (XR) perception pipeline, with workloads such as visual inertial odometry (VIO), eye gaze tracking, and scene understanding. Birch features vision modules with cascaded line buffers, in-step feature sorting, and double-buffered optical flow to extract and track quality features for VIO, a configurable matrix unit and vector unit for acceleration of deep neural network (DNN)-based tasks like eye gaze tracking and scene understanding, and reuse of the DNN vector unit for acceleration of matrix multiplications in VIO to save area in small-form-factor XR devices. Birch extracts and tracks features in 7.14 ms and 2.29 mJ/frame. For DNNs, Birch runs ResNet-18 at 109 frames/s and eye gaze extraction at 985 frames/s, <inline-formula> <tex-math>$3.5times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.6times $ </tex-math></inline-formula> faster than prior work, respectively. ResNet-50 also runs in real time at 46.5 frames/s.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"121-124"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset 基于550 μ w电容辅助变压器的压控振荡器在1mhz频偏下实现204 dbc /Hz FoMA
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-06 DOI: 10.1109/LSSC.2026.3690818
Teng-Shen Yang;Liang-Hung Lu
{"title":"A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset","authors":"Teng-Shen Yang;Liang-Hung Lu","doi":"10.1109/LSSC.2026.3690818","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3690818","url":null,"abstract":"This letter presents a capacitor-assisted transformer (CTF)-based voltage-controlled oscillator (VCO) that achieves a low flicker-noise corner with submilliwatt power consumption and compact chip area. By introducing a small assisting capacitor into the transformer, the higher order tank impedance is reshaped from the second-resonance region toward the third-resonance region, resulting in a more symmetric effective impulse sensitivity function (ISF) and hence reduced flicker-noise upconversion without incurring extra area overhead. Fabricated in a 90-nm CMOS process, the proposed VCO operates from 6.5 to 7.63 GHz while consuming 0.55 mW. Measurements show a minimum flicker-noise corner of 270 kHz and a phase noise of −131.3 dBc/Hz at 10-MHz offset. The core occupies 0.025 mm2, achieving a peak area-normalized figure of merit (FoM<inline-formula> <tex-math>${}_{A}$ </tex-math></inline-formula>) of 204.3 dBc/Hz at 1-MHz offset.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"150-153"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147937552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications 具有集成直接转换混频器功率检测器的CMOS LNA，用于低功耗物联网无线电应用
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-21 DOI: 10.1109/LSSC.2026.3725828
Yunfan Gao;Minghan Liu;Mengting Yan;Cristian Cassella;Miriam Leeser;Marvin Onabajo
{"title":"A CMOS LNA With an Integrated Direct-Conversion Mixer-Based Power Detector for Low-Power IoT Radio Applications","authors":"Yunfan Gao;Minghan Liu;Mengting Yan;Cristian Cassella;Miriam Leeser;Marvin Onabajo","doi":"10.1109/LSSC.2026.3725828","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3725828","url":null,"abstract":"This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct downconversion mixing, which avoids a dedicated LO generator, coupler, or standalone detector path. Implemented in a 65-nm CMOS process and operated from a 1-V supply, the prototype consumes a total of <inline-formula> <tex-math>$400~mu $ </tex-math></inline-formula>W, including <inline-formula> <tex-math>$375~mu $ </tex-math></inline-formula>W for the LNA and <inline-formula> <tex-math>$25~mu $ </tex-math></inline-formula>W for the PD. Measurements show an <inline-formula> <tex-math>$S!_{21}$ </tex-math></inline-formula> of 14.5 dB, <inline-formula> <tex-math>$S!_{11}$ </tex-math></inline-formula> of −12.9 dB, noise figure of 4.5 dB, IIP3 of −7.5 dBm, and input-referred 1-dB compression point (<inline-formula> <tex-math>$P_{1mathrm {dB}}$ </tex-math></inline-formula>) of −17.5 dBm at 2.8 GHz. The embedded PD provides a monotonic output response over more than 20-dB input range while occupying only 0.012 mm2. The proposed architecture enables compact RF power sensing for adaptive low-power receivers, including interference-resilient front-ends with frequency-selective limiters (FSLs).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"258-261"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C 一种集成动态参考和无驱动器操作的零静态功率ADC，在-40°C至85°C范围内实现58.6 dB SNDR
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-26 DOI: 10.1109/LSSC.2026.3697203
Yiming Wang;Yihang Luan;Zhiliang Hong;Jiawei Xu
{"title":"A Zero-Static-Power ADC With Integrated Dynamic Reference and Driver-Free Operation Achieving 58.6 dB SNDR From –40 °C to 85 °C","authors":"Yiming Wang;Yihang Luan;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2026.3697203","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3697203","url":null,"abstract":"This letter presents a 10-bit ENOB charge-sharing SAR ADC with a fully integrated dynamic bandgap reference (BGR), enabling first-order noise shaping and ultralow-power (ULP) operation. The charge-sharing ADC and dynamic BGR form an ideal pair: both operate without static current, allowing compact integration and high precision. The SAR uses only three key capacitors: CREF, CSMP, and CINT, eliminating the conventional large DAC array and relaxing the BGR drive requirement. By retaining the residual voltage on CINT between cycles, quantization noise is shaped, and precision is further improved. The dynamic BGR combines PTAT and CTAT outputs from two PNP-based capacitive DACs, precharged to the supply voltage and discharged for an adjustable duration. Implemented in a 65-nm LP CMOS process, the proposed ADC achieves > 58.6 dB SNDR from <inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C while consuming <inline-formula> <tex-math>$5.18~mu $ </tex-math></inline-formula>W. The fully integrated dynamic BGR, as part of the ADC, achieves <10.9> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C, enabling the full ADC’s state-of-the-art energy efficiency and temperature stability.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"178-181"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EMO-CIM: An Input/Stationary-Data Similarity-Aware Computing-In-Memory Design for Variable Vector-Wise Computation in Edge Multioperator AI Acceleration EMO-CIM：边缘多算子人工智能加速中可变矢量计算的输入/静态数据相似度感知内存计算设计
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-02-27 DOI: 10.1109/LSSC.2026.3668853
Bo Wang;Yuchen Tang;Feiran Liu;Xiaoxue Zhong;Yuchen Ma;Xin Si;Jun Yang
{"title":"EMO-CIM: An Input/Stationary-Data Similarity-Aware Computing-In-Memory Design for Variable Vector-Wise Computation in Edge Multioperator AI Acceleration","authors":"Bo Wang;Yuchen Tang;Feiran Liu;Xiaoxue Zhong;Yuchen Ma;Xin Si;Jun Yang","doi":"10.1109/LSSC.2026.3668853","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3668853","url":null,"abstract":"We propose an edge multioperator computing-in-memory (EMO-CIM) design that supports variable vector-wise multiply-and-accumulate (MAC) in CNN, Depthwise (DW)-Convolution, and Attention operators. It features: 1) a single EMO-CIM bank (ECB) excels in variable vector-wise MAC (V-MAC) for multioperators; 2) merging local input-shared compute units (LISCUs) with a decode-unit and adder-tree (DUAT) facilitates input/stationary-data (SD) similarity-aware computing (SAC) to improve energy and area efficiency (EF). Based on a row-wise vector separable accumulation (RVSA) strategy, the Attention/CNN task is optimized via multivector parallel crossover computation (MVPCC), while the DW task is optimized through the partial-convolution-first (PCF) computation. EMO-CIM achieves peak energy efficiencies of 93.5 and 39.3 TOPS/W for Attention/CNN and DW tasks, respectively, and area efficiencies of 4.971 and 3.728 TOPS/mm2 for the same tasks under INT8 MAC operations.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"97-100"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148491621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Broadband Class-E Power Amplifier With Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS 110纳米CMOS谐波抑制电纳补偿负载网络宽带e类功率放大器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-18 DOI: 10.1109/LSSC.2026.3725042
Kai Yue;Yubing Li;Yujia Chen;Xiuping Li
{"title":"A Broadband Class-E Power Amplifier With Compact Harmonic Suppression Susceptance Compensation Load Network in 110-nm CMOS","authors":"Kai Yue;Yubing Li;Yujia Chen;Xiuping Li","doi":"10.1109/LSSC.2026.3725042","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3725042","url":null,"abstract":"This letter presents a compact Class-E power amplifier (PA) with broadband and enhanced harmonic suppression performance. The harmonic suppression susceptance compensation (HSSC) Class-E load network is proposed and analyzed to simultaneously achieve broadband fundamental matching and harmonic suppression. Despite its sixth-order <inline-formula> <tex-math>$LC$ </tex-math></inline-formula> complexity, the proposed HSSC Class-E load network is compactly synthesized within the footprint of a single transformer. To validate the proposed structure, an X/Ku-band Class-E PA is fabricated using a 110-nm CMOS process. Measurement results demonstrate a peak gain of 24.3 dB with a 3-dB bandwidth of 10.2–16.3 GHz (46.0%), a maximum saturated-output power (Psat) of 15.8 dBm, and a peak power-added efficiency (PAE) of 28.9% with a 1-dB bandwidth of 11.3–17.1 GHz (40.8%). The core area of the circuit is only <inline-formula> <tex-math>$870 times{,} 280~mu $ </tex-math></inline-formula>m.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"254-257"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148925100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends 并行和无线光发射机前端40gb /s 8mw - oma基于gan的1对n VCSEL驱动
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-06 DOI: 10.1109/LSSC.2026.3720689
S. Sarah Feng;Fuzhan Chen;H. Bruce Bao;R. Matthew Ma;Kangping Zhong;P. T. Alan Lau;C. Patrick Yue
{"title":"A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends","authors":"S. Sarah Feng;Fuzhan Chen;H. Bruce Bao;R. Matthew Ma;Kangping Zhong;P. T. Alan Lau;C. Patrick Yue","doi":"10.1109/LSSC.2026.3720689","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3720689","url":null,"abstract":"This letter presents a broadband, high-optical modulation amplitude (OMA) GaN-based 1-to-N VCSEL driver implemented in a 150-nm GaN HEMT process for parallel and wireless optical transmitter frontends. It further compares split-node and conventional VCSEL-driving topologies and analyzes the bandwidth scaling and inter-VCSEL timing skew of series- and parallel-connected VCSEL arrays. Leveraging the high voltage-handling and driving capability of GaN, the proposed architecture supports series-connected VCSEL arrays, thereby reducing the effective capacitive loading while increasing the aggregate optical output. With a four-series VCSEL array, the driver demonstrates 40-Gb/s NRZ transmission with approximately 8-mW total OMA and 38-Gb/s PAM-4 operation. Preliminary free-space optical (FSO) measurements further show that increasing the number of series-connected VCSELs improves the received optical signal strength and extends the transmission distance, validating the proposed driver for wireless optical links.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"242-245"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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