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IEEE Solid-State Circuits Letters最新文献

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A 15.4-ppm/°C GaN-Based Voltage Reference With Process-Variation-Immunity and High PSR for Electric Vehicle Power Systems 一种15.4 ppm/°C、过程抗扰度和高PSR的基于gan的电动汽车电源基准电压
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-02 DOI: 10.1109/LSSC.2024.3510597
Po-Jui Chiu;Chi-Yu Chen;Xiao-Quan Wu;Yu-Ting Huang;Tz-Wun Wang;Sheng-Hsi Hung;Ke-Horng Chen;Kuo-Lin Zheng;Chih-Chen Li
{"title":"A 15.4-ppm/°C GaN-Based Voltage Reference With Process-Variation-Immunity and High PSR for Electric Vehicle Power Systems","authors":"Po-Jui Chiu;Chi-Yu Chen;Xiao-Quan Wu;Yu-Ting Huang;Tz-Wun Wang;Sheng-Hsi Hung;Ke-Horng Chen;Kuo-Lin Zheng;Chih-Chen Li","doi":"10.1109/LSSC.2024.3510597","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510597","url":null,"abstract":"The proposed gallium nitride (GaN)-based voltage reference (\u0000<inline-formula> <tex-math>$V_{mathrm { REF}}$ </tex-math></inline-formula>\u0000) generator has a low temperature coefficient (TC) of 15.4 ppm/°C, small \u0000<inline-formula> <tex-math>$V_{mathrm { REF}}$ </tex-math></inline-formula>\u0000 deviation at different process corners (standard deviation of 0.22%), line sensitivity as low as 0.0023%/V, and high power supply rejection (PSR) of −187 and −114 dB at 100 Hz and 50 MHz, respectively. The proportional-to-absolute-temperature (PTAT) gate current for enhancement-mode GaN (eGaN) optimizes TC. Eliminating depletion-mode GaN (dGaN) gate leakage and using multiple stacked composite dGaNs can improve line regulation and PSR. All performance is achieved with a low power consumption of \u0000<inline-formula> <tex-math>$10.9~mu $ </tex-math></inline-formula>\u0000W.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"359-362"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 828-μW 100.9-dB SNDR 20-kHz BW Zoom-Linear-Exponential Incremental ADC With Split Positive Feedback and Duty-Cycle Amplifier 一种828 μ w、100.9 db SNDR、20 khz BW、分路正反馈和占空比放大器的变焦线性指数增量ADC
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-02 DOI: 10.1109/LSSC.2024.3510423
Lairong Fang;Shuwen Zhang;Xiaoyang Zeng;Zhiliang Hong;Jiawei Xu
{"title":"An 828-μW 100.9-dB SNDR 20-kHz BW Zoom-Linear-Exponential Incremental ADC With Split Positive Feedback and Duty-Cycle Amplifier","authors":"Lairong Fang;Shuwen Zhang;Xiaoyang Zeng;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2024.3510423","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510423","url":null,"abstract":"This letter presents a hybrid, three-step zoom-linear-exponential incremental analog-to-digital converter (ZLE-IADC) for audio applications. The zoom-SAR in the first step provides coarse signal quantization and relaxes the accuracy requirements of subsequent conversions. The second step utilizes a single-loop, first-order delta–sigma modulator (\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M). In the third step, the \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M is reconfigured as an exponential counting loop with split positive feedback (SPF). The SPF isolates the loop integrator from the residue sampling network, thereby improving the settling time of the residue amplifier (RA) under the transient switching of linear-exponential loads. Besides, a duty-cycle RA further reduces its average power from 48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier \u0000<inline-formula> <tex-math>${mathrm { FoM}}_{mathrm { S,{mathrm {DR}}}}$ </tex-math></inline-formula>\u0000 of 177.7 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"1-4"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.41-ns CLK-OUT Delay, 0.22-μVrms Input-Referred Noise CMOS Integration Dynamic Comparator With Flipping Capacitor for Charge Reuse 0.41-ns CLK-OUT 延迟、0.22-μVrms 输入延迟噪声 CMOS 集成动态比较器，带翻转电容器，可重复使用电荷
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-02 DOI: 10.1109/LSSC.2024.3510389
Kwok Cheong Li;Xinhang Xu;Jihang Gao;Siyuan Ye;Jiajia Cui;Yacong Zhang;Ru Huang;Linxiao Shen
{"title":"A 0.41-ns CLK-OUT Delay, 0.22-μVrms Input-Referred Noise CMOS Integration Dynamic Comparator With Flipping Capacitor for Charge Reuse","authors":"Kwok Cheong Li;Xinhang Xu;Jihang Gao;Siyuan Ye;Jiajia Cui;Yacong Zhang;Ru Huang;Linxiao Shen","doi":"10.1109/LSSC.2024.3510389","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510389","url":null,"abstract":"A high-speed and power-efficient CMOS integration dynamic comparator is presented. Low-input-referred noise is accomplished by CMOS integration. To achieve low-power consumption, a charge-reusing scheme by flipping the flying capacitors across the pMOS/nMOS integration nodes is introduced. The 22-nm prototype achieves a 0.22-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000Vrms input-referred noise with an energy consumption of 227-fJ per conversion, which is improved by \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 compared with the StrongARM counterpart in the same process. Furthermore, with the latch stage embedded, the achieved 0.41-ns CLK-OUT delay shows an over \u0000<inline-formula> <tex-math>$20times $ </tex-math></inline-formula>\u0000 improvement compared with the existing works with CMOS integration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"5-8"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Reconfigurable, Multichannel Quantized-Analog Transmitter With <-35 dB EVM and <-51 dBc ACLR in 22-nm FDSOI 22纳米FDSOI中EVM <-35 dB、ACLR <-51 dBc的可重构多通道量化模拟发射机
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-29 DOI: 10.1109/LSSC.2024.3509378
John Zhong;Konstantinos Vasilakopoulos;Antonio Liscidini
{"title":"A Reconfigurable, Multichannel Quantized-Analog Transmitter With <-35 dB EVM and <-51 dBc ACLR in 22-nm FDSOI","authors":"John Zhong;Konstantinos Vasilakopoulos;Antonio Liscidini","doi":"10.1109/LSSC.2024.3509378","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3509378","url":null,"abstract":"This letter presents a multichannel quantized analog transmitter to maintain the spectral purity of the analog systems while offering radio-frequency digital-to-analog converter flexibility. Consuming 275 mW power, it achieves an EVM of better than −35 dB with an ACLR1/2 of −51/−54 dBc for a 15 MHz 64-QAM signal at 9.4-dBm output power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"355-358"},"PeriodicalIF":2.2,"publicationDate":"2024-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS 65纳米CMOS的两层四核双模VCO
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-27 DOI: 10.1109/LSSC.2024.3506672
Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi
{"title":"A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS","authors":"Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi","doi":"10.1109/LSSC.2024.3506672","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3506672","url":null,"abstract":"To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multistory multicore multimode oscillator topology based on the following ideas: 1) the N number of cores reduces the PN by \u0000<inline-formula> <tex-math>$10 log (N)$ </tex-math></inline-formula>\u0000 dB, and the circular geometry of inductors promotes their high-quality \u0000<inline-formula> <tex-math>$(Q)$ </tex-math></inline-formula>\u0000-factors and compact layout; 2) the multiple stacked cores exploiting current reuse improve the figure of merit (FoM) using an nMOS-only oscillator configuration under a standard supply; and 3) the multiple modes expand the FTR by leveraging the interstory coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of −111.3 to −106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, and a 197.6–200.2-dBc/Hz \u0000<inline-formula> <tex-math>$rm {FoM}_{T}$ </tex-math></inline-formula>\u0000 (i.e., FoM with normalized FTR).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"363-366"},"PeriodicalIF":2.2,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Adaptive Subharmonic Pulse Injection Crystal Oscillator Achieving —40 ∘C to 125 ∘C Operation 一种自适应亚谐波脉冲注入晶体振荡器，可在-40°C到125°C下工作
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-21 DOI: 10.1109/LSSC.2024.3503615
Yingjie Zhu;Yiqing Lan;Humiao Li;Haoran Lyu;Zhen Kong;Jian Zhao;Yida Li;Guoxing Wang;Jiamin Li;Longyang Lin
{"title":"An Adaptive Subharmonic Pulse Injection Crystal Oscillator Achieving —40 ∘C to 125 ∘C Operation","authors":"Yingjie Zhu;Yiqing Lan;Humiao Li;Haoran Lyu;Zhen Kong;Jian Zhao;Yida Li;Guoxing Wang;Jiamin Li;Longyang Lin","doi":"10.1109/LSSC.2024.3503615","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3503615","url":null,"abstract":"Subharmonic pulse injection crystal oscillators enable sub-nW operation with less frequent energy injection at oscillation peaks and valleys. However, this poses stringent requirements on the injection accuracy, which affects operation power, jitter, and reliability. To ensure accurate valley and peak injection across a wide temperature at minimum overhead, this work proposes the zero-voltage detection (ZVD)-based closed-loop timing adaptation, unbalanced differential injection and oscillation DC stabilizing techniques for a single-supply 16th subharmonic pulse-injection-based crystal oscillator (XO). Fabricated in 22-nm FDSOI, the IC enables operation across the widest reported temperature range from \u0000<inline-formula> <tex-math>$-40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>\u0000C, and achieves a 11 ppb Allan deviation floor while consuming 0.72 nW and 0.006 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"351-354"},"PeriodicalIF":2.2,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Average Amplitude Regulation Scheme for Ambient Illuminance Adaptation in Retinal Prosthesis 视网膜假体适应环境照度的平均振幅调节方案
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-05 DOI: 10.1109/LSSC.2024.3491166
Kyeongho Eom;Hyung-Min Lee
{"title":"An Average Amplitude Regulation Scheme for Ambient Illuminance Adaptation in Retinal Prosthesis","authors":"Kyeongho Eom;Hyung-Min Lee","doi":"10.1109/LSSC.2024.3491166","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3491166","url":null,"abstract":"This letter proposes an 8-channel retinal prosthesis stimulator with an average amplitude regulation (AAR) scheme to enable illuminance adaptation in retinal prosthesis to improve visual acuity in patients. The AAR scheme facilitates effective light adaptation by maintaining a consistent average stimulation current with global feedback. This method supports both subretinal and epi-retinal prostheses by regulating stimulus current levels rather than photodiode sensitivity. This approach eliminates the need for complex metal line connections, reducing pixel size. Experimental results demonstrate the AAR scheme’s effectiveness in maintaining appropriate stimulation levels, with the capability to return to the original average stimulation current within 260 ms after sudden changes in brightness, while achieving stimulation current mismatch less than 3.03%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"347-350"},"PeriodicalIF":2.2,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar 利用 CMOS-RFIC 进行太赫兹传感：使用 300-GHz MIMO 雷达进行短距离成像的可行性验证
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-04 DOI: 10.1109/LSSC.2024.3490547
Ichiro Somada;Akihito Hirai;Akinori Taira;Keigo Nakatani;Kazuaki Ishioka;Takuma Nishimura;Koji Yamanaka
{"title":"Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar","authors":"Ichiro Somada;Akihito Hirai;Akinori Taira;Keigo Nakatani;Kazuaki Ishioka;Takuma Nishimura;Koji Yamanaka","doi":"10.1109/LSSC.2024.3490547","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3490547","url":null,"abstract":"For solving various social issues, sensing technology has gained significant interest. Terahertz waves, which combine the high resolution of light and transparency of radio waves, enable visualization of obstacles behind internal structures. So, it offers potential for new solutions. This letter introduces the overview of a short-distance sensing system based on the full digital MIMO radar concept, the design, and fundamental evaluation results of 300 GHz RFIC using CMOS technology, as well as the achievements of imaging using 300 GHz terahertz wave based on actual measurements. Since the terahertz band can obtain an ultrawideband spectrum, several millimeter resolution imaging can be performed in azimuth, elevation, and depth direction. We show the feasibility of the security gate application with the measured high-resolution tomographic images.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"343-346"},"PeriodicalIF":2.2,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142671119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter 分析和优化增益增强型 N 路径开关电容带通滤波器中由寄生引起的峰值频移
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-30 DOI: 10.1109/LSSC.2024.3488001
Lei Lei;Zhiming Chen
{"title":"Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter","authors":"Lei Lei;Zhiming Chen","doi":"10.1109/LSSC.2024.3488001","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3488001","url":null,"abstract":"This letter proposes a \u0000<inline-formula> <tex-math>$C/g_{m}$ </tex-math></inline-formula>\u0000 method for analyzing the peak frequency shift caused by parasitic parameters in gain-boosted N-path switched-capacitor bandpass filter (GB-BPF). This method eliminates the device width variable, addressing the interdependencies among various parameters in GB-BPF. Numerical solution for peak frequency shift is obtained, and the impact of each variable on frequency shift is accurately quantified. Using the proposed \u0000<inline-formula> <tex-math>$C/g_{m}$ </tex-math></inline-formula>\u0000 variable, the optimal bias voltage is determined to minimize the peak frequency shift for same parasitic parameters. Additionally, optimization strategies for adjusting the filter capacitance and switching frequency are proposed. Finally, a GB-BPF is implemented in a 90-nm CMOS process. The accuracy of the analysis is verified by comparing the measured and simulated results with the theoretically derived results.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"339-342"},"PeriodicalIF":2.2,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method 利用模拟加减法实现相位补偿的 28 千兆赫可变增益移相器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-29 DOI: 10.1109/LSSC.2024.3487586
Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang
{"title":"A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method","authors":"Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang","doi":"10.1109/LSSC.2024.3487586","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3487586","url":null,"abstract":"In this letter, a 28-GHz variable-gain phase shifter (VG-PS) with phase compensation designed using a Gilbert-cell-based vector summation amplifier integrated with a current-type digital-to-analog converter (DAC) and a quadrature all-pass filter (QAF) I/Q generator, fabricated using the 90-nm CMOS process. The VG-PS achieves a 360° phase-shifting range with a 7-bit resolution and 7-dB gain-tuning range. The vector summation amplifier synthesizes a vector by combining in-phase and quadrature-phase signals, which are determined by the tail currents of the vector summation amplifier. Tail currents for the vector summation amplifier are generated and mirrored by the current-type DAC. Any mismatch between the DAC’s tail current and that of the vector summation amplifier results in amplitude and phase discrepancies in the synthesized vector. The proposed calibration method optimizes amplitude and phase accuracy through current addition and subtraction, eliminating the need for I/Q calibration of the QAF. Measurements show root-mean-square gain and phase errors of the VG-PS at 28 GHz to be 0.12 dB and 0.23°, respectively. The chip size of VG-PS is 0.723 mm2, including pads, and it consumes 32 mW at maximum gain state.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"335-338"},"PeriodicalIF":2.2,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142636474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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