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IEEE Solid-State Circuits Letters最新文献

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A Scalable mK DC Demultiplexer With Extremely Low OFF-Leakage CMOS Switches for Biasing of Spin Qubits 一种可扩展的mK DC解复用器，具有极低的off -漏CMOS开关，用于自旋量子位的偏置
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-22 DOI: 10.1109/LSSC.2025.3591584
Alican Caglar;Imri Fattal;Clement Godfrin;Roy Li;Steven Van Winckel;Kristiaan De Greve;Piet Wambacq;Jan Craninckx
{"title":"A Scalable mK DC Demultiplexer With Extremely Low OFF-Leakage CMOS Switches for Biasing of Spin Qubits","authors":"Alican Caglar;Imri Fattal;Clement Godfrin;Roy Li;Steven Van Winckel;Kristiaan De Greve;Piet Wambacq;Jan Craninckx","doi":"10.1109/LSSC.2025.3591584","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3591584","url":null,"abstract":"This letter demonstrates a DC demultiplexer using CMOS switches with extremely low OFF-state current at mK temperatures. The DC demultiplexer is designed to reduce the number of interconnections needed for voltage biasing of large-scale spin qubit arrays. The demultiplexer utilizes a T-switch structure and thick-oxide devices in a 65 nm bulk CMOS technology to avoid current leakage in the OFF-state of switches at mK temperatures, which enables preservation of a voltage stored on a capacitor without the need for resampling thereby reducing dynamic power consumption. The demultiplexer has a static power consumption of 33 nW with 4 inputs and 16 outputs, which can be scaled up using the SPI interface of the demultiplexer in a daisy-chain configuration. With its scalability, ultralow static power dissipation, and extremely low OFF-leakage current, the DC demultiplexer can help mitigate the wiring bottleneck of spin-based quantum computers at the base stage of dilution refrigerators.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"221-224"},"PeriodicalIF":2.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth 具有pvt不敏感环路带宽的双径SPD/PFD锁相环
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-16 DOI: 10.1109/LSSC.2025.3589568
Yan Chen;Gaofeng Jin;Haojie Xu;Yu Cui;Lei Zeng;Xiang Gao
{"title":"A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth","authors":"Yan Chen;Gaofeng Jin;Haojie Xu;Yu Cui;Lei Zeng;Xiang Gao","doi":"10.1109/LSSC.2025.3589568","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3589568","url":null,"abstract":"This work presents an 8.5–14 GHz dual-path sampling phase detection (SPD)/phase frequency detection (PFD) phase-locked loop (PLL) (DP-SPFDPLL), with extended frequency/phase detection ranges, built-in frequency-locked loop (FLL) function, and stable loop bandwidth across PVT corners. An SPD and a PFD are placed on the dual paths, responsible for phase/frequency locking and temperature drift tracking. An SPD replica is introduced to align the locking points of the integral and proportional paths. A Slew Rate Calibration technique using a Ring Oscillator is proposed to make the slew rate of sampling ramps stable. Implemented in 7 nm FinFET, the 8.5–14 GHz DP-SPFDPLL achieves <inline-formula> <tex-math>$75~fs_{rms}$ </tex-math></inline-formula> integrated jitter and −252 dB PLL Figure-of-Merit (FoM)J.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"237-240"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement 一种55纳米SRAM芯片每125纳秒扫描误差用于事件智能软误差测量
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-16 DOI: 10.1109/LSSC.2025.3589611
Yuibi Gomi;Akira Sato;Waleed Madany;Kenichi Okada;Satoshi Adachi;Masatoshi Itoh;Masanori Hashimoto
{"title":"A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement","authors":"Yuibi Gomi;Akira Sato;Waleed Madany;Kenichi Okada;Satoshi Adachi;Masatoshi Itoh;Masanori Hashimoto","doi":"10.1109/LSSC.2025.3589611","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3589611","url":null,"abstract":"We developed a 55 nm CMOS static random access memory (SRAM) chip that scans all data every 125 ns and outputs timestamped soft error data via an SPI interface through a FIFO. The proposed system, consisting of the developed chip and particle detectors, enables event-wise soft error measurement and precise identification of single bit upset and multiple-cell upsets (MCUs), thus resolving misclassifications such as Pseudo- and Distant MCUs that conventional methods cannot distinguish. An 80-MeV proton irradiation experiment at RARiS, Tohoku University verified the system operation. Timestamps between the SRAM chip and the particle detectors were successfully synchronized, accounting for PLL disturbances caused by radiation. Event building was achieved by determining a reset offset with sub-ns resolution, and spatial synchronization was maintained within several tens of micrometers.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"245-248"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144916321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning 一种基于rram的基于原位可转置计算和混合精度的边缘学习CIM设计
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-16 DOI: 10.1109/LSSC.2025.3589580
Qiumeng Wei;Peng Yao;Dong Wu;Qi Qin;Bin Gao;Qingtian Zhang;Sining Pan;Jianshi Tang;He Qian;Lu Jie;Huaqiang Wu
{"title":"A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning","authors":"Qiumeng Wei;Peng Yao;Dong Wu;Qi Qin;Bin Gao;Qingtian Zhang;Sining Pan;Jianshi Tang;He Qian;Lu Jie;Huaqiang Wu","doi":"10.1109/LSSC.2025.3589580","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3589580","url":null,"abstract":"Edge computing devices demand efficient transposable computing architectures to enable on-chip learning, necessitating novel hardware designs that balance performance and flexibility. We present an RRAM-based compute-in-memory macro capable of supporting both in-situ forward and backward propagation operations. The design incorporates an orthogonal-WL array structure with weight-level parallelism adjustment and a precision-driven input mechanism to enable flexible transposable computing. Additionally, optimized ADCs provide high throughput while maintaining area efficiency. The work exhibits a SOTA normalized area efficiency of 126.7 TOPS/mm2/bit, an energy efficiency of 2348.96 TOPS/W/bit, and a storage density of 4.84 Mb/mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"205-208"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144773316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact Low Power Active Oscillator Using Oxide TFTs on a Flexible Foil 在柔性箔上使用氧化物tft的小型低功率有源振荡器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-10 DOI: 10.1109/LSSC.2025.3587763
Suyash Shrivastava;Vaishali Choudhary;Pydi Ganga Bahubalindruni
{"title":"A Compact Low Power Active Oscillator Using Oxide TFTs on a Flexible Foil","authors":"Suyash Shrivastava;Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3587763","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3587763","url":null,"abstract":"This letter presents a novel voltage-controlled LC oscillators (LCO) designed for energy-efficient wearable applications. The circuit employs a compact AIND topology paired with cross-coupled transistors to generate sustained oscillations. The active inductor (AIND) has been implemented with four transistors. Cross-coupled transistors provide negative resistance to circumvent losses due to parasitic resistance, enabling robust oscillation while minimizing area. This LCO is fabricated on a <inline-formula> <tex-math>$27~ mu $ </tex-math></inline-formula>m thick flexible polyimide substrate using all enhancement n-type amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) technology. From measurements, the LCO has shown a wide tuning range (power consumption) of 152 kHz (<inline-formula> <tex-math>$10.4~ mu $ </tex-math></inline-formula>W)–1.9 MHz (<inline-formula> <tex-math>$450~ mu $ </tex-math></inline-formula>W), when the supply voltage (VDD) is swept from 0.8 to 2.5 V, respectively. Moreover, the LCO exhibits a phase noise of –94.26 and –90 dBc/Hz at a offset frequency of 10 kHz at a VDD of 2 and 0.8 V, respectively. The average tuning sensitivity <inline-formula> <tex-math>$(K_{text {LCO}})$ </tex-math></inline-formula> is around 985 kHz/V. Reproducibility and stress dependent stability of the LCO has been validated from multiple sample’s experimental characterization. This circuit occupies a total active area of 0.03 mm2. These parameters indicate that the proposed LCO can find potential applications in on-chip clock generation to implement compact wearable devices.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"209-212"},"PeriodicalIF":2.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144773263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact 8-to-16 GHz GaN Nonuniform Distributed PA With Double Feeding Line Matching Structure Presenting 43.2% Average PAE 一种具有双馈线匹配结构的8 ~ 16 GHz GaN非均匀分布PA，平均PAE为43.2%
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-10 DOI: 10.1109/LSSC.2025.3587242
Zhaowu Wang;Dexin Shi;Xinyan Li;Shu Ma;Ronglin Chen;Ze Yu;Ziao Wang;Shijie Chen;Xiaochen Tang;Yong Wang
{"title":"A Compact 8-to-16 GHz GaN Nonuniform Distributed PA With Double Feeding Line Matching Structure Presenting 43.2% Average PAE","authors":"Zhaowu Wang;Dexin Shi;Xinyan Li;Shu Ma;Ronglin Chen;Ze Yu;Ziao Wang;Shijie Chen;Xiaochen Tang;Yong Wang","doi":"10.1109/LSSC.2025.3587242","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3587242","url":null,"abstract":"This letter focuses on improving power added efficiency (PAE) of high-power nonuniform distributed power amplifier (NDPA). A double feeding line matching (DFLM) structure is proposed, where a double-T-type and a <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-type DFLM networks are inserted into drain transmission-line (TL) and gate TL of classical designs, respectively. These optimize load/source impedance for each transistor, improving the output power and PAE. The NPDA monolithic microwave integrated circuit (MMIC) is fabricated with a commercial 0.25-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m gallium nitride (GaN) process. The measurement results show that the proposed NDPA achieves output power of 37.6-to-40.2 dBm, and PAE of 37.6%-to-50.3% at 8-to-16 GHz, with the chip area of merely 3.5 mm2. The proposed NPDA outperforms the state-of-the-art broadband power amplifier (PA) in PAE with a much smaller chip area.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"201-204"},"PeriodicalIF":2.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2 pA/√Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5 GHz Bandwidth for Optical Receiver 一种基于2.5 GHz带宽、180nm CMOS的2pa /√Hz输入参考噪声TIA
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-06-30 DOI: 10.1109/LSSC.2025.3584266
Yihao Yang;Dan Li;Nan Qi;Binhao Wang
{"title":"A 2 pA/√Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5 GHz Bandwidth for Optical Receiver","authors":"Yihao Yang;Dan Li;Nan Qi;Binhao Wang","doi":"10.1109/LSSC.2025.3584266","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3584266","url":null,"abstract":"This letter describes an ultralow-noise, high-speed transimpedance amplifier (TIA) applied to the analog front-end (AFE) circuit of the high-sensitivity optical receiver. A combination of a three-stage amplifier and two positive feedback Miller capacitors is introduced to comprehensively reduce the input-referred noise current (IRNC) of a shunt-feedback TIA (SFTIA) and to extend its bandwidth (BW). The proposed SFTIA utilizes an 80 K<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> resistor as the feedback resistor (RF) and achieves a BW of 2.5 GHz and an average IRNC of only 2 pA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz in 180 nm CMOS technology, which is the lowest TIA noise reported to date above the GHz BW. Although the fabrication process is not as advanced as the state-of-the-art process, we believe it remains valuable and instructive for a wide variety of applications requiring low noise and high sensitivity.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"189-192"},"PeriodicalIF":2.2,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144662025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency 数字低压差稳压器辅助降压DC-DC变换器，降压电压为68 mv，效率为95.5%
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-06-20 DOI: 10.1109/LSSC.2025.3581844
Yichen Xu;Zhaoqing Wang;Rentao Wan;Suhwan Kim;Minxiang Gong;Ram Krishnamurthy;Xin Zhang;Mingoo Seok
{"title":"Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency","authors":"Yichen Xu;Zhaoqing Wang;Rentao Wan;Suhwan Kim;Minxiang Gong;Ram Krishnamurthy;Xin Zhang;Mingoo Seok","doi":"10.1109/LSSC.2025.3581844","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3581844","url":null,"abstract":"This letter proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high-peak efficiency of 95.5%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"193-196"},"PeriodicalIF":2.0,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144751050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10.9-nV/√Hz, 74.9-dB DR, 20-MS/s Ultrasound Analog Front End for Fully Digital Beamforming 用于全数字波束形成的10.9 nv /√Hz, 74.9 db DR， 20 ms /s超声模拟前端
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-06-20 DOI: 10.1109/LSSC.2025.3581584
Changde Ding;Yan Zhu;Pengjie Wang;Zhiliang Hong;Jiawei Xu
{"title":"A 10.9-nV/√Hz, 74.9-dB DR, 20-MS/s Ultrasound Analog Front End for Fully Digital Beamforming","authors":"Changde Ding;Yan Zhu;Pengjie Wang;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3581584","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3581584","url":null,"abstract":"This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully digital beamforming in endoscopic and catheter-based 3-D ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20-MS/s SAR ADC. To minimize chip area and power consumption, the LNA employs a capacitor-splitting inverter-based amplifier with dynamic power control, while the ADC utilizes unit-length capacitors and digital error correction. A modified monotonic switching improves the conversion rate, and the kickback noise is reduced by an enhanced Elzakker comparator. Fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the ultrasound AFE occupies a low silicon area of 0.052 mm2/channel, achieves 74.93-dB dynamic range (DR), 10.9-nV/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz input referred noise, and −58.33-dB total harmonic distortion (THD). The average power consumption is 1.34 mW/channel.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"185-188"},"PeriodicalIF":2.2,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144597896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique 基于残差移位技术的6.2b-ENOB 2.5 GS/s flash - vco邻域ADC
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-06-11 DOI: 10.1109/LSSC.2025.3578546
Sungjin Kim;Jeonghyun Lee;Yoonse Cho;Jintae Kim;Jaehyouk Choi;Heein Yoon
{"title":"A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique","authors":"Sungjin Kim;Jeonghyun Lee;Yoonse Cho;Jintae Kim;Jaehyouk Choi;Heein Yoon","doi":"10.1109/LSSC.2025.3578546","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3578546","url":null,"abstract":"This letter presents a 7-bit pipelined subranging ADC that integrates a 3-bit flash ADC with a ring VCO-based quantizer. A resistor-ladder-based residue shifter (RLRS) replaces traditional residue amplifiers, efficiently shifting the residue voltage into the most linear region of the <inline-formula> <tex-math>$K_{textrm {VCO}}$ </tex-math></inline-formula>, thereby eliminating the need for post-linearity calibration. Fabricated in a 28-nm FDSOI process, the ADC occupies an area of 0.009 mm2 and achieves an SNDR of 39.26 dB and an SFDR of 48.01 dB at 2.5 GS/s, while consuming 6.5 mW of power. This results in a Walden FOM of 34.6 fJ/conversion step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"177-180"},"PeriodicalIF":2.2,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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