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A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS 65纳米CMOS的两层四核双模VCO
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-27 DOI: 10.1109/LSSC.2024.3506672
Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi
{"title":"A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS","authors":"Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi","doi":"10.1109/LSSC.2024.3506672","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3506672","url":null,"abstract":"To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multistory multicore multimode oscillator topology based on the following ideas: 1) the N number of cores reduces the PN by \u0000<inline-formula> <tex-math>$10 log (N)$ </tex-math></inline-formula>\u0000 dB, and the circular geometry of inductors promotes their high-quality \u0000<inline-formula> <tex-math>$(Q)$ </tex-math></inline-formula>\u0000-factors and compact layout; 2) the multiple stacked cores exploiting current reuse improve the figure of merit (FoM) using an nMOS-only oscillator configuration under a standard supply; and 3) the multiple modes expand the FTR by leveraging the interstory coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of −111.3 to −106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, and a 197.6–200.2-dBc/Hz \u0000<inline-formula> <tex-math>$rm {FoM}_{T}$ </tex-math></inline-formula>\u0000 (i.e., FoM with normalized FTR).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"363-366"},"PeriodicalIF":2.2,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Adaptive Subharmonic Pulse Injection Crystal Oscillator Achieving —40 ∘C to 125 ∘C Operation 一种自适应亚谐波脉冲注入晶体振荡器，可在-40°C到125°C下工作
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-21 DOI: 10.1109/LSSC.2024.3503615
Yingjie Zhu;Yiqing Lan;Humiao Li;Haoran Lyu;Zhen Kong;Jian Zhao;Yida Li;Guoxing Wang;Jiamin Li;Longyang Lin
{"title":"An Adaptive Subharmonic Pulse Injection Crystal Oscillator Achieving —40 ∘C to 125 ∘C Operation","authors":"Yingjie Zhu;Yiqing Lan;Humiao Li;Haoran Lyu;Zhen Kong;Jian Zhao;Yida Li;Guoxing Wang;Jiamin Li;Longyang Lin","doi":"10.1109/LSSC.2024.3503615","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3503615","url":null,"abstract":"Subharmonic pulse injection crystal oscillators enable sub-nW operation with less frequent energy injection at oscillation peaks and valleys. However, this poses stringent requirements on the injection accuracy, which affects operation power, jitter, and reliability. To ensure accurate valley and peak injection across a wide temperature at minimum overhead, this work proposes the zero-voltage detection (ZVD)-based closed-loop timing adaptation, unbalanced differential injection and oscillation DC stabilizing techniques for a single-supply 16th subharmonic pulse-injection-based crystal oscillator (XO). Fabricated in 22-nm FDSOI, the IC enables operation across the widest reported temperature range from \u0000<inline-formula> <tex-math>$-40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>\u0000C, and achieves a 11 ppb Allan deviation floor while consuming 0.72 nW and 0.006 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"351-354"},"PeriodicalIF":2.2,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Average Amplitude Regulation Scheme for Ambient Illuminance Adaptation in Retinal Prosthesis 视网膜假体适应环境照度的平均振幅调节方案
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-05 DOI: 10.1109/LSSC.2024.3491166
Kyeongho Eom;Hyung-Min Lee
{"title":"An Average Amplitude Regulation Scheme for Ambient Illuminance Adaptation in Retinal Prosthesis","authors":"Kyeongho Eom;Hyung-Min Lee","doi":"10.1109/LSSC.2024.3491166","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3491166","url":null,"abstract":"This letter proposes an 8-channel retinal prosthesis stimulator with an average amplitude regulation (AAR) scheme to enable illuminance adaptation in retinal prosthesis to improve visual acuity in patients. The AAR scheme facilitates effective light adaptation by maintaining a consistent average stimulation current with global feedback. This method supports both subretinal and epi-retinal prostheses by regulating stimulus current levels rather than photodiode sensitivity. This approach eliminates the need for complex metal line connections, reducing pixel size. Experimental results demonstrate the AAR scheme’s effectiveness in maintaining appropriate stimulation levels, with the capability to return to the original average stimulation current within 260 ms after sudden changes in brightness, while achieving stimulation current mismatch less than 3.03%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"347-350"},"PeriodicalIF":2.2,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar 利用 CMOS-RFIC 进行太赫兹传感：使用 300-GHz MIMO 雷达进行短距离成像的可行性验证
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-11-04 DOI: 10.1109/LSSC.2024.3490547
Ichiro Somada;Akihito Hirai;Akinori Taira;Keigo Nakatani;Kazuaki Ishioka;Takuma Nishimura;Koji Yamanaka
{"title":"Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar","authors":"Ichiro Somada;Akihito Hirai;Akinori Taira;Keigo Nakatani;Kazuaki Ishioka;Takuma Nishimura;Koji Yamanaka","doi":"10.1109/LSSC.2024.3490547","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3490547","url":null,"abstract":"For solving various social issues, sensing technology has gained significant interest. Terahertz waves, which combine the high resolution of light and transparency of radio waves, enable visualization of obstacles behind internal structures. So, it offers potential for new solutions. This letter introduces the overview of a short-distance sensing system based on the full digital MIMO radar concept, the design, and fundamental evaluation results of 300 GHz RFIC using CMOS technology, as well as the achievements of imaging using 300 GHz terahertz wave based on actual measurements. Since the terahertz band can obtain an ultrawideband spectrum, several millimeter resolution imaging can be performed in azimuth, elevation, and depth direction. We show the feasibility of the security gate application with the measured high-resolution tomographic images.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"343-346"},"PeriodicalIF":2.2,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142671119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter 分析和优化增益增强型 N 路径开关电容带通滤波器中由寄生引起的峰值频移
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-30 DOI: 10.1109/LSSC.2024.3488001
Lei Lei;Zhiming Chen
{"title":"Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter","authors":"Lei Lei;Zhiming Chen","doi":"10.1109/LSSC.2024.3488001","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3488001","url":null,"abstract":"This letter proposes a \u0000<inline-formula> <tex-math>$C/g_{m}$ </tex-math></inline-formula>\u0000 method for analyzing the peak frequency shift caused by parasitic parameters in gain-boosted N-path switched-capacitor bandpass filter (GB-BPF). This method eliminates the device width variable, addressing the interdependencies among various parameters in GB-BPF. Numerical solution for peak frequency shift is obtained, and the impact of each variable on frequency shift is accurately quantified. Using the proposed \u0000<inline-formula> <tex-math>$C/g_{m}$ </tex-math></inline-formula>\u0000 variable, the optimal bias voltage is determined to minimize the peak frequency shift for same parasitic parameters. Additionally, optimization strategies for adjusting the filter capacitance and switching frequency are proposed. Finally, a GB-BPF is implemented in a 90-nm CMOS process. The accuracy of the analysis is verified by comparing the measured and simulated results with the theoretically derived results.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"339-342"},"PeriodicalIF":2.2,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method 利用模拟加减法实现相位补偿的 28 千兆赫可变增益移相器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-29 DOI: 10.1109/LSSC.2024.3487586
Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang
{"title":"A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method","authors":"Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang","doi":"10.1109/LSSC.2024.3487586","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3487586","url":null,"abstract":"In this letter, a 28-GHz variable-gain phase shifter (VG-PS) with phase compensation designed using a Gilbert-cell-based vector summation amplifier integrated with a current-type digital-to-analog converter (DAC) and a quadrature all-pass filter (QAF) I/Q generator, fabricated using the 90-nm CMOS process. The VG-PS achieves a 360° phase-shifting range with a 7-bit resolution and 7-dB gain-tuning range. The vector summation amplifier synthesizes a vector by combining in-phase and quadrature-phase signals, which are determined by the tail currents of the vector summation amplifier. Tail currents for the vector summation amplifier are generated and mirrored by the current-type DAC. Any mismatch between the DAC’s tail current and that of the vector summation amplifier results in amplitude and phase discrepancies in the synthesized vector. The proposed calibration method optimizes amplitude and phase accuracy through current addition and subtraction, eliminating the need for I/Q calibration of the QAF. Measurements show root-mean-square gain and phase errors of the VG-PS at 28 GHz to be 0.12 dB and 0.23°, respectively. The chip size of VG-PS is 0.723 mm2, including pads, and it consumes 32 mW at maximum gain state.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"335-338"},"PeriodicalIF":2.2,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142636474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication 用于卫星间光学通信的 33.06 Gb/s 可重构伽罗瓦场 oFEC 解码器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-24 DOI: 10.1109/LSSC.2024.3486234
Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim
{"title":"A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication","authors":"Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim","doi":"10.1109/LSSC.2024.3486234","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3486234","url":null,"abstract":"We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at \u0000<inline-formula> <tex-math>$10^{text {-6}}$ </tex-math></inline-formula>\u0000 BER with an oFEC code using inner BCH(256, 223).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"331-334"},"PeriodicalIF":2.2,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Time-Modulated-LO-Path Vector Modulators for Beamforming Receivers 用于波束成形接收器的时间调制-LO-路径矢量调制器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-11 DOI: 10.1109/LSSC.2024.3478837
Petar Barac;Matthew Bajor;Peter R. Kinget
{"title":"Time-Modulated-LO-Path Vector Modulators for Beamforming Receivers","authors":"Petar Barac;Matthew Bajor;Peter R. Kinget","doi":"10.1109/LSSC.2024.3478837","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3478837","url":null,"abstract":"A time-modulated LO (TM-LO) vector modulator (VM) architecture using a time domain approach for amplitude scaling and phase shifting received signals is presented. The TM-LO uses rail-to-rail LO waveforms generated from digitally synthesized blocks and pass-gate switches to perform the amplitude/phase control. A single element receiver achieves 0.2 dB RMS gain error and 1.4° RMS phase error with 5 bits of amplitude/phase resolution across a 360° range is implemented in a 65 nm CMOS process. Without time-modulation, the hardware is capable of 3-bits of resolution. The inherent digital nature of TM-LO architecture provides opportunity very compact front-ends suitable for large arrays and lower voltage technologies. Four TM-LO chips were used to create a beamforming receiver","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"323-326"},"PeriodicalIF":2.2,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation 基于 PLL 和 MDLL 组合的 1-3 GHz 快速锁定频率合成器，具有自动零相位误差补偿功能
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-11 DOI: 10.1109/LSSC.2024.3478799
Ching-Yuan Yang;Hao-Cheng Hsu;Ping-Heng Wu;Samuel Palermo
{"title":"A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation","authors":"Ching-Yuan Yang;Hao-Cheng Hsu;Ping-Heng Wu;Samuel Palermo","doi":"10.1109/LSSC.2024.3478799","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3478799","url":null,"abstract":"A fast-locking low-jitter hybrid frequency synthesizer using a charge-pump phase-locked loop (CP-PLL) and a multiplying delay-locked loop (MDLL) is presented. The CP-PLL uses a discriminator-aided detector (DAD) to alleviate the cycle-slipping issue and an auto-zero phase error compensator (AZ-PEC) to compensate the accumulated phase error during frequency acquisition to enhance the settling time. Then, the MDLL overcomes the jitter accumulation of CP-PLL. The synthesizer was fabricated in a 90-nm CMOS process. The output frequency ranges from 1 to 3 GHz. When switching from 1 to 2.5 GHz, the measured settling time using DAD and AZ-PEC is 520 ns, which is approximately 26 reference clock cycles. The power consumption is 12 mW at 2.5 GHz for a supply of 1.2 V. The integral root-mean-square jitter over 1 kHz–100 MHz is 1.62 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"315-318"},"PeriodicalIF":2.2,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management 基于数字 SRAM 的计算内存宏，支持并行维护网络管理
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-10 DOI: 10.1109/LSSC.2024.3477619
Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao
{"title":"A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management","authors":"Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao","doi":"10.1109/LSSC.2024.3477619","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3477619","url":null,"abstract":"A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves \u0000<inline-formula> <tex-math>$6.9times $ </tex-math></inline-formula>\u0000 in energy at 1.2 V and \u0000<inline-formula> <tex-math>$2.33times $ </tex-math></inline-formula>\u0000 in area compared with the conventional statistics counters in a 55-nm CMOS technology.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"327-330"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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