20–26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jin-Fa Chang
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Abstract

We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal $\lambda $ /4 spiral transmission line inductors based on a $\lambda $ /9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage ( $V_{\mathrm { th}}$ ) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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