IEEE Solid-State Circuits Letters最新文献

Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar 利用 CMOS-RFIC 进行太赫兹传感：使用 300-GHz MIMO 雷达进行短距离成像的可行性验证

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-11-04 DOI: 10.1109/LSSC.2024.3490547

Ichiro Somada;Akihito Hirai;Akinori Taira;Keigo Nakatani;Kazuaki Ishioka;Takuma Nishimura;Koji Yamanaka

引用次数: 0

Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter 分析和优化增益增强型 N 路径开关电容带通滤波器中由寄生引起的峰值频移

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-30 DOI: 10.1109/LSSC.2024.3488001

Lei Lei;Zhiming Chen

引用次数: 0

A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method 利用模拟加减法实现相位补偿的 28 千兆赫可变增益移相器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-29 DOI: 10.1109/LSSC.2024.3487586

Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang

{"title":"A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method","authors":"Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang","doi":"10.1109/LSSC.2024.3487586","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3487586","url":null,"abstract":"In this letter, a 28-GHz variable-gain phase shifter (VG-PS) with phase compensation designed using a Gilbert-cell-based vector summation amplifier integrated with a current-type digital-to-analog converter (DAC) and a quadrature all-pass filter (QAF) I/Q generator, fabricated using the 90-nm CMOS process. The VG-PS achieves a 360° phase-shifting range with a 7-bit resolution and 7-dB gain-tuning range. The vector summation amplifier synthesizes a vector by combining in-phase and quadrature-phase signals, which are determined by the tail currents of the vector summation amplifier. Tail currents for the vector summation amplifier are generated and mirrored by the current-type DAC. Any mismatch between the DAC’s tail current and that of the vector summation amplifier results in amplitude and phase discrepancies in the synthesized vector. The proposed calibration method optimizes amplitude and phase accuracy through current addition and subtraction, eliminating the need for I/Q calibration of the QAF. Measurements show root-mean-square gain and phase errors of the VG-PS at 28 GHz to be 0.12 dB and 0.23°, respectively. The chip size of VG-PS is 0.723 mm2, including pads, and it consumes 32 mW at maximum gain state.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"335-338"},"PeriodicalIF":2.2,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142636474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication 用于卫星间光学通信的 33.06 Gb/s 可重构伽罗瓦场 oFEC 解码器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-24 DOI: 10.1109/LSSC.2024.3486234

Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim

引用次数: 0

Time-Modulated-LO-Path Vector Modulators for Beamforming Receivers 用于波束成形接收器的时间调制-LO-路径矢量调制器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-11 DOI: 10.1109/LSSC.2024.3478837

Petar Barac;Matthew Bajor;Peter R. Kinget

引用次数: 0

A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation 基于 PLL 和 MDLL 组合的 1-3 GHz 快速锁定频率合成器，具有自动零相位误差补偿功能

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-11 DOI: 10.1109/LSSC.2024.3478799

Ching-Yuan Yang;Hao-Cheng Hsu;Ping-Heng Wu;Samuel Palermo

引用次数: 0

A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management 基于数字 SRAM 的计算内存宏，支持并行维护网络管理

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-10 DOI: 10.1109/LSSC.2024.3477619

Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao

引用次数: 0

An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing 具有前/后通道切换抖动补偿和 DQS 驱动偏置功能的 8 纳米 20-Gb/s/pin 单端 PAM-4 收发器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-10 DOI: 10.1109/LSSC.2024.3477736

Kyunghwan Min;Jahoon Jin;Soo-Min Lee;Sodam Ju;Jisu Yook;Jihoon Lee;Yunji Hong;Sung-Sik Park;Sang-Ho Kim;Jongwoo Lee;Hyungjong Ko

{"title":"An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing","authors":"Kyunghwan Min;Jahoon Jin;Soo-Min Lee;Sodam Ju;Jisu Yook;Jihoon Lee;Yunji Hong;Sung-Sik Park;Sang-Ho Kim;Jongwoo Lee;Hyungjong Ko","doi":"10.1109/LSSC.2024.3477736","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3477736","url":null,"abstract":"This letter presents a 20-Gb/s/pin single-ended pulse amplitude modulation (PAM)-4 transceiver implemented in an 8-nm CMOS process, featuring an advanced switching jitter compensation (SWJC) technique and a DQS-driven amplifier bias generation method for a source-synchronous clocking system, aimed for next-generation low-power memory interfaces utilizing multilevel signaling. The proposed prechannel SWJC (pre-SWJC) in the transmitter adjusts the input edge timing of the thermometer PAM-4 driver to control the transitions of the PAM-4 signal. This transition control advances the outermost transitions, thereby not only minimizing the switching jitter (SWJ) of the middle eye but also enhancing the effectiveness of the post-channel SWJC (post-SWJC) performed at the receiver. Ultimately, the comprehensive solution combining the proposed pre/post-SWJC improved the timing margin from 0.26 UI to 0.39 UI at a BER of 1e-12, with only a 4.5% increase in power consumption and a 0.59% area overhead. Additionally, the proposed DQS-driven biasing technique in the receiver supplies biases for the amplifiers in the data lanes by utilizing the common-mode feedback of the replica amplifier in the differential clock lane. This approach reduces variation sources compared to the self-biasing structure that uses common-mode feedback in the data lanes, thereby improving the standard deviation of the amplifier’s bias voltage and gain variation by 58.3%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"319-322"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

0.6-V, μW-Power Four-Stage OTA With Minimal Components, and 100× Load Range 0.6 V、μW 功率四级 OTA，元件最少，负载范围达 100 倍

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-08 DOI: 10.1109/LSSC.2024.3476194

Marco Privitera;Alfio Dario Grasso;Andrea Ballo;Massimo Alioto

{"title":"0.6-V, μW-Power Four-Stage OTA With Minimal Components, and 100× Load Range","authors":"Marco Privitera;Alfio Dario Grasso;Andrea Ballo;Massimo Alioto","doi":"10.1109/LSSC.2024.3476194","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3476194","url":null,"abstract":"A four-stage operational transconductance amplifier (OTA) for ultralow-power applications is introduced in this letter. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the traditionally difficult compensation of four-stage OTAs and bringing it back to the simplicity of three-stage OTAs. At the same time, the proposed circuit achieves high power efficiency, as evidenced by the >\u0000<inline-formula> <tex-math>$3.7times $ </tex-math></inline-formula>\u0000 (>\u0000<inline-formula> <tex-math>$11.3times $ </tex-math></inline-formula>\u0000) improvement in the large-signal (small-signal) power efficiency figure of merit \u0000<inline-formula> <tex-math>${mathrm { FOM}}_{L}~({mathrm { FOM}}_{S})$ </tex-math></inline-formula>\u0000, compared to prior four-stage OTAs (sub-1 V multistage OTAs). Thanks to the lower sensitivity of the phase margin to the load capacitance, the proposed OTA remains stable under a wide range of loads (double-sided as in any three- and four-stage OTA), achieving a max/min ratio of the load capacitance of >\u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"311-314"},"PeriodicalIF":2.2,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler 使用紧凑型短路耦合器的宽带 GaN MMIC Doherty 功率放大器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-10-01 DOI: 10.1109/LSSC.2024.3471855

Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng

{"title":"Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler","authors":"Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng","doi":"10.1109/LSSC.2024.3471855","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3471855","url":null,"abstract":"In this letter, a broadband gallium nitride (GaN) monolithic microwave integrated circuit Doherty power amplifier (DPA) using a compact short-circuited coupler (CSC) is presented. To enhance the bandwidth and reduce the size of integrated DPA, the conventional \u0000<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>\u0000/2 transmission line in the peaking output matching network is replaced by the CSC structure. Detailed theoretical analysis and design procedures are provided. Based on the proposed solution, a 5.1–7.2-GHz DPA is designed using a 0.12-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaN HEMT process. The fractional bandwidth (FBW) is 34.1%. The measurement results show a saturated output power of 37.2–39 dBm and a 6-dB back-off drain efficiency of 38.4%–50.5% across the design bands with a chip size of \u0000<inline-formula> <tex-math>$2.6times 2$ </tex-math></inline-formula>\u0000.6 mm. The adjacent channel power ratio (ACPR) under 100-MHz single-carrier 64 QAM modulation signal with a 6-dB peak-to-average power ratio (PAPR) excitation is better than −45 dBc with digital predistortion (DPD).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"307-310"},"PeriodicalIF":2.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0