IEEE Solid-State Circuits Letters最新文献

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A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector 基于互补功率门控注入锁频乘法器的低参考杂散低抖动d波段锁相环鉴相器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-28 DOI: 10.1109/LSSC.2025.3564893
Jaeho Kim;Jooeun Bang;Seohee Jung;Myeongho Han;Jaehyouk Choi
{"title":"A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector","authors":"Jaeho Kim;Jooeun Bang;Seohee Jung;Myeongho Han;Jaehyouk Choi","doi":"10.1109/LSSC.2025.3564893","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3564893","url":null,"abstract":"This letter presents a D-Band fundamental-sampling phase-locked loop (FS-PLL) featuring a complementary power-gating injection locking frequency-multiplier-based phase detector (CPG-ILFM PD). To reduce the level of the reference spur, the proposed CPG-ILFM PD employs two replica voltage-controlled oscillators (RVCOs) that are alternatively switched to detect the phase error of the main VCO. This approach mitigates the binary frequency shift keying (BFSK)-like modulation typically observed in conventional ILFM PDs. Additionally, the loop bandwidth of the PLL was extended, effectively suppressing the poor out-of-band phase noise (PN) of the D-Band main VCO and enhancing jitter performance. Fabricated in a 40-nm CMOS process, the proposed D-Band PLL achieved a reference spur of −51 dBc and an RMS jitter of 65.6 fs while consuming 59.5 mW of power. This results in a jitter FoM of −245.9 dB at 119.5 GHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"129-132"},"PeriodicalIF":2.2,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 56-Gb/s DAC/ADC-Based Multicarrier Transceiver With TX Polar DSP and RX MIMO-DSP for >40-dB Loss Channel 一种56gb /s基于DAC/ adc的多载波收发器,具有TX极性DSP和RX MIMO-DSP,适用于>40-dB损耗通道
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-21 DOI: 10.1109/LSSC.2025.3562615
Srujan Kumar Kaile;Julian Camilo Gomez Diaz;Yuanming Zhu;Il-Min Yi;Tong Liu;Sebastian Hoyos;Samuel Palermo
{"title":"A 56-Gb/s DAC/ADC-Based Multicarrier Transceiver With TX Polar DSP and RX MIMO-DSP for >40-dB Loss Channel","authors":"Srujan Kumar Kaile;Julian Camilo Gomez Diaz;Yuanming Zhu;Il-Min Yi;Tong Liu;Sebastian Hoyos;Samuel Palermo","doi":"10.1109/LSSC.2025.3562615","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3562615","url":null,"abstract":"This letter presents a digital-to-analog-converter/analog-to-digital converter (DAC/ADC)-based multicarrier transceiver fabricated in a 22-nm FinFET technology. The multicarrier signaling scheme utilizes orthogonally spaced carriers for spectral efficient band spacing and exhibit jitter robustness compared to conventional baseband pulse amplitude-based signaling. The transmitter has a polar digital signal processor (DSP) to generate the equalized codes driving the 7-b phase DACs, and 7-b amplitude DACs with 2-b predistortion to yield 1.2-Vppd swing. The multicarrier receiver front-end ADC outputs are equalized with a MIMO DSP backend to compensate for the intersymbol interference and interchannel interference. The measured transceiver at 56 Gb/s through a 40.8-dB loss at 14-GHz channel showed a jitter tolerance of up to 1.21 psrms at BER<inline-formula> <tex-math>$lt 10{^{-}4 }$ </tex-math></inline-formula> with 7.82-pJ/bit power efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"125-128"},"PeriodicalIF":2.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Convolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving 基于卷积窗口的内存相似性感知计算节能技术
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-15 DOI: 10.1109/LSSC.2025.3560676
Yong-Jun Jo;Chufeng Yang;Yuanjin Zheng;Tony Tae-Hyoung Kim
{"title":"Convolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving","authors":"Yong-Jun Jo;Chufeng Yang;Yuanjin Zheng;Tony Tae-Hyoung Kim","doi":"10.1109/LSSC.2025.3560676","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3560676","url":null,"abstract":"Various data-driven computation-in-memory (CIM) architectures have been proposed to reduce inference energy. However, most data-driven CIM architectures require specific conditions to achieve energy savings (e.g., zero skip requires a ReLU activation function). This letter proposes a convolutional window-inspired similarity-aware CIM that saves energy by predicting the current output based on the previous one, which is applicable in most cases where the neural network is based on convolution. In addition, this letter introduces a novel transposable architecture to enhance linearity and an analog-to-digital converter (ADC) for improved area efficiency. The prototype was fabricated with 65 nm process and achieved the highest SWaP FoM as 19.04 TOPS/W<inline-formula> <tex-math>$times $ </tex-math></inline-formula>Mb/mm2 among the state-of-the-art transposable CIMs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"121-124"},"PeriodicalIF":2.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A MOS-Based Temperature Sensor With Energy-Efficient Techniques 一种基于mos的高能效温度传感器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-11 DOI: 10.1109/LSSC.2025.3559900
Jooeun Kim;Jeongmyeong Kim;Minkyu Yang;Kyounghun Kang;Wanyeong Jung
{"title":"A MOS-Based Temperature Sensor With Energy-Efficient Techniques","authors":"Jooeun Kim;Jeongmyeong Kim;Minkyu Yang;Kyounghun Kang;Wanyeong Jung","doi":"10.1109/LSSC.2025.3559900","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3559900","url":null,"abstract":"This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to <inline-formula> <tex-math>$145~^{circ }$ </tex-math></inline-formula>C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/<inline-formula> <tex-math>${+} 1.44~^{circ }$ </tex-math></inline-formula>C over the entire range and −0.96/<inline-formula> <tex-math>${+} 0.94~^{circ }$ </tex-math></inline-formula>C from −43 to <inline-formula> <tex-math>$137~^{circ }$ </tex-math></inline-formula>C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>K2 among MOS-based sensors.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"109-112"},"PeriodicalIF":2.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure 具有双边缘时域结构的分段精确可配置内存宏
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-08 DOI: 10.1109/LSSC.2025.3558928
Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He
{"title":"A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure","authors":"Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He","doi":"10.1109/LSSC.2025.3558928","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3558928","url":null,"abstract":"In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"117-120"},"PeriodicalIF":2.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology 采用柔性氧化物TFT技术的低功耗全动态锁存比较器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-04 DOI: 10.1109/LSSC.2025.3557862
Vaishali Choudhary;Pydi Ganga Bahubalindruni
{"title":"A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology","authors":"Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3557862","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557862","url":null,"abstract":"This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a <inline-formula> <tex-math>$27~mu $ </tex-math></inline-formula>m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> of 4 V, while consuming only <inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"101-104"},"PeriodicalIF":2.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143850040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Power Consumption and Propagation Delay in Voltage Level Shifters 电压电平转换器的功耗和传播延迟分析
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-03 DOI: 10.1109/LSSC.2025.3557524
Mehdi Saberi;Alexandre Schmid
{"title":"Analysis of Power Consumption and Propagation Delay in Voltage Level Shifters","authors":"Mehdi Saberi;Alexandre Schmid","doi":"10.1109/LSSC.2025.3557524","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557524","url":null,"abstract":"The analysis of the operation of nonlinear circuits, such as voltage level shifters and latched comparators, and therefore the prediction of their propagation delay and power consumption, is challenging. This is because the operating points of the employed nonlinear devices are time-varying. Hence, in this letter, a new approach which uses the trajectory of the operating points of the employed devices is proposed to analyze nonlinear circuits. The proposed method is used to provide a comprehensive study about the operation of the cross-coupled voltage level shifters. The proposed analysis not only formulates the existing contention between the pull-up and pull-down devices but also presents closed-form formulas for the delay as well as the power consumption. Measurement results of a prototype implemented in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology verify the effectiveness of the proposed method.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"113-116"},"PeriodicalIF":2.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaN HEMT-Based Resonators Using Parasitic Effects and Its Application to A Ka-band Coupled-Resonator SPDT Switch 利用寄生效应的GaN hemt谐振器及其在ka波段耦合谐振器SPDT开关中的应用
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-04-03 DOI: 10.1109/LSSC.2025.3557531
Guangxu Shen;Haitao Ma;Chenyang Zhang;Dingyuan Zeng Member;Haoshen Zhu;Wenquan Che
{"title":"GaN HEMT-Based Resonators Using Parasitic Effects and Its Application to A Ka-band Coupled-Resonator SPDT Switch","authors":"Guangxu Shen;Haitao Ma;Chenyang Zhang;Dingyuan Zeng Member;Haoshen Zhu;Wenquan Che","doi":"10.1109/LSSC.2025.3557531","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557531","url":null,"abstract":"A series of switchable resonators are proposed by incorporating the parasitic effects of two gallium nitride (GaN) high electron mobility transistor (HEMT) devices in this letter, based on which a broadband single-pole double-throw (SPDT) switch is presented with a bandpass response. As for on-chip switches, the ideal transistor is desired to act as a capacitor in its off-state but a resistor in its on-state. In conventional switch designs, the inductive effects of transistors are typically suppressed due to their detrimental impact on impedance matching and isolation. In contrast to this conventional approach, this study proposes a resonator-based design strategy that intentionally exploits and amplifies these inductive characteristics to construct two distinct GaN HEMT-integrated resonators. The first resonator employs the enhanced on-state inductance of a switching transistor combined with an MIM capacitor to form a series resonant network, enabling broadband impedance matching. The second resonator utilizes the large off-state capacitance of a power transistor and a short-circuited transmission line to establish a parallel resonant network. Leveraging the unique properties of these resonators, a broadband switch topology is accordingly proposed and experimentally validated. For demonstration, a SPDT switch is designed and fabricated in a 100 nm GaN-on-Si process. The proposed switch operates from 16 to 33 GHz based on experimental measurements. Two transmission poles are observed in the passband. This result experimentally validates the GaN HEMT-based resonator design.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"105-108"},"PeriodicalIF":2.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143850828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Secure FMCW LiDAR Ranging With an Electro-Optical Synthesizer at 5000 Measurements/s 利用每秒 5000 次测量的电光合成器实现安全的 FMCW 激光雷达测距
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-03-28 DOI: 10.1109/LSSC.2025.3555948
Marziyeh Rezaei;Liban Hussein;Alana Dee;Shucheng Fang;Qixuan Lin;Mo Li;Sajjad Moazeni
{"title":"Secure FMCW LiDAR Ranging With an Electro-Optical Synthesizer at 5000 Measurements/s","authors":"Marziyeh Rezaei;Liban Hussein;Alana Dee;Shucheng Fang;Qixuan Lin;Mo Li;Sajjad Moazeni","doi":"10.1109/LSSC.2025.3555948","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3555948","url":null,"abstract":"Frequency-modulated continuous wave (FMCW) LiDAR offers a significant advantage over FMCW RADAR due to its superior lateral resolution, achieving more than a <inline-formula> <tex-math>$1000times $ </tex-math></inline-formula> improvement. However, laser nonlinearities require the use of electro-optical phase-locked loops (EO PLLs), and conventional EO PLL-based FMCW LiDAR systems are susceptible to spoofing attacks. To address this vulnerability, this letter introduces an electro-optical (EO) synthesizer designed to generate FMCW signals with randomly varying chirp rates per frame. The synthesizer incorporates an on-chip SRAM-based physically unclonable function (PUF) fabricated in 180-nm RF CMOS, which generates a device-specific random key to enhance the security of FMCW LiDAR against spoofing attacks. The synthesizer supports four programmable chirp rates: from 8.5 to 12 GHz/ms with a chirp period of <inline-formula> <tex-math>$600~mu $ </tex-math></inline-formula>s, and from 12.75 to 18 GHz/ms with a chirp period of <inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>s, resulting in a <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> increase in generated cloud points compared to existing long-range EO PLL-based FMCW LiDAR systems.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"93-96"},"PeriodicalIF":2.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143830476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 24 V-to-1 V Low Input Current Ripple SC Hybrid Converter With Conducted EMI Noise Precompensation Filter and Current-Modulated Gate-Driver for Automobile Application 带传导EMI噪声预补偿滤波器和电流调制栅极驱动器的24v - 1v低输入纹波SC混合变换器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-03-26 DOI: 10.1109/LSSC.2025.3554811
Yu-Tse Shih;Li-Jen Huang;Xiao-Quan Wu;Wei-Chieh Hung;Tz-Han Hsu;Kuo-Lin Zheng;Ke-Horng Chen;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai
{"title":"A 24 V-to-1 V Low Input Current Ripple SC Hybrid Converter With Conducted EMI Noise Precompensation Filter and Current-Modulated Gate-Driver for Automobile Application","authors":"Yu-Tse Shih;Li-Jen Huang;Xiao-Quan Wu;Wei-Chieh Hung;Tz-Han Hsu;Kuo-Lin Zheng;Ke-Horng Chen;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai","doi":"10.1109/LSSC.2025.3554811","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3554811","url":null,"abstract":"The proposed low input current ripple (LICR) switched-capacitor (SC) hybrid converter effectively minimizes input current ripple by incorporating a precompensation active biasing electromagnetic interference (EMI) filter (PABEF), addressing EMI issues in automotive applications without requiring large external components. In addition, the current-modulation gate driver (CMGD) helps suppress conducted EMI noise at high frequencies. As a result, the LICR achieves a 74% reduction in input current ripple, EMI noise attenuation of 32 dB at low frequencies and 5 dB at high frequencies, and a peak efficiency of 93.3% at <inline-formula> <tex-math>$V_{mathrm { O}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$V_{mathrm { IN}}{=}1.8$ </tex-math></inline-formula>/24.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"89-92"},"PeriodicalIF":2.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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