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IEEE Solid-State Circuits Letters最新文献

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High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit 基于高熵类比的强物理不可克隆函数，面积熵比为166f2 /bit
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-30 DOI: 10.1109/LSSC.2025.3616263
Alessandro Catania;Sebastiano Strangio;Maksym Paliy;Christian Sbrana;Michele Bertozzi;Giuseppe Iannaccone
{"title":"High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit","authors":"Alessandro Catania;Sebastiano Strangio;Maksym Paliy;Christian Sbrana;Michele Bertozzi;Giuseppe Iannaccone","doi":"10.1109/LSSC.2025.3616263","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3616263","url":null,"abstract":"In this letter, we present a high-entropy strong physically unclonable function (PUF) utilizing weak-inversion current mirrors implemented in a standard 65-nm CMOS technology. Each response bit of the proposed PUF relies on the threshold voltage differences of minimum-sized transistors arranged in a <inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula> matrix. The analog operating principle enables encoding at least three effective bits per transistor pair, significantly improving entropy density. Leveraging a bit-masking technique, the design achieves remarkable robustness, attaining a bit error rate (BER) as low as 0.22% even under substantial supply voltage and temperature variations, with less than 10% discarded bits. The presented architecture exhibits a record area-to-entropy ratio of <inline-formula> <tex-math>$166~rm {F^{2}}$ </tex-math></inline-formula>/bit, confirming its suitability for highly secure, compact applications in hardware security.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"309-312"},"PeriodicalIF":2.0,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 一个紧凑的电流复用6mw 66 - 92ghz频率四倍器，峰值功率增加效率5%，谐波抑制> 36dbc，采用22nm FDSOI CMOS
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-24 DOI: 10.1109/LSSC.2025.3614381
Shankkar Balasubramanian;Kristof Vaesen;Piet Wambacq;Carsten Wulff
{"title":"A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS","authors":"Shankkar Balasubramanian;Kristof Vaesen;Piet Wambacq;Carsten Wulff","doi":"10.1109/LSSC.2025.3614381","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3614381","url":null,"abstract":"This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second doubler with high fundamental harmonic rejection. The second doubler based on the nMOS-based push-push architecture uses gain enhancement to achieve a maximum conversion gain of –4 dB for the quadrupler. The quadrupler with an output saturation power (P<inline-formula> <tex-math>${}_{text {sat}}$ </tex-math></inline-formula>) of –2.6 dBm achieves first- to third-harmonic rejections of more than 36 dBc across the 3-dB bandwidth. The compact quadrupler has a core area of 0.09 mm2, while consuming a DC power of 6.2 mW from a 0.8 V supply with an input power of 0 dBm at 20 GHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"301-304"},"PeriodicalIF":2.0,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11178244","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Battery-Free BLE Backscatter Communication Chip for Wearable Systems 一种用于可穿戴系统的无电池BLE反向散射通信芯片
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-22 DOI: 10.1109/LSSC.2025.3612423
Yongling Zhang;Ji Xiong;Junzai Chen;Xiaoyu Li;Jinrui Zuo;Yan Wang;Xiaoyi Wang;Miao Meng
{"title":"A Battery-Free BLE Backscatter Communication Chip for Wearable Systems","authors":"Yongling Zhang;Ji Xiong;Junzai Chen;Xiaoyu Li;Jinrui Zuo;Yan Wang;Xiaoyi Wang;Miao Meng","doi":"10.1109/LSSC.2025.3612423","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3612423","url":null,"abstract":"This letter presents a backscatter chip that features bidirectional communication with commodity bluetooth low-energy (BLE) transceivers. For uplink, the chip reflects a reverse-whitened BLE tone into single-sideband (SSB) GFSK-modulated BLE packets via a proposed replica VCO-based GFSK modulator and an inductor-free SSB reflector. For downlink, the BLE packets are frequency down-converted passively by utilizing a reverse-whitened BLE tone followed by a proposed self-calibrated GFSK demodulator to recover the downlink data at ultralow power with improved robustness. A dual-linearly polarized microstrip patch antenna (DPMPA) is integrated to enable concurrent RF energy harvesting and communication in a wearable form factor. Implemented in 65-nm CMOS, the chip consumes <inline-formula> <tex-math>$1.4~mu $ </tex-math></inline-formula>W for downlink and <inline-formula> <tex-math>$15.8~mu $ </tex-math></inline-formula>W for uplink. Wireless tests demonstrated a 50 cm downlink and >3 m uplink ranges at 20 dBm EIRP.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"297-300"},"PeriodicalIF":2.0,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications Opal：用于全稀疏机器学习应用的16nm粗粒度可重构阵列SoC
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-22 DOI: 10.1109/LSSC.2025.3613245
Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina
{"title":"Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications","authors":"Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina","doi":"10.1109/LSSC.2025.3613245","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3613245","url":null,"abstract":"Sparsity has recently attracted increased attention in the machine learning (ML) community due to its potential to improve performance and energy efficiency by eliminating ineffectual computations. As ML models evolve rapidly, reconfigurable architectures, such as coarse-grained reconfigurable arrays (CGRAs), are being explored to adapt to and accelerate emerging models. Previous CGRA designs have supported unstructured sparsity and reported promising speedups and energy savings for compute-intensive kernels. However, these approaches still face performance bottlenecks when accelerating entire sparse ML networks. In this letter, we identify the primary sources of inefficiency in prior CGRA-based approaches and present Opal, a CGRA SoC with three key contributions: 1) flexible dataflow architecture supporting Gustavson’s dataflow for sparse matrix multiplication; 2) high-throughput sparse hardware primitives; and 3) enhanced processing elements to support mapping all ML operations on the CGRA. As a result, Opal achieves a 66% to 79% reduction in runtime and energy consumption across our evaluated sparse graph neural network benchmarks compared to prior CGRA solutions which only target kernel acceleration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"293-296"},"PeriodicalIF":2.0,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants 一个40.68 mhz， 200-ns沉降有源整流器毫米大小的植入物
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-18 DOI: 10.1109/LSSC.2025.3611484
Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore
{"title":"A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants","authors":"Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore","doi":"10.1109/LSSC.2025.3611484","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3611484","url":null,"abstract":"This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm2 area, resulting in a 118 mW/mm2 power density while integrating the resonance and filter capacitors. The worst-case settling of the ON- and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"305-308"},"PeriodicalIF":2.0,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication 具有异步100/167 Mb/s ASK/FSK全双工通信的栅极驱动器的完全集成电隔离器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-17 DOI: 10.1109/LSSC.2025.3611018
Lucrezia Navarin;Karl Norling;Marco Parenzan;Stefano Ruzzu;Andrea Neviani;Andrea Bevilacqua
{"title":"A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication","authors":"Lucrezia Navarin;Karl Norling;Marco Parenzan;Stefano Ruzzu;Andrea Neviani;Andrea Bevilacqua","doi":"10.1109/LSSC.2025.3611018","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3611018","url":null,"abstract":"A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m HV CMOS technology, covering an area of 2.2 mm2. The system operates from a low 1.5-V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"289-292"},"PeriodicalIF":2.0,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter 一种采用16nm FinFET的四核VCO的19.5 ghz抗辐射次采样锁相环，实现了低于50秒的抖动
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-17 DOI: 10.1109/LSSC.2025.3610901
David Dolt;Samuel Palermo
{"title":"A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter","authors":"David Dolt;Samuel Palermo","doi":"10.1109/LSSC.2025.3610901","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3610901","url":null,"abstract":"This letter presents a radiation-hardened (rad-hard) subsampled phase-locked loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techniques to mitigate single-event-upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL subblock which include a rad-hard charge-pump Gm cell, a pulser circuit with triple modular redundancy (TMR), and a quad-core voltage-controlled oscillator (VCO) with varactor hardening and LC tail filters. Implemented in a 16-nm FinFET process, the PLL consumes 36.5 mW of power and achieves a jitter of 45.82 fs at 19.5 GHz. Testing at a cyclotron facility verifies robust SEU performance up to an LET of 55 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"285-288"},"PeriodicalIF":2.0,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation 一种用于植入式神经刺激的线性动态电压缩放技术及自适应最小电压净空跟踪
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608096
Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma
{"title":"A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation","authors":"Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma","doi":"10.1109/LSSC.2025.3608096","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608096","url":null,"abstract":"This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the linear region under different stimulus currents. Furthermore, a simple mode-switched control is introduced to improve the loop response of charge-pump. The design has been fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process. The DVS technique increases the measured stimulus efficiency up to 52.8% higher than a fixed supply voltage with a peak efficiency of 89.6% in the range of the stimulus current from 0.5 mA to 0.9 mA.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"261-264"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm 一款800GbE PAM-4 PHY收发器，适用于42 dB铜和7 nm直接驱动光学应用
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608134
Chang Liu;Burak Catli;Yong Liu;Anand Vasani;Guansheng Li;Kun Chuai;Lakshmi Rao;Yang Liu;Xin Meng;Jiawen Zhang;Tim He;Batu Dayanik;Vadim Milirud;Meisam Honarvar Nazari;Hyo Gyuem Rhew;Derui Kong;Arvindh Iyer;Nan Wang;Alireza Nilchi;Aminghasem Safarian;Ray Wang;Hyung-Joon Jeon;Xiaochen Yang;Boyu Hu;Jerry Han;Adesh Garg;Kumar Thasari;Heng Zhang;Namik Kocaman;Ali Nazemi;Delong Cui;Afshin Momtaz;Jun Cao
{"title":"An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm","authors":"Chang Liu;Burak Catli;Yong Liu;Anand Vasani;Guansheng Li;Kun Chuai;Lakshmi Rao;Yang Liu;Xin Meng;Jiawen Zhang;Tim He;Batu Dayanik;Vadim Milirud;Meisam Honarvar Nazari;Hyo Gyuem Rhew;Derui Kong;Arvindh Iyer;Nan Wang;Alireza Nilchi;Aminghasem Safarian;Ray Wang;Hyung-Joon Jeon;Xiaochen Yang;Boyu Hu;Jerry Han;Adesh Garg;Kumar Thasari;Heng Zhang;Namik Kocaman;Ali Nazemi;Delong Cui;Afshin Momtaz;Jun Cao","doi":"10.1109/LSSC.2025.3608134","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608134","url":null,"abstract":"This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"281-284"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation 一种38.1 fJ/Bit电容锁存真随机数发生器，具有逆变器自动归零失配和加速评估功能
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608187
Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim
{"title":"A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation","authors":"Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim","doi":"10.1109/LSSC.2025.3608187","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608187","url":null,"abstract":"This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4-V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"265-268"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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