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A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-01-10 DOI: 10.1109/LSSC.2025.3528005
Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao
{"title":"A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique","authors":"Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao","doi":"10.1109/LSSC.2025.3528005","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528005","url":null,"abstract":"A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"45-48"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-01-09 DOI: 10.1109/LSSC.2025.3527533
Ali Ameri;Ali M. Niknejad
{"title":"A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology","authors":"Ali Ameri;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3527533","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3527533","url":null,"abstract":"A single-stage frequency quadrupler operating in the 199–219-GHz frequency range is presented. The quadrupler utilizes a second harmonic trap and recycles the trapped power to generate additional power toward the desired fourth harmonic. The quadrupler has a peak power of −2.54 dBm while consuming 54 mW, resulting in a maximum efficiency <inline-formula> <tex-math>$eta _{mathrm {MAX}}=1.03%$ </tex-math></inline-formula>. The circuit occupies an area of <inline-formula> <tex-math>$370~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times $ </tex-math></inline-formula> <inline-formula> <tex-math>$240~mu $ </tex-math></inline-formula>m, the smallest footprint among the reported sub-THz frequency quadruplers. An on-chip LC oscillator and a tuned buffer provide the input signal to the quadrupler, constituting a fully integrated system.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"37-40"},"PeriodicalIF":2.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-01-08 DOI: 10.1109/LSSC.2025.3527153
Shota Konno;Zachary J. Ellis;Anupam Golder;Sigang Ryu;Daniel Dinu;Avinash Varna;Sanu Mathew;Arijit Raychowdhury
{"title":"A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor","authors":"Shota Konno;Zachary J. Ellis;Anupam Golder;Sigang Ryu;Daniel Dinu;Avinash Varna;Sanu Mathew;Arijit Raychowdhury","doi":"10.1109/LSSC.2025.3527153","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3527153","url":null,"abstract":"This letter describes a delta-sigma ADC-based power-side-channel-attack sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing dual-integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65-nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance ><inline-formula> <tex-math>${=}0.25~Omega $ </tex-math></inline-formula> and a power consumption of <inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>W at 1.0-V operation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"57-60"},"PeriodicalIF":2.2,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2025-01-06 DOI: 10.1109/LSSC.2025.3526877
G. Gangasani;A. Mostafa;A. Singh;D. Storaska;D. Prabakaran;K. Mohammad;M. Baecher;M. Shannon;M. Sorna;M. Wielgos;P. Jenkins;P. Ramakrishna;U. Shukla
{"title":"A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS","authors":"G. Gangasani;A. Mostafa;A. Singh;D. Storaska;D. Prabakaran;K. Mohammad;M. Baecher;M. Shannon;M. Sorna;M. Wielgos;P. Jenkins;P. Ramakrishna;U. Shukla","doi":"10.1109/LSSC.2025.3526877","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3526877","url":null,"abstract":"This letter uses 113-Gb/s PAM4 transceiver in 5-nm CMOS to demonstrate a 1.8-Tb/s chiplet, over die-to-die extremely short-reach (XSR) intrapackage links, in an 8-port configuration. The 16-channels range from 1 to 12 dB of loss at <inline-formula> <tex-math>$F_{textrm {baud}}/2$ </tex-math></inline-formula>. The chiplet performance over these channels is better than <inline-formula> <tex-math>$textrm {BER}lt 10^{-9}$ </tex-math></inline-formula>, while consuming <1.1-pJ/b power and 0.22-mm2 area per lane. The performance targets are achieved using an transceiver equalization strategy which minimizes 0.5-UI ISI by design in the data path and using a LUT-based TX FFE-3 for signal equalization and envelope adaptation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"33-36"},"PeriodicalIF":2.2,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler 具有全动态电流积分采样器的2.6-GS/s 8位时间交错ADC
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-27 DOI: 10.1109/LSSC.2024.3523509
Dengquan Li;Maowen Qian;Depan Li;Hongzhi Liang;Zhangming Zhu
{"title":"A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler","authors":"Dengquan Li;Maowen Qian;Depan Li;Hongzhi Liang;Zhangming Zhu","doi":"10.1109/LSSC.2024.3523509","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3523509","url":null,"abstract":"This letter presents an 8-bit 2.6-GS/s 8-way time-interleaved (TI) analog-to-digital converter (ADC) in 65-nm CMOS. The proposed dynamic current integrating sampler (DCIS) implements the functionality of input buffer and anti-aliasing filter, and eliminates the memory effect caused by parasitic capacitance. It breaks through the limitations of conventional CIS in terms of power consumption, output swing, and bandwidth. A global master sampling network with charge sharing is adopted to alleviate the impact of timing skew. The measured results show that the TI-ADC achieves an SFDR of 50.01 dB and SNDR of 41.29 dB with Nyquist input, respectively. The total power consumption is 28.88 mW, which corresponds to a Walden figure of merit of 117.2 fJ/conv.-step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"29-32"},"PeriodicalIF":2.2,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor 基于级联逆变器的1.48 fm模拟无电容ldo
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-25 DOI: 10.1109/LSSC.2024.3522785
Hing Tai Chen;Xun Liu;Ka Nang Leung
{"title":"A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor","authors":"Hing Tai Chen;Xun Liu;Ka Nang Leung","doi":"10.1109/LSSC.2024.3522785","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3522785","url":null,"abstract":"A capacitorless analog low-dropout regulator (CL-LDO) with cascade-inverter-based pseudo-power transistor is presented in this letter. The proposed architecture supports ultralow-voltage operation, fast transient response, high current efficiency, and high loop gain with low quiescent current along the full load range. The proposed CL-LDO can be easily implemented without any external transient-enhancement circuit. The circuit is fabricated in a 65-nm LP CMOS process with an active area of 0.00782 mm2. The minimum supply voltage can be as low as 0.5 V. The minimum dropout voltage is 20 mV. Under a 1-V supply, the undershoot voltage with 100-mV dropout voltage is 87 mV and settles down within 10 ns when the load current increases from \u0000<inline-formula> <tex-math>$100~boldsymbol {mu }$ </tex-math></inline-formula>\u0000 A to 50 mA within 5-ns edge time. The measured quiescent current is \u0000<inline-formula> <tex-math>$4~boldsymbol {mu }$ </tex-math></inline-formula>\u0000 A. The transient figure of merit is 1.48 fs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"25-28"},"PeriodicalIF":2.2,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142937889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-nm Static-Power-Free Fully Parallel RRAM-Based TD CIM Macro With 1982 TOPS/W/Bit for Edge Applications 用于边缘应用的28nm无静电全并行rram TD CIM微型机，具有1982 TOPS/W/Bit
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-19 DOI: 10.1109/LSSC.2024.3520593
Songtao Wei;Peng Yao;Xinying Guo;Dong Wu;Lu Jie;Qi Qin;Bin Gao;Jianshi Tang;He Qian;Sining Pan;Huaqiang Wu
{"title":"A 28-nm Static-Power-Free Fully Parallel RRAM-Based TD CIM Macro With 1982 TOPS/W/Bit for Edge Applications","authors":"Songtao Wei;Peng Yao;Xinying Guo;Dong Wu;Lu Jie;Qi Qin;Bin Gao;Jianshi Tang;He Qian;Sining Pan;Huaqiang Wu","doi":"10.1109/LSSC.2024.3520593","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3520593","url":null,"abstract":"Analog computing in memory (CIM) based on resistive nonvolatile memory (NVM) has encountered several issues, such as low parallelism, low computing accuracy, and considerable power consumption. In this letter, a temporal unit based on design technology co-optimization (DTCO) for resistive random access memory is proposed for the first time, with the advantage of eliminating dc current and reducing the deviation of mapped weight. A time-domain (TD) array based on the proposed temporal unit features performing fully parallel matrix-vector multiplication (MVM) in a static-power-free manner, without the consideration of IR drop and limited sensing margin (SM). Besides, a low-power time-digital converter (TDC) with local offset elimination further boosts energy efficiency (EF) and computing accuracy. The fabricated 28-nm TD CIM macro achieves a state-of-the-art normalized EF of 1982 and 1387 TOPS/W/bit under 1b-input, ternary-weight and 4b-input, signed 4b-weight, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"21-24"},"PeriodicalIF":2.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultrasensitive Reset-Less Integrator-Based PIN-Diode Receiver With Input Current Control 基于输入电流控制的超灵敏无复位积分器PIN-Diode接收器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-19 DOI: 10.1109/LSSC.2024.3520338
Christoph Gasser;Christoph Ribisch;Simon Michael Laube;Kerstin Schneider-Hornstein;Horst Zimmermann
{"title":"Ultrasensitive Reset-Less Integrator-Based PIN-Diode Receiver With Input Current Control","authors":"Christoph Gasser;Christoph Ribisch;Simon Michael Laube;Kerstin Schneider-Hornstein;Horst Zimmermann","doi":"10.1109/LSSC.2024.3520338","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3520338","url":null,"abstract":"This work presents a novel ultrasensitive integrator-based optical frontend that eliminates the need for a reset network to stabilize the operating point. The proposed method introduces a current source at the input node that compensates the average photocurrent. Eliminating the reset phase for the integrator results in better data rate scalability and PVT robustness without the need for correlated double sampling. The full-custom designed PIN-diode receiver was fabricated in 0.35\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS and characterized. Using a Manchester encoded PRBS15 bit stream, the best sample achieved a sensitivity of \u0000<inline-formula> <tex-math>$mathbf {-52.93}$ </tex-math></inline-formula>\u0000dBm at a wavelength of 642nm, an effective data rate of 50Mb/s and a bit error ratio of \u0000<inline-formula> <tex-math>$mathbf {2cdot 10^{-3}}$ </tex-math></inline-formula>\u0000. This results in a distance of 20.75 dB to the quantum limit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"17-20"},"PeriodicalIF":2.2,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10807184","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions 增强AI加速：具有激活函数的免校准，pvt鲁棒模拟内存中计算宏
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-04 DOI: 10.1109/LSSC.2024.3510679
Hechen Wang;Renzhi Liu;Richard Dorrance;Deepak Dasalukunte;Niranjan Mylarappa Gowda;Brent Carlton
{"title":"Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions","authors":"Hechen Wang;Renzhi Liu;Richard Dorrance;Deepak Dasalukunte;Niranjan Mylarappa Gowda;Brent Carlton","doi":"10.1109/LSSC.2024.3510679","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510679","url":null,"abstract":"Most analog compute-in-memory (ACiM) works only focus on the multiple–accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"9-12"},"PeriodicalIF":2.2,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3 基于单片集成PIN光电二极管的10gb /s光接收机，新型AGC，误码率为-27.1 dBm
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-12-04 DOI: 10.1109/LSSC.2024.3511582
Wenyu Zhou;Larry Tarof;Rony E. Amaya
{"title":"A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3","authors":"Wenyu Zhou;Larry Tarof;Rony E. Amaya","doi":"10.1109/LSSC.2024.3511582","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3511582","url":null,"abstract":"A monolithically integrated optical receiver in InP for 10-Gb/s intensity modulation direct detect (IMDD) application is presented. The sensitivity at the bit error rate (BER) \u0000<inline-formula> <tex-math>$rm 10^{-3}$ </tex-math></inline-formula>\u0000 is measured to be –27.1 dBm. An integrated PIN diode photodetector (PD) minimizes the parasitics caused by wire bonds between the PD and the transimpedance amplifier (TIA). For the first time, electronics and photonics are monolithically integrated into a single InP IC. The avalanche photodetector (APD) is replaced with PIN PD, exhibiting comparable sensitivity and requiring a simple 3.3-V supply voltage. A single transistor voltage-to-current convertor between two cascaded TIAs performs automatic gain control (AGC). A total dynamic gain control of 9 dB has been demonstrated with a dynamic range of more than 17 dB, employing only four transistors and dissipating 8.5 mW. Improved gain peaking extends the operating bandwidth and makes it suitable for higher-speed applications. The power supply rejection ratio (PSRR) exceeds 24 dB without needing on-chip bandgap references.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"13-16"},"PeriodicalIF":2.2,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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