IEEE Solid-State Circuits Letters最新文献_第2页

An Inverter-Based Sampling Front-End Achieving >46-dB SFDR at 50-GHz Input 基于逆变器的采样前端在50 ghz输入下实现>46-dB SFDR

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-18 DOI: 10.1109/LSSC.2025.3552520

Zehang Wu;Chi-Hang Chan;Yan Zhu;Rui P. Martins;Minglei Zhang

引用次数: 0

Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure 紧凑型单级输入输出轨对轨AB级缓冲放大器，具有非对称输出结构

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-18 DOI: 10.1109/LSSC.2025.3551357

Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong

引用次数: 0

A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology 在18A级技术的图形核心上实现的同步13.1 GHz背面谐振时钟网格

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-17 DOI: 10.1109/LSSC.2025.3552251

Ragh Kuttappa;Vinayak Honkote;Amreesh Rao;Gaurav Kamalkar;Kailash Chandrashekar;Eric Finley;Chaitanya Sankuratri;Faran Rafiq;Robert Orton;Nils Hernandez;Anuradha Srinivasan;Tanay Karnik

引用次数: 0

A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications 用于d波段通信的122 GHz无线供电有源反射器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-13 DOI: 10.1109/LSSC.2025.3551244

Michihiro Ide;Keito Yuasa;Sena Kato;Shu Date;Takashi Tomura;Kenichi Okada;Atsushi Shirane

{"title":"A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications","authors":"Michihiro Ide;Keito Yuasa;Sena Kato;Shu Date;Takashi Tomura;Kenichi Okada;Atsushi Shirane","doi":"10.1109/LSSC.2025.3551244","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551244","url":null,"abstract":"This letter introduces an active reflector for D-band communication utilizing 122-GHz wireless power transfer (WPT). The reflector consists of rectifiers with an integrated low-pass filter (LPF), an IF-band power combining network, and an 1-port amplifier composed of a circulator and IF-band amplifiers. The proposed rectifier not only works as an RF-DC converter but also operates as a self-heterodyne mixer by using the 122 GHz WPT signal as a LO. Since the rectifier operates in a fully passive manner, it can simultaneously perform the upconversion and downconversion required for Tx and Rx operations. The IF signal obtained from downconversion is efficiently amplified and then reinput into the IF distributing network and rectifier after 1-port amplifier for upconversion and reflectively transmission in the specular direction. According to probe measurements, the rectifier achieves a power conversion efficiency (PCE) of 12.2% with an input power of 9.3 dBm, and conversion gains of −15.9 and −17.7 dB for Tx and Rx modes, respectively. Additionally, the proposed rectifier supports a data rate of 48 Gb/s with a 64QAM modulation scheme and an 8-GHz bandwidth for both Tx and Rx.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"97-100"},"PeriodicalIF":2.2,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143835458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bi-Directional Near-Ground Current Sensor With Reconfigurable Unidirectional Gains 具有可重构单向增益的双向近地电流传感器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-10 DOI: 10.1109/LSSC.2025.3549495

Yun Hao;Bo Zhou;Xukun Wang;Chunli Huang;Zhihua Wang

引用次数: 0

A Wideband VCO Using a Switchable Inductance Technique and Negative Gₘ Enhancement With Positive Feedback 一种采用可开关电感技术和正反馈负G值增强的宽带压控振荡器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-06 DOI: 10.1109/LSSC.2025.3567309

Yu-Teng Chang;Shau-Chi Ho;Wen-Jie Lin

{"title":"A Wideband VCO Using a Switchable Inductance Technique and Negative Gₘ Enhancement With Positive Feedback","authors":"Yu-Teng Chang;Shau-Chi Ho;Wen-Jie Lin","doi":"10.1109/LSSC.2025.3567309","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3567309","url":null,"abstract":"In this letter, we propose a wideband voltage-controlled oscillator (VCO) that combines a switchable inductor technique and negative transconductance <inline-formula> <tex-math>$(G_{m})$ </tex-math></inline-formula> enhancement with the positive feedback loop. To extend the tuning range (TR) and reduce the frequency overlapping region between two modes, a mathematical analysis for the optimization TR is proposed to resist the frequency gap caused by process variations and implement a wider TR by using the switchable inductor. Furthermore, to compensate for the loss of the switchable inductor, the source-coupled pair provides additional wideband –<inline-formula> <tex-math>$G_{m}$ </tex-math></inline-formula> characteristics to improve the Q value of the entire LC tank across the TR, thereby cooperating with the switchable inductance technique to implement the better phase noise (PN) across all TR. The measured TR is 39.67%, spanning from 10.77 to 16.1 GHz. At 13.19 GHz, the measured PN is –138 dBc/Hz at a 10-MHz offset frequency. The proposed VCO consumes only 10.7 mW of the total DC power. Comparing the proposed VCO to existing designs, these results demonstrate that it has a wider TR, an improved PN, and a higher figure of merit (FoM).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"137-140"},"PeriodicalIF":2.2,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver 300ghz波段36gb /s可扩展二维相控阵CMOS双超外差接收机

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-05 DOI: 10.1109/LSSC.2025.3566726

Satoshi Tanaka;Shinsuke Hara;Kyoya Takano;Akifumi Kasamatsu;Yoshiki Sugimoto;Kunio Sakakibara;Shunichi Kubo;Takeshi Yoshida;Shuhei Amakawa;Minoru Fujishima

{"title":"A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver","authors":"Satoshi Tanaka;Shinsuke Hara;Kyoya Takano;Akifumi Kasamatsu;Yoshiki Sugimoto;Kunio Sakakibara;Shunichi Kubo;Takeshi Yoshida;Shuhei Amakawa;Minoru Fujishima","doi":"10.1109/LSSC.2025.3566726","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3566726","url":null,"abstract":"This letter presents a near-<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/2-antenna-pitch 2-D phased-array CMOS receiver to address the challenge of implementing sub-THz beamforming with the narrow <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/<inline-formula> <tex-math>$2~(approx ~555~mu $ </tex-math></inline-formula>m at 270 GHz) antenna pitch. A double superheterodyne architecture is adopted to reduce the area occupied by the 2-D RX array circuits by locating the E- and H-plane phase control circuits outside the array. Additionally, interpolated feeding is employed to enlarge the area available for the RX circuits by enabling an n-by-n array of RX elements to feed a near-<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/2-pitch (<inline-formula> <tex-math>$2{n}$ </tex-math></inline-formula> – 1)-by-(<inline-formula> <tex-math>$2{n}$ </tex-math></inline-formula> – 1) antenna array composed of main and auxiliary antennas. A 40-nm CMOS prototype with <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> RX elements feeding <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> antenna elements demonstrate beam scanning ranges of approximately ±20° and ±30°in the E- and H-planes, respectively, and achieves 36-Gb/s QPSK signal transmission over a distance of 5 cm.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"133-136"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10985811","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 115.2-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Mismatch Error Shaping for Noninvasive Biomedical Devices 用于非侵入性生物医学设备的具有失配误差整形的115.2 db动态范围两步直接转换前端

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-05 DOI: 10.1109/LSSC.2025.3548453

Yuxuan Chen;Xianzhi Yang;Jiayi Lin;Zilong Liu;Min Zeng;Qi Wu;Mingyi Chen

{"title":"A 115.2-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Mismatch Error Shaping for Noninvasive Biomedical Devices","authors":"Yuxuan Chen;Xianzhi Yang;Jiayi Lin;Zilong Liu;Min Zeng;Qi Wu;Mingyi Chen","doi":"10.1109/LSSC.2025.3548453","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3548453","url":null,"abstract":"This article presents a two-step direct-conversion front-end (Direct-FE) for noninvasive wearable biomedical devices. In the first step, a delta modulator (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> M) with embedded gain is used to implement coarse quantization, while in the second step, a discrete-time sigma delta modulator (DT-<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula> M) is used to realize fine quantization. DC-coupled differential difference amplifier (DDA) with resistor-based digital-to-analog converter (RDAC) is adopted as the input stage. Mismatch error shaping (MES) with reduced silicon area is utilized to suppress the mismatch error of the RDAC. The prototype has been implemented in 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m BCD process and achieves a peak input range of <inline-formula> <tex-math>$7.64~{mathrm {V}_{mathrm {pp}}}$ </tex-math></inline-formula>, an input-referred-noise (IRN) of <inline-formula> <tex-math>$1.59~mu mathrm {V}_{mathrm {RMS}}$ </tex-math></inline-formula>, a corresponding dynamic range (DR) of 115.2 dB, while consuming 2.4-mW power. The real physiological signals recording demonstrates its potential capability for wearable bio-potential acquisition, boosting the wearable and fitness application areas.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"69-72"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator 带动态放大器辅助级联积分器的94.3 db SNDR 184db fms四阶噪声整形SAR ADC

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-02-21 DOI: 10.1109/LSSC.2025.3544649

Kai-Cheng Cheng;Soon-Jyh Chang;Chung-Chieh Chen;Shuo-Hong Hung

引用次数: 0

A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS 基于28nm CMOS片上天线的1.54 pJ/b 80gb /s d波段二维可扩展收发器阵列

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-02-05 DOI: 10.1109/LSSC.2025.3539228

Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad

{"title":"A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS","authors":"Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3539228","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3539228","url":null,"abstract":"This work represents a 140 GHz wideband 2-D scalable phased array in 28-nm bulk CMOS technology. The chip integrates <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> transceiving elements with on-chip antennas and a <inline-formula> <tex-math>$times 16$ </tex-math></inline-formula> LO multiplication chain in <inline-formula> <tex-math>$2.115times 2$ </tex-math></inline-formula>.115 mm2. The elements are forming an RF beamformer while keeping approximately half-wavelength spacing between the elements. The integrated antennas leverage substrate thinning and substrate mode cancellation to boost the array radiation efficiency. The system adopts a superheterodyne transceiver (TRX) architecture with 25 GHz IF center frequency. The proposed work achieves 1.54 pJ/b and 80 Gb/s over-the-air (OTA) using 16-QAM modulation scheme for the overall transmit-receive link. To the best of the authors’ knowledge, this work achieves the highest reported array-level OTA data rate while improving the energy efficiency (pJ/b) by approximately an order of magnitude compared to other D-band transceiver arrays.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"61-64"},"PeriodicalIF":2.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0