IEEE Solid-State Circuits Letters最新文献_第2页

A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications 用于d波段通信的122 GHz无线供电有源反射器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-13 DOI: 10.1109/LSSC.2025.3551244

Michihiro Ide;Keito Yuasa;Sena Kato;Shu Date;Takashi Tomura;Kenichi Okada;Atsushi Shirane

{"title":"A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications","authors":"Michihiro Ide;Keito Yuasa;Sena Kato;Shu Date;Takashi Tomura;Kenichi Okada;Atsushi Shirane","doi":"10.1109/LSSC.2025.3551244","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551244","url":null,"abstract":"This letter introduces an active reflector for D-band communication utilizing 122-GHz wireless power transfer (WPT). The reflector consists of rectifiers with an integrated low-pass filter (LPF), an IF-band power combining network, and an 1-port amplifier composed of a circulator and IF-band amplifiers. The proposed rectifier not only works as an RF-DC converter but also operates as a self-heterodyne mixer by using the 122 GHz WPT signal as a LO. Since the rectifier operates in a fully passive manner, it can simultaneously perform the upconversion and downconversion required for Tx and Rx operations. The IF signal obtained from downconversion is efficiently amplified and then reinput into the IF distributing network and rectifier after 1-port amplifier for upconversion and reflectively transmission in the specular direction. According to probe measurements, the rectifier achieves a power conversion efficiency (PCE) of 12.2% with an input power of 9.3 dBm, and conversion gains of −15.9 and −17.7 dB for Tx and Rx modes, respectively. Additionally, the proposed rectifier supports a data rate of 48 Gb/s with a 64QAM modulation scheme and an 8-GHz bandwidth for both Tx and Rx.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"97-100"},"PeriodicalIF":2.2,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143835458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bi-Directional Near-Ground Current Sensor With Reconfigurable Unidirectional Gains 具有可重构单向增益的双向近地电流传感器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-10 DOI: 10.1109/LSSC.2025.3549495

Yun Hao;Bo Zhou;Xukun Wang;Chunli Huang;Zhihua Wang

引用次数: 0

A 115.2-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Mismatch Error Shaping for Noninvasive Biomedical Devices 用于非侵入性生物医学设备的具有失配误差整形的115.2 db动态范围两步直接转换前端

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-03-05 DOI: 10.1109/LSSC.2025.3548453

Yuxuan Chen;Xianzhi Yang;Jiayi Lin;Zilong Liu;Min Zeng;Qi Wu;Mingyi Chen

{"title":"A 115.2-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Mismatch Error Shaping for Noninvasive Biomedical Devices","authors":"Yuxuan Chen;Xianzhi Yang;Jiayi Lin;Zilong Liu;Min Zeng;Qi Wu;Mingyi Chen","doi":"10.1109/LSSC.2025.3548453","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3548453","url":null,"abstract":"This article presents a two-step direct-conversion front-end (Direct-FE) for noninvasive wearable biomedical devices. In the first step, a delta modulator (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> M) with embedded gain is used to implement coarse quantization, while in the second step, a discrete-time sigma delta modulator (DT-<inline-formula> <tex-math>$Sigma Delta $ </tex-math></inline-formula> M) is used to realize fine quantization. DC-coupled differential difference amplifier (DDA) with resistor-based digital-to-analog converter (RDAC) is adopted as the input stage. Mismatch error shaping (MES) with reduced silicon area is utilized to suppress the mismatch error of the RDAC. The prototype has been implemented in 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m BCD process and achieves a peak input range of <inline-formula> <tex-math>$7.64~{mathrm {V}_{mathrm {pp}}}$ </tex-math></inline-formula>, an input-referred-noise (IRN) of <inline-formula> <tex-math>$1.59~mu mathrm {V}_{mathrm {RMS}}$ </tex-math></inline-formula>, a corresponding dynamic range (DR) of 115.2 dB, while consuming 2.4-mW power. The real physiological signals recording demonstrates its potential capability for wearable bio-potential acquisition, boosting the wearable and fitness application areas.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"69-72"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator 带动态放大器辅助级联积分器的94.3 db SNDR 184db fms四阶噪声整形SAR ADC

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-02-21 DOI: 10.1109/LSSC.2025.3544649

Kai-Cheng Cheng;Soon-Jyh Chang;Chung-Chieh Chen;Shuo-Hong Hung

引用次数: 0

A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS 基于28nm CMOS片上天线的1.54 pJ/b 80gb /s d波段二维可扩展收发器阵列

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-02-05 DOI: 10.1109/LSSC.2025.3539228

Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad

{"title":"A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS","authors":"Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3539228","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3539228","url":null,"abstract":"This work represents a 140 GHz wideband 2-D scalable phased array in 28-nm bulk CMOS technology. The chip integrates <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> transceiving elements with on-chip antennas and a <inline-formula> <tex-math>$times 16$ </tex-math></inline-formula> LO multiplication chain in <inline-formula> <tex-math>$2.115times 2$ </tex-math></inline-formula>.115 mm2. The elements are forming an RF beamformer while keeping approximately half-wavelength spacing between the elements. The integrated antennas leverage substrate thinning and substrate mode cancellation to boost the array radiation efficiency. The system adopts a superheterodyne transceiver (TRX) architecture with 25 GHz IF center frequency. The proposed work achieves 1.54 pJ/b and 80 Gb/s over-the-air (OTA) using 16-QAM modulation scheme for the overall transmit-receive link. To the best of the authors’ knowledge, this work achieves the highest reported array-level OTA data rate while improving the energy efficiency (pJ/b) by approximately an order of magnitude compared to other D-band transceiver arrays.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"61-64"},"PeriodicalIF":2.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.86 mW 17 fA/√Hz, 129-dB DR Current-Sensing Front-End for Under-Display Ambient Light Sensor With Zero-Compensated Logarithmic TIA

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-13 DOI: 10.1109/LSSC.2025.3528962

Liheng Liu;Tianxiang Qu;Hao Li;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu

{"title":"A 0.86 mW 17 fA/√Hz, 129-dB DR Current-Sensing Front-End for Under-Display Ambient Light Sensor With Zero-Compensated Logarithmic TIA","authors":"Liheng Liu;Tianxiang Qu;Hao Li;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3528962","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528962","url":null,"abstract":"This letter presents a low-noise, power-efficient, and pulsatile-interference stabilized photocurrent readout circuit for under-display ambient light sensors (ALS). To achieve pA-level input noise and seven decades of input current dynamic range (DR) simultaneously, a logarithmic transimpedance amplifier (TIA) with a diode-connected MOS feedback is set as the first stage of the ALS. An auto-tracking zero, implemented in the amplifier of the TIA, improves the phase-margin and reduces the settling time against pulsatile interference without extra power consumption. The TIA output is then quantized by a first-order 9-bit incremental delta-sigma modulator. Fabricated in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the proposed ALS achieves the best-in-the-class input-referred current noise of <inline-formula> <tex-math>$0.6~rm {pA}_{mathrm {rms}}$ </tex-math></inline-formula> within a 400-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s readout time. The total input range of <inline-formula> <tex-math>$1.7~rm {pA}_{mathrm {PP}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$5~mu rm {A}_{mathrm {PP}}$ </tex-math></inline-formula> corresponds to a DR of 129 dB while consuming 0.86 mW at a 1.8-V supply.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"49-52"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

20–26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-13 DOI: 10.1109/LSSC.2025.3529347

Jin-Fa Chang

{"title":"20–26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner","authors":"Jin-Fa Chang","doi":"10.1109/LSSC.2025.3529347","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3529347","url":null,"abstract":"We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/4 spiral transmission line inductors based on a <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage (<inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"53-56"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 23–28-GHz Doherty Power Amplifier With a PVT Insensitive Power Detection for Adaptive Biasing

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-10 DOI: 10.1109/LSSC.2025.3528055

Yahia Ibrahim;Ali Niknejad

{"title":"A 23–28-GHz Doherty Power Amplifier With a PVT Insensitive Power Detection for Adaptive Biasing","authors":"Yahia Ibrahim;Ali Niknejad","doi":"10.1109/LSSC.2025.3528055","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528055","url":null,"abstract":"This letter presents a compact Doherty power amplifier (PA) featuring a single transformer balun. A novel envelope power detector architecture is introduced for high-bandwidth (BW) adaptive biasing, that is, insensitive to process-voltage–temperature (PVT) variations. The measured PA attains a saturated power <inline-formula> <tex-math>$(mathbf {P_{mathrm { sat}}})$ </tex-math></inline-formula> exceeding 20.2 dBm and a power gain of 19.5 dB across the frequency range of 23–28 GHz. Moreover, it exhibits a peak power added efficiency (PAE) of 38% and a 6-dB power back-off (PBO) PAE of 27% at 25 GHz. The proposed adaptive biasing scheme enables a modulation BW of up to 800 MHz for a 64-QAM signal. Under this setting, the average output power <inline-formula> <tex-math>$(mathbf {P_{avg}})$ </tex-math></inline-formula> is measured at 11.3 dBm with an RMS error vector magnitude (EVM) of −24.5 dB and an average PAE of 15.5%. The PA is fabricated in Global Foundries 45-nm-SOI technology with a compact area of 0.27 mm2. To the best of the authors’ knowledge, this work is the first to demonstrate robust performance for Doherty PAs across PVT variations.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"41-44"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-10 DOI: 10.1109/LSSC.2025.3528005

Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao

引用次数: 0

A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-09 DOI: 10.1109/LSSC.2025.3527533

Ali Ameri;Ali M. Niknejad

引用次数: 0