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Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler 使用紧凑型短路耦合器的宽带 GaN MMIC Doherty 功率放大器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-01 DOI: 10.1109/LSSC.2024.3471855
Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng
{"title":"Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler","authors":"Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng","doi":"10.1109/LSSC.2024.3471855","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3471855","url":null,"abstract":"In this letter, a broadband gallium nitride (GaN) monolithic microwave integrated circuit Doherty power amplifier (DPA) using a compact short-circuited coupler (CSC) is presented. To enhance the bandwidth and reduce the size of integrated DPA, the conventional \u0000<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>\u0000/2 transmission line in the peaking output matching network is replaced by the CSC structure. Detailed theoretical analysis and design procedures are provided. Based on the proposed solution, a 5.1–7.2-GHz DPA is designed using a 0.12-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaN HEMT process. The fractional bandwidth (FBW) is 34.1%. The measurement results show a saturated output power of 37.2–39 dBm and a 6-dB back-off drain efficiency of 38.4%–50.5% across the design bands with a chip size of \u0000<inline-formula> <tex-math>$2.6times 2$ </tex-math></inline-formula>\u0000.6 mm. The adjacent channel power ratio (ACPR) under 100-MHz single-carrier 64 QAM modulation signal with a 6-dB peak-to-average power ratio (PAPR) excitation is better than −45 dBc with digital predistortion (DPD).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"307-310"},"PeriodicalIF":2.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12 V Compliant Multichannel Dual Mode Neural Stimulator With 0.004% Charge Mismatch and a 4×VDD Tolerant On-Chip Discharge Switch in Low-Voltage CMOS 符合 12 V 标准的多通道双模式神经刺激器，电荷失配率为 0.004%，采用低压 CMOS，具有 4×VDD 容限的片上放电开关
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-25 DOI: 10.1109/LSSC.2024.3467341
Thanh Dat Nguyen;Alessandro Maggi;Gianluca Lazzi;Constantine Sideris
{"title":"A 12 V Compliant Multichannel Dual Mode Neural Stimulator With 0.004% Charge Mismatch and a 4×VDD Tolerant On-Chip Discharge Switch in Low-Voltage CMOS","authors":"Thanh Dat Nguyen;Alessandro Maggi;Gianluca Lazzi;Constantine Sideris","doi":"10.1109/LSSC.2024.3467341","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3467341","url":null,"abstract":"This letter presents a 12 V-compliant 4-channel neural stimulator fabricated in a low-voltage bulk CMOS process. Arrays of current memory cells are used to implement anodic and cathodic current sources to generate anodic and cathodic current ratios that are robust to process-voltage-temperature variations. A novel, fully integrated discharge switch is presented that tolerates an output voltage up to \u0000<inline-formula> <tex-math>$4times V_{DD}$ </tex-math></inline-formula>\u0000, which is the highest reported for low-voltage bulk CMOS monopolar stimulators. The proposed neural stimulator can operate in both constant current mode (CCM) with a \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000-1.2 mA output current range and constant voltage mode (CVM) with a 1–11 V output voltage range. The output waveform is fully programmable, including cathodic and anodic amplitudes and ratios designed to have excellent charge balancing with only 0.004% charge mismatch.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"283-286"},"PeriodicalIF":2.2,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator 基于 14 纳米 MRAM 的多比特模拟内存计算，可对 72 个基于宏的加速器进行过程变化校准
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-23 DOI: 10.1109/LSSC.2024.3465595
Sungmeen Myung;Seok-Ju Yun;Minje Kim;Wooseok Yi;Jaehyuk Lee;Jangho An;Kyoung-Rog Lee;Chang-Woo Shin;Seungchul Jung;Soonwan Kwon
{"title":"A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator","authors":"Sungmeen Myung;Seok-Ju Yun;Minje Kim;Wooseok Yi;Jaehyuk Lee;Jangho An;Kyoung-Rog Lee;Chang-Woo Shin;Seungchul Jung;Soonwan Kwon","doi":"10.1109/LSSC.2024.3465595","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3465595","url":null,"abstract":"This letter presents an analog in-memory computing (IMC) macro utilizing 14 nm MRAM technology. To facilitate energy-efficient high-throughput multiply accumulate (MAC) operations, a multi-bit weight is introduced using stacked magnetic tunnel junction architecture and an analog bit-parallel MAC (ABP-MAC) scheme is proposed. This approach delivers 3.3 times better TOPS/mm2 than the state-of-the-art MRAM-based IMC macro. Additionally, a comprehensive calibration technique significantly improves computational accuracy across 72 IMC macros. The proposed IMC macro achieves 18.29 TOPS/mm2 and 340.8 TOPS/W with 1-bit normalization and classification accuracy of 90.2% with the Google speech commands dataset.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"295-298"},"PeriodicalIF":2.2,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142430726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update S2D-CIM：基于 SRAM 的收缩式内存数字计算框架，采用多米诺数据路径，支持灵活的矢量操作和二维权重更新
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-19 DOI: 10.1109/LSSC.2024.3463697
Meng Wu;Wenjie Ren;Peiyu Chen;Wentao Zhao;Tianyu Jia;Le Ye
{"title":"S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update","authors":"Meng Wu;Wenjie Ren;Peiyu Chen;Wentao Zhao;Tianyu Jia;Le Ye","doi":"10.1109/LSSC.2024.3463697","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3463697","url":null,"abstract":"In this letter, we propose an SRAM-based systolic digital compute-in-memory (S2D-CIM) framework which enables flexible input dataflow and mapping strategy to enhance the effective energy efficiency (EE), area efficiency, and writing bandwidth for practical CIM with innovations: 1) multistage domino data path (DDP); 2) a configurable asynchronous timing scheme; and 3) a 2-D burst writing scheme. The proposed S2D-CIM is fabricated using TSMC 22-nm technology and achieves 9.19 and 24.4 TOPS/W peak EE in systolic mode and broadcast mode, respectively, at full precision of 8-bit input, 8-bit weight, and 21-bit output. Compared with state of the arts, it achieves \u0000<inline-formula> <tex-math>$1.67times $ </tex-math></inline-formula>\u0000 effective EE improvement. Thanks to reusing introduced DDP, fast 2-D weight update is realized and gains 1.187 Tb/s writing bandwidth, which is \u0000<inline-formula> <tex-math>$14.3times $ </tex-math></inline-formula>\u0000 better than that of normal SRAM macro with the same capacity.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"291-294"},"PeriodicalIF":2.2,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Reconfigurable Floating-Point Compute-in-Memory With Analog Exponent Preprocesses 带模拟指数预处理的可重构浮点内存计算器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-18 DOI: 10.1109/LSSC.2024.3463208
Pengyu He;Yuanzhe Zhao;Heng Xie;Yang Wang;Shouyi Yin;Li Li;Yan Zhu;Rui P. Martins;Chi-Hang Chan;Minglei Zhang
{"title":"A Reconfigurable Floating-Point Compute-in-Memory With Analog Exponent Preprocesses","authors":"Pengyu He;Yuanzhe Zhao;Heng Xie;Yang Wang;Shouyi Yin;Li Li;Yan Zhu;Rui P. Martins;Chi-Hang Chan;Minglei Zhang","doi":"10.1109/LSSC.2024.3463208","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3463208","url":null,"abstract":"This letter presents a reconfigurable floating-point compute-in-memory (FP-CIM) macro that preprocesses the exponent in the analog domain, enhancing the energy efficiency of edge devices for the floating-point (FP) inference. The presented FP-CIM macro supports FP8 inference, while can be configured to BP16 precision in a segmented computation manner. Furthermore, a time-domain analog-to-digital converter facilitates the analog compute-in-memory (CIM) macro while improving energy efficiency by sharing the counter and quantizing in a coarse-fine structure. Fabricated in a 28-nm CMOS process, the presented FP-CIM macro achieves 314.6-TFLOPS/W energy efficiency and 12.13-TFLOPS/mm2 area efficiency at the FP8 mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"271-274"},"PeriodicalIF":2.2,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fully Integrated Dynamic-Voltage-Scaling Stimulator IC for Cochlear Implants 用于人工耳蜗的全集成动态电压缩放刺激器集成电路
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-17 DOI: 10.1109/LSSC.2024.3462559
Kim-Hoang Nguyen;Quyet Nguyen;Quynh-Trang Nguyen;Thanh-Tung Vu;Woojin Ahn;Loan Pham-Nguyen;Hanh-Phuc Le;Minkyu Je
{"title":"A Fully Integrated Dynamic-Voltage-Scaling Stimulator IC for Cochlear Implants","authors":"Kim-Hoang Nguyen;Quyet Nguyen;Quynh-Trang Nguyen;Thanh-Tung Vu;Woojin Ahn;Loan Pham-Nguyen;Hanh-Phuc Le;Minkyu Je","doi":"10.1109/LSSC.2024.3462559","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3462559","url":null,"abstract":"A fully integrated dynamic-voltage-scaling stimulator IC, consisting of a novel reconfigurable supply modulator (RSM) and 12 high-voltage-tolerant channel drivers, for cochlear implants, is presented, utilizing a 180-nm standard CMOS process. The RSM is designed to adaptively generate one of four supply voltage levels ranging from 2.6 to 11.3 V, effectively stimulating the cochlea with varying electrode-tissue-interface impedance and stimulus currents while offering improved power efficiency. The channel driver design is miniaturized to support high-channel-count applications within a single IC. Additional excessive current protection is implemented to ensure charge balancing between biphasic stimulating pulses, complementing the electrode-shorting technique.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"275-278"},"PeriodicalIF":2.2,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Computational Digital LDO With Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application 面向移动 SoC 应用的带分布式电源门开关和基于时间的快速瞬态控制器的计算型数字 LDO
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-16 DOI: 10.1109/LSSC.2024.3461158
Dongha Lee;Seki Kim;Takahiro Nomiyama;Dong-Hoon Jung;Dongsu Kim;Jongwoo Lee
{"title":"A Computational Digital LDO With Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application","authors":"Dongha Lee;Seki Kim;Takahiro Nomiyama;Dong-Hoon Jung;Dongsu Kim;Jongwoo Lee","doi":"10.1109/LSSC.2024.3461158","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3461158","url":null,"abstract":"This letter introduces a 10 A computational digital LDO (CDLDO) for mobile SoC application specifically targeting a big CPU core. The proposed CDLDO eliminates the power-FET area overhead by reusing power gating switches (PGSs) already distributed throughout the entire CPU. The CDLDO employs a time-based exponential control (TEC) with a slope detector to achieve fast-transient response and improve stability. Furthermore, a step-back and a negative-step control are introduced to mitigate the effect of the propagation delay between the controller and the PGSs. Additionally, a pre-computational scheme significantly reduces calculation time and relaxes timing constraints during synthesis. The proposed CDLDO is implemented in 3 nm GAAFET CMOS process. An implemented IC of eight distributed CDLDO units provides a maximum load current of 10 A with a current density of 263 A/mm2. The CDLDO shows 94 mV droop under 6.5 A/1 ns load transition.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"287-290"},"PeriodicalIF":2.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An X-Band Expandable Reconfigurable 1:2 Power Divider Switch for Switched Beam-Forming Networks in 0.10-µm GaAs Process 0.10µm GaAs 工艺中用于交换式波束成形网络的 X 波段可扩展可重构 1:2 功率分配器开关
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-11 DOI: 10.1109/LSSC.2024.3458453
Yicheng Wang;Zhaowu Wang;Zhenyu Wang;Xiaochen Tang;Yong Wang
{"title":"An X-Band Expandable Reconfigurable 1:2 Power Divider Switch for Switched Beam-Forming Networks in 0.10-µm GaAs Process","authors":"Yicheng Wang;Zhaowu Wang;Zhenyu Wang;Xiaochen Tang;Yong Wang","doi":"10.1109/LSSC.2024.3458453","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3458453","url":null,"abstract":"In this letter, an X-band expandable reconfigurable 1:2 power divider switch (PDSW) is proposed for switched beam-forming networks. A switched inductor-artificial transmission line (SI-ATL) is proposed. With proper switch logic, the SI-ATL features two types of transmission line (TL): 1) a \u0000<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>\u0000/4 TL of \u0000<inline-formula> <tex-math>$50sqrt {2} ; Omega $ </tex-math></inline-formula>\u0000 and 2) a TL of \u0000<inline-formula> <tex-math>$50 ; Omega $ </tex-math></inline-formula>\u0000. This enables the PDSW to realize three port states of two corresponding modes, including single-pole–double-throw (SPDT) mode and power divider (PD) mode. The PDSW has the ability to be expanded to an N-stage 1:\u0000<inline-formula> <tex-math>$2^{N}$ </tex-math></inline-formula>\u0000 matrix with \u0000<inline-formula> <tex-math>$2^{2^{N}} - 1$ </tex-math></inline-formula>\u0000 states. The proposed design is fabricated with a 0.10-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaAs pHEMT process. The measurement results show a \u0000<inline-formula> <tex-math>$leq 1$ </tex-math></inline-formula>\u0000.2-dB insertion loss (IL), a \u0000<inline-formula> <tex-math>$geq $ </tex-math></inline-formula>\u0000 10-dB return loss (RL), and a \u0000<inline-formula> <tex-math>$geq 40$ </tex-math></inline-formula>\u0000-dBm input 3rd-order intercept points (IIP3), in both modes. The isolation is 27–32 dB for SPDT mode and 14–31 dB for PD mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"303-306"},"PeriodicalIF":2.2,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142430743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI 基于 SiPh 的 112 Gb/s、-10 dBm 灵敏度、+5 dBm 过载接收器前端，采用 22-nm FDSOI 封装
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-11 DOI: 10.1109/LSSC.2024.3457775
Mahdi Parvizi;Bahar Jalali;Toshi Omori;John Rogers;Li Chen;Long Chen;Ricardo Aroca
{"title":"A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI","authors":"Mahdi Parvizi;Bahar Jalali;Toshi Omori;John Rogers;Li Chen;Long Chen;Ricardo Aroca","doi":"10.1109/LSSC.2024.3457775","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3457775","url":null,"abstract":"This letter demonstrates a Si-Photonic (SiPh)-based 112 Gb/s PAM4 optical receiver frontend using novel single-ended transimpedance amplifier (TIA) architecture that achieves −10 and +5 dBm input optical modulation amplitude (OMA) sensitivity and overload, respectively. To achieve that an overload mitigation circuit is proposed to break the tradeoff between noise and linearity of the shunt feedback CMOS TIAs. The TIA is optimized to provide the best sensitivity and linearity performance at minimum and maximum input OMA, respectively. Implemented in 22-nm FDSOI technology, and designed for 112 Gb/s PAM4 optical links, the TIA achieves more than +15 dBm OMA range with 11 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz input referred noise while burning only 155 mW from an 1.8-V supply.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"263-266"},"PeriodicalIF":2.2,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fully Integrated 5510-μm² Process Monitor and Threshold Voltage Extractor Circuit in 28 nm 28 纳米全集成 5510-μm² 工艺监控器和阈值电压提取电路
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-11 DOI: 10.1109/LSSC.2024.3457768
Ido Shpernat;Asaf Feldman;Joseph Shor
{"title":"A Fully Integrated 5510-μm² Process Monitor and Threshold Voltage Extractor Circuit in 28 nm","authors":"Ido Shpernat;Asaf Feldman;Joseph Shor","doi":"10.1109/LSSC.2024.3457768","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3457768","url":null,"abstract":"A new architecture of an on-die process monitor circuit is demonstrated in 28 nm. The proposed circuit can extract the threshold voltage, \u0000<inline-formula> <tex-math>$V_{mathrm { TH,}}$ </tex-math></inline-formula>\u0000 and random mismatch of a transistor using multiple extraction methods, including the second derivative method. A sigma-delta modulator analog-to-digital converter samples the output to enable on-die processing of the results. A \u0000<inline-formula> <tex-math>$V_{mathrm { DS}}$ </tex-math></inline-formula>\u0000 voltage control loop enables \u0000<inline-formula> <tex-math>$V_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 extraction in both the linear and saturation regions of the device. The circuit has a compact area of \u0000<inline-formula> <tex-math>$5510~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"279-282"},"PeriodicalIF":2.2,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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