IEEE Solid-State Circuits Letters最新文献_第2页

A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue 10.2 V 8通道神经刺激器，在90%电流范围内具有几乎恒定的效率和基于TDM adc的一次电荷平衡，残余小于6 mV

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-12 DOI: 10.1109/LSSC.2026.3653014

Alin Thomas Tharakan;Cong Huang;Yiheng Fu;Horacio Londoño Ramírez;Stéphanie P. Lacour;Mahsa Shoaran

引用次数: 0

Dual-Band Voltage-Controlled Oscillator for CB and HF RFID Bands in a Flexible IGZO Technology 柔性IGZO技术中用于CB和HF RFID频段的双频压控振荡器

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-12 DOI: 10.1109/LSSC.2026.3651909

Lautaro N. Petrauskas;Bahman K. Boroujeni;Frank Ellinger

{"title":"Dual-Band Voltage-Controlled Oscillator for CB and HF RFID Bands in a Flexible IGZO Technology","authors":"Lautaro N. Petrauskas;Bahman K. Boroujeni;Frank Ellinger","doi":"10.1109/LSSC.2026.3651909","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3651909","url":null,"abstract":"In this work, a cross-coupled voltage-controlled oscillator (VCO) for the high frequency RFID and citizen bands (CBs) is investigated, and implemented on a flexible Indium gallium zinc oxide thin film transistor (TFT) technology. To circumvent the challenges of integrating passive components in this frequency range and minimize the circuit’s footprint, the resonant tank is designed as a parallel connection of an active inductor with a metal oxide semiconductor capacitor - yielding a total area of <inline-formula> <tex-math>$mathrm {200~mu text {m} }$ </tex-math></inline-formula> by <inline-formula> <tex-math>$mathrm {330~mu text {m} }$ </tex-math></inline-formula>. The VCO can operate in the CB mode at 10 V power supply, boasting a tuning range from 26.9 MHz to 27.7 MHz and a dc power of 1.93 mW, or in the RFID mode from a 4 V supply, obtaining a 12.9 MHz - 13.6 MHz range at <inline-formula> <tex-math>$mathrm {140~mu text {W} }$ </tex-math></inline-formula> dc power. To the best of the authors’ knowledge, this circuit possesses the highest figure-of-merit (frequency/total power), and overall highest oscillation frequency for VCOs reported up to date in comparable technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"33-36"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications 使用全局定时器架构的激光雷达应用中具有0.056%像素对像素变化的1×32 TDC阵列

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-12 DOI: 10.1109/LSSC.2026.3652323

Hsi-Hao Huang;Zong-Rui Cao;Ying-Ying Cheng;Jia-Yu Lin;Chen-Yi Lee

{"title":"A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications","authors":"Hsi-Hao Huang;Zong-Rui Cao;Ying-Ying Cheng;Jia-Yu Lin;Chen-Yi Lee","doi":"10.1109/LSSC.2026.3652323","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652323","url":null,"abstract":"This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the entire sensing array, which is challenging due to process, voltage, and temperature (PVT) variations. To mitigate this issue, we propose a TDC array architecture featuring a single global timer (GT) circuit that controls the entire array. The GT comprises a differential gated ring oscillator (DGRO)-based all-digital frequency-locked loop (ADFLL) and a 16-to-5 encoder, which drives 32 time-sampling circuits through a buffer tree. The ADFLL ensures precise and uniform timing resolution over the measurement period, while the encoder and buffer tree ensure that the fine timing signal is distributed to the entire TDC array with minimal PPV. The total number of TDC output bits is 12, and the effective number of bits (ENOB) is 11.68. Measurement results indicate a PPV of 0.056%, a differential nonlinearity (DNL) of–0.99/+ 2.53 LSB, an integral nonlinearity (INL) of–2.01/+ 5.21 LSB, a resolution of 49.48 ps, and a full-scale range (FSR) of 202.65 ns.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"41-44"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference 基于低功耗乘加单元和动态稀疏自适应配置的边缘人工智能近似数字CIM宏

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-12 DOI: 10.1109/LSSC.2026.3652570

Xiaofeng Li;Yi Zhan;Purui Zhu;Rui Zhou;Jiayin Song;Heng You;Yumei Zhou;Shushan Qiao

引用次数: 0

A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology 在Intel 18a带状场效应管技术中，一种基于独立内存电压交叉的辅助开关电路，用于可靠和高效的过程跟踪内存Vmin改进

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-12 DOI: 10.1109/LSSC.2026.3652110

Saroj Satapathy;Amlan Ghosh;John Riley;Jalal Quadri;Jaydeep Kulkarni;Feroze Merchant

{"title":"A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology","authors":"Saroj Satapathy;Amlan Ghosh;John Riley;Jalal Quadri;Jaydeep Kulkarni;Feroze Merchant","doi":"10.1109/LSSC.2026.3652110","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652110","url":null,"abstract":"Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various static random access memory arrays, limiting their effectiveness. This restricts the power and area benefits that could be gained from an in-situ, memory circuit-assist enable/disable mechanism. To address this, we propose a novel voltage crossover-based memory assist switching circuit implemented in Intel 18A-RibbonFET technology featuring backside power delivery. Its <inline-formula> <tex-math>$150times $ </tex-math></inline-formula> area efficiency enables independent placement within memory blocks, offering 19% array-level power and 17% performance improvements. Silicon measurements show tight variation control and strong simulation correlation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"37-40"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Cryo-CMOS Smart Temperature Sensor for the Ultrawide Temperature Range From 5 K to 296 K Cryo-CMOS智能温度传感器，适用于5 K至296 K的超宽温度范围

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-02 DOI: 10.1109/LSSC.2025.3650657

D. Cerviño Fungueiriño;L. A. Enthoven;J. van Staveren;M. Babaie;F. Sebastiano

引用次数: 0

HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro HyFPCiM：一个65nm 417 μ w错误敏感的FP8内存中计算宏

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-04-29 DOI: 10.1109/LSSC.2026.3688988

Gaurav Kumar K;Yatharth Agarwal;Kaushik Roy

{"title":"HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro","authors":"Gaurav Kumar K;Yatharth Agarwal;Kaushik Roy","doi":"10.1109/LSSC.2026.3688988","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3688988","url":null,"abstract":"This letter presents HyFPCiM, a 65-nm FP8 compute-in-memory (CiM) macro that enables sub-mW floating-point (FP) inference using error-sensitivity-aware FP partitioning (EAP). EAP maps exponent processing to a digital CiM (DCiM) path and mantissa accumulation to an analog CiM (ACiM), avoiding the power- and area-intensive adder-tree-based accumulation used in prior FP-CiM designs. The proposed DCiM employs dual-rail inverter-based sensing for exponent processing, while the ACiM path performs preanalog-to-digital conversion (ADC) charge-domain accumulation using switched-capacitor (SC) circuits. By amortizing one ADC conversion across eight multiply-and-accumulate (MAC) units, the proposed ACiM reduces ADC energy by <inline-formula> <tex-math>$8times $ </tex-math></inline-formula>, ADC + transimpedance amplifier (TIA) power by 75%, and total macro power by 31% versus ADC-first designs. Fabricated in TSMC 65-nm, HyFPCiM consumes <inline-formula> <tex-math>$417~mu $ </tex-math></inline-formula>W at 1 V and 50 MHz, achieves 40 GFLOPS/W, and incurs < 0.55% accuracy loss across multiple classification workloads. To the best of our knowledge, HyFPCiM achieves the lowest reported power among silicon-measured FP-CiM macros.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"146-149"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147937492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 7-Level 18-Wire-State Trio-Signaling Transmitter for MIPI C-PHY 3.0 Interfaces 用于MIPI C-PHY 3.0接口的7级18线态三路信号发送器

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-11 DOI: 10.1109/LSSC.2026.3672642

Junyeong Lee;Myeongjin Oh;Kiwoon Kim;Jung-Hoon Chun

引用次数: 0

A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC 带有动态阈值DTC的9ghz数字分数n锁相环

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-20 DOI: 10.1109/LSSC.2026.3725284

Daxu Zhang;Yuncheng Zhang;Zezheng Liu;Yuang Xiong;Wenqian Wang;Duo Li;Minzhe Tang;Dongfan Xu;Dingxin Xu;Kazuaki Kunihiro;Hiroyuki Sakai;Kenichi Okada

引用次数: 0

A 1.1-nJ/Conversion RC-Discharge-Based Resistance Sensor With ±0.65% (3σ) 1 -Point Trimmed Inaccuracy in 0.18-μm CMOS Technology 基于0.18 μm CMOS技术的1.1 nj /转换rc放电电阻传感器，误差为±0.65% (3σ) 1点

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-25 DOI: 10.1109/LSSC.2026.3677301

Mu Wu;Yihang Cheng;Xingli Cui;Sining Pan;Huaqiang Wu

引用次数: 0