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IEEE Solid-State Circuits Letters最新文献

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Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions 串联三阱型低寄生MOS电容器的设计与验证
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608282
Zhendong Li;Yongjuan Shi;Yifan Jiang;Chen Hu;Junting Chen;Mengyuan Hua;Xun Liu;Junmin Jiang
{"title":"Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions","authors":"Zhendong Li;Yongjuan Shi;Yifan Jiang;Chen Hu;Junting Chen;Mengyuan Hua;Xun Liu;Junmin Jiang","doi":"10.1109/LSSC.2025.3608282","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608282","url":null,"abstract":"This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"277-280"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS 1.53 GSamples/s 40nm CMOS噪声发生器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-02 DOI: 10.1109/LSSC.2025.3605369
Cheng-Bin Chen;Tsung Chen;Yuan-Hao Huang
{"title":"24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS","authors":"Cheng-Bin Chen;Tsung Chen;Yuan-Hao Huang","doi":"10.1109/LSSC.2025.3605369","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3605369","url":null,"abstract":"This letter presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG with Box-Muller modules to produce Gaussian noise signals. This letter also analyzes the impact of step size on the infinite divergence phenomenon and performs the NIST test to ensure CRNG’s mathematical stability and reliability. The chip was designed and fabricated using TSMC 40 nm CMOS technology. The proposed CRNG chip achieves a throughput of 24.86 Gb/s at a maximum clock frequency of 259 MHz, with a core power consumption of 17.82 mW and an energy efficiency of 0.717 pJ/bit. This performance achieves the highest throughput among state-of-the-art ASIC-based true RNGs (TRNGs). Additionally, the proposed processor achieves a throughput of 1.53 Gsamples/s with a clock frequency of 255 MHz, a core power consumption of 62.73 mW, and an energy efficiency of 41 pJ/sample. This performance achieves the highest throughput and the best energy efficiency in state-of-the-art works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"253-256"},"PeriodicalIF":2.0,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS 一个0.32 pj /b的100gb /s PAM-4 TIA在28纳米CMOS
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-29 DOI: 10.1109/LSSC.2025.3603569
Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue
{"title":"A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS","authors":"Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue","doi":"10.1109/LSSC.2025.3603569","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3603569","url":null,"abstract":"This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An inverter-based single-ended continuous-time linear equalizer (CTLE) enhanced with a Q-shaping inductor is used to further extend the BW. Moreover, a current reuse variable gain amplifier (VGA) based on a transadmittance stage (TAS)-transimpedance stage (TAS-TIS) topology is proposed to provide a dynamic range of 9 dB while maintaining the overall BW and linearity. Implemented in 28-nm CMOS, the TIA achieves a 28-GHz BW with a 65 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> dc transimpedance, while showing an input referred noise density of 16 pA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz and a total harmonic distortion (THD) < 5% up to <inline-formula> <tex-math>$640~mu $ </tex-math></inline-formula>App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"273-276"},"PeriodicalIF":2.0,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP 基于弱反转电荷供电环振荡器的LIF神经元实现201fj /SOP
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-27 DOI: 10.1109/LSSC.2025.3603335
Javier Granizo;Ruben Garvi;Ricardo Carrero;Luis Hernandez
{"title":"LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP","authors":"Javier Granizo;Ruben Garvi;Ricardo Carrero;Luis Hernandez","doi":"10.1109/LSSC.2025.3603335","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3603335","url":null,"abstract":"This letter presents the experimental results of a leaky-integrate-and-fire neuron (LIF) neuron based on time-domain analog circuitry. This kind of neuron is the core of spiking neural network (SNN) used in edge applications. Edge applications require power-efficient neuron designs whose power consumption is extremely low when idle, and low when in dynamic operation. The proposed neuron complies with the aforementioned requisites by transforming the voltage-based threshold of conventional LIF neurons into a time domain threshold on a quadrature oscillator. In conjunction with a charge-sharing integrator, the proposed neuron shows an energy efficiency of 201 fJ/SOP implemented in <inline-formula> <tex-math>$0.13mathbf {mu m}$ </tex-math></inline-formula> process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"249-252"},"PeriodicalIF":2.0,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112–170 GHz for 6G Transceivers 一种覆盖112-170 GHz的160gb /s d波段双向CMOS混频器，用于6G收发器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-11 DOI: 10.1109/LSSC.2025.3597690
Chenxin Liu;Yudai Yamazaki;Anyi Tian;Chun Wang;Hans Herdian;Abanob Shehata;Han Nie;Minzhe Tang;Hiroyuki Sakai;Kazuaki Kunihiro;Atsushi Shirane;Kenichi Okada
{"title":"A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112–170 GHz for 6G Transceivers","authors":"Chenxin Liu;Yudai Yamazaki;Anyi Tian;Chun Wang;Hans Herdian;Abanob Shehata;Han Nie;Minzhe Tang;Hiroyuki Sakai;Kazuaki Kunihiro;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2025.3597690","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3597690","url":null,"abstract":"This work presents a D-band bi-directional CMOS double-balanced mixer (DBM) supporting data rates over 160 Gb/s with a 58-GHz RF bandwidth (112–170 GHz). The mixer employs four identical NMOS passive switches (<inline-formula> <tex-math>$12~mu $ </tex-math></inline-formula>m/60 nm) in a DBM topology, providing the isolation between RF, LO, and IF ports. Both IF and RF are bi-directional, enabling up conversion and down conversion. The proposed mixer is fabricated in a 65-nm CMOS process with an integrated LO-driver amplifier. LO amplifier has a 9.5-dB simulated gain and an 8-dBm saturated output power. The total area, including RF and DC pads is 0.7749 mm2. The measurement result shows a −12.5-dB conversion gain in both directions with differential signals and a 3-dB extra loss in a single-ended configuration. <inline-formula> <tex-math>$mathrm { OP_{1dB}}$ </tex-math></inline-formula> is −13.5 dBm for up conversion and −5.5 dBm for down conversion. In modulated signal measurements, the mixer handles a 40-GHz bandwidth OFDM 16-QAM signal centered at 135 GHz, demonstrating a 160-Gb/s data rate in both up conversion and down conversion.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"241-244"},"PeriodicalIF":2.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency 一个0到- 10μF的片外输出电容可扩展升压变换器，实现96.68%的峰值效率
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-01 DOI: 10.1109/LSSC.2025.3594739
Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong
{"title":"A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency","authors":"Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3594739","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3594739","url":null,"abstract":"This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the <inline-formula> <tex-math>$C_{O}$ </tex-math></inline-formula> capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at <inline-formula> <tex-math>$V_{IN}{=}5.5$ </tex-math></inline-formula> V, <inline-formula> <tex-math>$V_{O}{=}7$ </tex-math></inline-formula> V, and I<inline-formula> <tex-math>${_{text {O}}} {=}200$ </tex-math></inline-formula> mA which has the CR of 1.27.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"233-236"},"PeriodicalIF":2.0,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization 路径激活感知监测点优化的统一预警AVFS设计
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-30 DOI: 10.1109/LSSC.2025.3593960
Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan
{"title":"A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization","authors":"Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan","doi":"10.1109/LSSC.2025.3593960","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3593960","url":null,"abstract":"This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40 nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50–100 MHz across SS/TT/FF corners.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"229-232"},"PeriodicalIF":2.0,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS 带I/Q相位校准的240ghz亚太赫兹直接转换发射机
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-24 DOI: 10.1109/LSSC.2025.3592246
Chun-Sheng Lin;Chih-Hsueh Lin;Chun-Hsing Li
{"title":"A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS","authors":"Chun-Sheng Lin;Chih-Hsueh Lin;Chun-Hsing Li","doi":"10.1109/LSSC.2025.3592246","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3592246","url":null,"abstract":"A 240-GHz direct-conversion transmitter (TX), consisting of an LO chain and fundamental I/Q mixers, is proposed for sub-THz communication applications. The LO chain integrates phase-shifter-embedded impedance matching networks (IMNs) and frequency tripler with an optimized harmonic IMN, delivering I/Q LO signals at 240 GHz with high output power, 360° phase shifting range, and I/Q phase calibration capability. The I/Q mixer incorporates two transformer baluns for I/Q signal combining and ground-shielding structures, ensuring layout symmetry and reducing coupling. This can significantly enhance the image rejection ratio (IMRR) and suppress LO feedthrough (LOFT). Fabricated in a 40-nm CMOS process, the proposed TX provides an output power of -11.7 dBm at 240 GHz with a 3-dB bandwidth (BW) from 224 to 244 GHz. It achieves LOFT suppression and IMRR better than -17.7 and -16.3 dBc, respectively, within the 3-dB BW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"225-228"},"PeriodicalIF":2.0,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS 用于BLE应用的0.7 v多类数字多尔蒂功率放大器，在22nm CMOS中具有41%的峰值DE
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-22 DOI: 10.1109/LSSC.2025.3591570
Edoardo Baiesi Fietta;David Seebacher;Davide Ponton;Andrea Bevilacqua
{"title":"A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS","authors":"Edoardo Baiesi Fietta;David Seebacher;Davide Ponton;Andrea Bevilacqua","doi":"10.1109/LSSC.2025.3591570","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3591570","url":null,"abstract":"This letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an on-chip, compact matching network. The DDPA is implemented in a 22-nm bulk CMOS technology, with the main goal of supporting BLE power classes 1.5, 2, and 3 efficiently. The proposed DDPA shows a peak drain efficiency (DE) of 41% at 10.5-dBm full-scale output power, and features an output spectrum compliant with the BLE spectrum emission mask.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"217-220"},"PeriodicalIF":2.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication MIX-ACIM：基于矢量矩阵乘法数字特征恢复的28纳米混合精度内存模拟计算
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-07-22 DOI: 10.1109/LSSC.2025.3590757
Wei-Chun Wang;Shida Zhang;Laith Shamieh;Narasimha Vasishta Kidambi;Isha Chakraborty;Saibal Mukhopadhyay
{"title":"MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication","authors":"Wei-Chun Wang;Shida Zhang;Laith Shamieh;Narasimha Vasishta Kidambi;Isha Chakraborty;Saibal Mukhopadhyay","doi":"10.1109/LSSC.2025.3590757","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3590757","url":null,"abstract":"A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 TFLOPS/mm2 for 16-bit floating-point equivalent operation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"213-216"},"PeriodicalIF":2.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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