路径激活感知监测点优化的统一预警AVFS设计

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Cai Li;Kaize Zhou;Junyi Qian;Haochang Zhi;Weiwei Shan
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引用次数: 0

摘要

这项工作提出了一个统一的预警自适应电压频率缩放(AVFS)系统,为商用物联网设备提供了一个实用的低功耗解决方案。首先,提出了一种路径激活感知的监测点优化策略,以降低非法电压标度的风险。该策略将路径激活评估与所需的定时保护带相结合,将监测成本降低了18.7%。其次,开发了延迟补偿的双阴影监视器,并与可扩展的监视窗口大小方法配对,以监视具有内存类型端点的路径的时间,克服了仅监视dff类型端点的限制。第三,提出了一种集成频率和电压缩放的统一架构,以缓解片外电压调节的问题。采用40纳米CMOS制造的Cortex M0+ CPU,在SS/TT/FF角范围内,在50-100 MHz范围内,电压降低15.4%至29.5%,功耗节省32.3%至49.3%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization
This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing guard band, reducing monitoring costs by 18.7%. Second, a delay-compensated dual-shadow monitor is developed and paired with a scalable monitoring window sizing methodology to monitor the timing of paths with memory-type endpoints, overcoming the limitation of monitoring only DFF-type endpoints. Third, a unified architecture that integrates both frequency and voltage scaling is presented to alleviate the problems of the off-chip voltage regulation. Fabricated in 40 nm CMOS, a Cortex M0+ CPU with AVFS achieves voltage reductions between 15.4% and 29.5% and power savings ranging from 32.3% to 49.3% at 50–100 MHz across SS/TT/FF corners.
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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