一个0.32 pj /b的100gb /s PAM-4 TIA在28纳米CMOS

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-08-29 DOI:10.1109/LSSC.2025.3603569

Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue

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引用次数: 0

摘要

这封信提出了一个0.32 pJ/bit 100 gb /s PAM-4 CMOS跨阻放大器（TIA）。提出了几种技术来减轻TIA设计的权衡，同时将能源效率推向极限。设计了一种多峰输入网络，以缓解输入接口和ESD二极管寄生导致的带宽下降。采用基于逆变器的单端连续时间线性均衡器（CTLE），增强了q整形电感，进一步扩展了BW。此外，提出了一种基于跨导纳级(TAS)-跨阻抗级（TAS- tis）拓扑结构的电流复用可变增益放大器（VGA），在保持整体BW和线性度的同时提供9db的动态范围。在28纳米CMOS中实现的TIA实现了28 ghz的BW，具有65 dB $\Omega $直流透阻，同时显示出16 pA/ $\surd $ Hz的输入参考噪声密度和总谐波失真(THD) < 5% up to $640~\mu $ App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.

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A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS

This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An inverter-based single-ended continuous-time linear equalizer (CTLE) enhanced with a Q-shaping inductor is used to further extend the BW. Moreover, a current reuse variable gain amplifier (VGA) based on a transadmittance stage (TAS)-transimpedance stage (TAS-TIS) topology is proposed to provide a dynamic range of 9 dB while maintaining the overall BW and linearity. Implemented in 28-nm CMOS, the TIA achieves a 28-GHz BW with a 65 dB

$\Omega $

dc transimpedance, while showing an input referred noise density of 16 pA/

$\surd $

Hz and a total harmonic distortion (THD) < 5% up to

$640~\mu $

App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.

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