IEEE Solid-State Circuits Letters最新文献_第10页

A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems 采用倍频桥接芯片的 6.4 GB/s/针 nand 闪存多芯片封装，用于可扩展性能和容量的存储系统

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-14 DOI: 10.1109/LSSC.2024.3377263

Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama

{"title":"A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems","authors":"Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama","doi":"10.1109/LSSC.2024.3377263","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3377263","url":null,"abstract":"This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple packages on each printed circuit board (PCB) channel. This NAND MCP allows to reduce the number of NAND IF channels on the PCB while retaining the total bandwidth of the SSD and increasing the capacity. The Bridge Chip employs a 2:1 frequency multiplying function to bridge the speed gap, a fast-lock phase-locked loop (PLL) with an extended pull-in range and 16-cycle lock time to enhance the IF performance with its input-jitter filtering effect, and equalizers to compensate for intersymbol interference and reflected noise in up to a 4-drop configuration. The Bridge Chip implemented in a 12-nm CMOS process is demonstrated at 6.4 Gb/s/pin with 2.85-pJ/b I/O energy efficiency in a read operation. The NAND MCP incorporating the Bridge Chip and eight 1-Tb NAND dies achieves data transmission to and from field-programmable gate array (FPGA) at twice the speed of the NAND IF in a 2-drop configuration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"115-118"},"PeriodicalIF":2.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140348399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier 带电流模式边缘合成功率放大器的多通道注入锁定 OOK 发射机

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-11 DOI: 10.1109/LSSC.2024.3375329

Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng

{"title":"A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier","authors":"Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng","doi":"10.1109/LSSC.2024.3375329","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375329","url":null,"abstract":"This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for Internet of Things (IoT) applications, the prototype incorporates a low-frequency phase-rotation-based frequency synthesizer. To mitigate the quantization noise in \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator of the synthesizer, the design combines an N-path filter and injection-locked ring oscillators to effectively filter out the shaped far-out phase noise. The prototype, fabricated in TSMC 90-nm CMOS, achieves an output power of −6.9 dBm with a power consumption of \u0000<inline-formula> <tex-math>$890~mu text{W}$ </tex-math></inline-formula>\u0000 at a 0.75-V supply voltage. It supports data rates of up to 40 Mb/s under OOK modulation, resulting in an energy efficiency of 22 pJ/bit and a global efficiency of 23%, showcasing its effectiveness in balancing performance and power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"111-114"},"PeriodicalIF":2.7,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140310160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network 针对非理想去耦网络的稳健隐含共模共振 VCO

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-10 DOI: 10.1109/LSSC.2024.3399228

Dingxin Xu;Zheng Sun;Yuang Xiong;Yuncheng Zhang;Hongye Huang;Zezheng Liu;Ashbir Aviat Fadila;Atsushi Shirane;Kenichi Okada

引用次数: 0

Bidirectional 6-Bit Active Phase Shifter in W-Band W 波段双向 6 位有源移相器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-09 DOI: 10.1109/LSSC.2024.3398779

Kateryna Smirnova;Mark van der Heijden;Domine Leenaerts;Ahmet Çağrı Ulusoy

引用次数: 0

3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design 用于实时 DVS 数据压缩的三维传感器内计算：65 纳米硬件-算法协同设计

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-08 DOI: 10.1109/LSSC.2024.3375110

Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao

{"title":"3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design","authors":"Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao","doi":"10.1109/LSSC.2024.3375110","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375110","url":null,"abstract":"Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1–10 MHz operating frequency, and\u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 compression ratio on \u0000<inline-formula> <tex-math>$256times 256$ </tex-math></inline-formula>\u0000 DVS pixels.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"119-122"},"PeriodicalIF":2.7,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140544255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems 用于自主视觉系统的级联内动态范围为 640 × 480 的堆叠式图像传感器，1 帧/秒时功耗为 90 µW，30 帧/秒时功耗为 1.33 mW，动态范围为 120 分贝

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-27 DOI: 10.1109/LSSC.2024.3370797

Pierre-François Rüedi;Riccardo Quaglia;Hans-Rudolf Graf

引用次数: 0

An Ultrasound Receiver With Bandwidth-Enhanced Current Conveyor and Element-Level Ultrasound Transmitter for Ultrasound Imaging Systems 用于超声波成像系统的带带宽增强型电流传输器和元件级超声波发射器的超声波接收器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-23 DOI: 10.1109/LSSC.2024.3369605

Gichan Yun;Kyeongwon Jeong;Haidam Choi;Seunghyun Nam;Chaerin Oh;Hyunjoo Jenny Lee;Sohmyung Ha;Minkyu Je

引用次数: 0

PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs PS-IMC：针对 DNN 的具有位并行输入和可分解权重的 2385.7-TOPS/W/b 精度可扩展内存计算宏

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-23 DOI: 10.1109/LSSC.2024.3369058

Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan

{"title":"PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs","authors":"Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan","doi":"10.1109/LSSC.2024.3369058","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3369058","url":null,"abstract":"We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the number of shift–accumulate operations, bringing down the overall adder hardware cost by \u0000<inline-formula> <tex-math>$1.57times $ </tex-math></inline-formula>\u0000 while maintaining 100% utilization for all supported precision. It also employs a carry save adder tree that saves 21% of adder hardware. The 28-nm prototype chip achieves a speed-up of \u0000<inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$10.8times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$2.42times $ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$3.22times $ </tex-math></inline-formula>\u0000 over prior SoTA in 1bW:1bI, 1bW:4bI, 4bW:4bI, and 8bW:8bI MACs, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"102-105"},"PeriodicalIF":2.7,"publicationDate":"2024-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sustainable Status Monitoring of MOSFETs in a Fully Integrated RF Amplifier by Thermal Voltage Sensing of On-Chip Thermopile 通过片上热电堆的热电压传感实现全集成射频放大器中 MOSFET 的可持续状态监控

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-22 DOI: 10.1109/LSSC.2024.3368634

Jian-Hua Li;Xiaoping Liao

{"title":"Sustainable Status Monitoring of MOSFETs in a Fully Integrated RF Amplifier by Thermal Voltage Sensing of On-Chip Thermopile","authors":"Jian-Hua Li;Xiaoping Liao","doi":"10.1109/LSSC.2024.3368634","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3368634","url":null,"abstract":"In this letter, a sustainable status monitoring of MOSFETs in a fully integrated two stage RF amplifier by thermal voltage sensing of on-chip thermopile is implemented in 0.18-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology. The designed micro-thermopile consists of many thermocouples electrically connected in series by Al and P-type polysilicon, which are carefully arranged around the metal-oxide-semiconductor field-effect transistors (MOSFETs). A noteworthy attribute of variations-aware thermopiles, which exhibits an exceptionally close physical proximity to the MOSFETs, is their nonintrusive nature, indicating that they lack electrical connectivity to transistors. During normal operation of the RF amplifier, the dynamic range of its input power spans from −20 to 0 dBm. Experimental measurements on the MOSFETs employed in the first and second power amplification stages are observed to lie within the range of 0.226 to 0.264 and 0.275 to 0.3 mV at 5.4 GHz, respectively. This result demonstrates the capability of integrated on-chip micro-thermopiles to enable continuous monitoring of the operational status of MOSFETs. In comparison to conventional status monitoring approaches, the advantage of this integrated design lies in its elimination of the requirement for supplementary sensors or devices, thereby presenting a significant economic benefit as a low-cost, sustainable monitoring solution in a fully integrated CMOS RF amplifier.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"94-97"},"PeriodicalIF":2.7,"publicationDate":"2024-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140063492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

OCCAM: An Error Oblivious CAM OCCAM：忽略错误的 CAM

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-06 DOI: 10.1109/LSSC.2024.3362891

Yuval Harary;Paz Snapir;Eyal Reshef;Esteban Garzón;Leonid Yavits

引用次数: 0