IEEE Solid-State Circuits Letters最新文献_第10页

An 11-Level Adiabatic Ultrasonic Pulser Achieving 87.2% Dynamic Power Reduction 一种11级绝热超声脉冲发生器，动态功率降低87.2%

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-10-19 DOI: 10.1109/LSSC.2023.3326087

Sandeep Reddy Kukunuru;Loai G. Salem

{"title":"An 11-Level Adiabatic Ultrasonic Pulser Achieving 87.2% Dynamic Power Reduction","authors":"Sandeep Reddy Kukunuru;Loai G. Salem","doi":"10.1109/LSSC.2023.3326087","DOIUrl":"10.1109/LSSC.2023.3326087","url":null,"abstract":"This letter introduces a pulser topology that allows switched-capacitor adiabatic drivers (SCADs) to exploit an H-bridge for doubling the output voltage swing across an ultrasonic transducer (UT) from \u0000<inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$2V_{DD}$ </tex-math></inline-formula>\u0000. The topology enables a fourfold increase in the output power of an \u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000-step SCAD while reducing the switching loss of the internal capacitance of a UT by \u0000<inline-formula> <tex-math>$sim 10times $ </tex-math></inline-formula>\u0000. A periodically switched flying ladder of capacitors is employed to balance the voltages across the \u0000<inline-formula> <tex-math>$N -1$ </tex-math></inline-formula>\u0000 charge-recycling capacitors in an \u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000-step SCAD at integer multiples of \u0000<inline-formula> <tex-math>$V_{DD}/N$ </tex-math></inline-formula>\u0000 against the imbalance produced by an H-bridge or a UT of high power factor. In this way, an H-bridge can be combined with an SCAD to flip the polarity of the voltage applied across a UT every half cycle, effectively lowering the number of required charge-recycling capacitors and intermediate switches for a given number of steps by 2. Measurements of a 0.18-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS prototype demonstrate a switching loss reduction of up to 87.2% and a peak ultrasonic driving efficiency of 92.9%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"281-284"},"PeriodicalIF":2.7,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135058583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Scheme for Low-Power, Low-Latency, and Interferer-Tolerant Wake-Up Receivers 一种低功耗、低延迟、抗干扰唤醒接收器的新方案

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-10-17 DOI: 10.1109/LSSC.2023.3325186

Hamid Jafari Sharemi;Mehrdad Sharif Bakhtiar

引用次数: 0

A 0.13-μm BiCMOS, 130-MHz Bandwidth Interface Circuit With Noise Canceling for HDD Fly-Height Resistive Sensors 用于HDD飞高电阻传感器的0.13 μm BiCMOS、130 mhz带宽消噪接口电路

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-10-13 DOI: 10.1109/LSSC.2023.3324589

M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici

{"title":"A 0.13-μm BiCMOS, 130-MHz Bandwidth Interface Circuit With Noise Canceling for HDD Fly-Height Resistive Sensors","authors":"M. M. Abdevand;D. Livornesi;A. E. Vergani;F. Piscitelli;E. Mammei;E. Bonizzoni;P. Malcovati;P. Pulici","doi":"10.1109/LSSC.2023.3324589","DOIUrl":"10.1109/LSSC.2023.3324589","url":null,"abstract":"A fully analog interface circuit based on closed-loop biasing and noise canceling techniques, fabricated in a 130-nm BiCMOS technology, is presented in this letter. The proposed interface circuit is able to precisely bias the sensor and read out the resulting signal in two frequency ranges (low-frequency (LF) range from dc to 375 kHz and high-frequency range from 1 kHz to 130 MHz). In the LF range, thanks to a dedicated noise-canceling technique, the achieved integrated input-referred noise is reduced from 7.3 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 to 2.8 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 in the 100-Hz to 1-kHz band and from 14.2 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 to 4.6 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 in the 1–100-kHz band, respectively. The fabricated chip features an active area of 1.11 mm2 and consumes 172 mW of power, including the 36 mW required to bias the sensor.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"289-292"},"PeriodicalIF":2.7,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136302120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analog Multiplexer for Performance Enhancement of Digital-to-Analog Converters and Experimental 2-to-1 Time Interleaving in 28-nm FD-SOI CMOS 28纳米FD-SOI CMOS中用于增强数模转换器性能和实验性2对1时间交错的模拟多路复用器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-10-13 DOI: 10.1109/LSSC.2023.3323857

Daniel Widmann;Tobias Tannert;Markus Grözing;Manfred Berroth

{"title":"Analog Multiplexer for Performance Enhancement of Digital-to-Analog Converters and Experimental 2-to-1 Time Interleaving in 28-nm FD-SOI CMOS","authors":"Daniel Widmann;Tobias Tannert;Markus Grözing;Manfred Berroth","doi":"10.1109/LSSC.2023.3323857","DOIUrl":"10.1109/LSSC.2023.3323857","url":null,"abstract":"To enhance the performance of digital-to-analog converters (DACs), time interleaving by an analog multiplexer (AMUX) provides a powerful concept. Next to an increased sampling rate, potential signal quality improvement as well as a sin(\u0000<inline-formula> <tex-math>${x}$ </tex-math></inline-formula>\u0000)/\u0000<inline-formula> <tex-math>${x}$ </tex-math></inline-formula>\u0000 roll-off shift due to the nonlinear switching operation enabling a true bandwidth extension can be achieved. In this letter, an integrated AMUX in a 28-nm CMOS technology is presented. The fundamental roll-off shift is deduced from a general mathematical model. In measurements, the roll-off shift as well as improvements of the edge jitter of pulse-amplitude modulated (PAM) signals due to the AMUX are demonstrated at a sampling rate of 100GS/s. Compared to single-DAC operation at 50GS/s, the total edge jitter of a PAM-2 signal can be improved from a standard deviation of about 1.27ps to about 0.56ps at 100GS/s with AMUX operation in the given system. Finally, switching operation of the AMUX at 126GS/s is shown demonstrating the potential of the concept.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"277-280"},"PeriodicalIF":2.7,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136304261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 15.5-ENOB 335 mVPP-Linear-Input-Range 4.7-GΩ-Input-Impedance CT-ΔΣM Analog Front-End With Embedded Low-Frequency Chopping 15.5-ENOB 335 mVPP线性输入范围4.7-GΩ-输入阻抗CT-Δ∑M模拟前端，带嵌入式低频斩波

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-09-25 DOI: 10.1109/LSSC.2023.3318815

Yijie Li;Weiqi Zhi;Yuying Li;Jianhong Zhou;Zhiliang Hong;Jiawei Xu

{"title":"A 15.5-ENOB 335 mVPP-Linear-Input-Range 4.7-GΩ-Input-Impedance CT-ΔΣM Analog Front-End With Embedded Low-Frequency Chopping","authors":"Yijie Li;Weiqi Zhi;Yuying Li;Jianhong Zhou;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2023.3318815","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3318815","url":null,"abstract":"This article presents a second-order continuous-time delta-sigma (CT-\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000)-based analog front-end (AFE) for biopotential sensor interfaces. High linearity is achieved by using a current balanced \u0000<inline-formula> <tex-math>$G_{m,1}$ </tex-math></inline-formula>\u0000 input stage with gain-boosting and cascode techniques. Low-frequency chopping embedded in gain-boosting OTAs breaks the limitation of chopping frequency in conventional CT-\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 ADCs and mitigates flicker noise without reducing the input impedance. In the second stage, the closed-loop \u0000<inline-formula> <tex-math>$G_{m,2}$ </tex-math></inline-formula>\u0000-OTA-C proportional integrator (PI) relaxes the linearity requirements of the OTA and eliminates the additional active adder. Fabricated in a standard 0.18-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology, this direct-digitization AFE achieves 94.9-dB peak SNDR, \u0000<inline-formula> <tex-math>$335 rm mV_{pp}$ </tex-math></inline-formula>\u0000 linear input range, and 4.7-\u0000<inline-formula> <tex-math>$text{G}Omega $ </tex-math></inline-formula>\u0000 input impedance at 50 Hz with \u0000<inline-formula> <tex-math>$64times $ </tex-math></inline-formula>\u0000 reduction in the chopping frequency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"265-268"},"PeriodicalIF":2.7,"publicationDate":"2023-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68079040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Monolithic 26 A/mm2 Continuously Scalable Conversion Ratio Switched-Capacitor Converter With Phase-Merging Turbo and Communication-Less Ganging 一种26A/mm2连续可扩展的Turbo并相无通信Ganging单片转换比开关电容变换器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-09-19 DOI: 10.1109/LSSC.2023.3306369

Nicolas Butzen;Harish Krishnamurthy;Zakir Ahmed;Sheldon Weng;Krishnan Ravichandran;Michael Zelikson;James Tschanz;Jonathan Douglas

引用次数: 0

A 4-to-42-V Input 3.3-V Output Self-Biased DC–DC Buck Converter Featuring Leakage-Emulated Bootstrap Voltage Refresher and Anti-Deadlock 一种具有泄漏模拟自举电压刷新器和防死锁功能的4至42-V输入3.3 V输出自偏压DC-DC降压转换器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-09-13 DOI: 10.1109/LSSC.2023.3314795

Heejun Lee;Hyunki Han;Hyun-Sik Kim

{"title":"A 4-to-42-V Input 3.3-V Output Self-Biased DC–DC Buck Converter Featuring Leakage-Emulated Bootstrap Voltage Refresher and Anti-Deadlock","authors":"Heejun Lee;Hyunki Han;Hyun-Sik Kim","doi":"10.1109/LSSC.2023.3314795","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3314795","url":null,"abstract":"This letter presents a 4-to-42-V input and 3.3-V output dc–dc buck converter for battery-powered automotive uses. Pulse-frequency modulation (PFM) is a common scheme employed to reduce quiescent current \u0000<inline-formula> <tex-math>$(I_{Q})$ </tex-math></inline-formula>\u0000 and mitigate battery drain. However, sustaining the bootstrap voltage \u0000<inline-formula> <tex-math>$(V_{B})$ </tex-math></inline-formula>\u0000, essential for activating power switches, becomes arduous at elevated temperatures due to significant leakage currents, particularly when the switching frequency is low in no-load scenarios. To address this issue, this letter proposes a leakage-emulating oscillator-based (LEOB) refresher that stabilizes \u0000<inline-formula> <tex-math>$V_{B}$ </tex-math></inline-formula>\u0000, even at temperatures as high as +125 °C. Additionally, an anti-deadlock self-bias supply is presented to further reduce \u0000<inline-formula> <tex-math>$I_{Q}$ </tex-math></inline-formula>\u0000 while ensuring fault tolerance. The chip, fabricated in a 180-nm BCD process, exhibits a low \u0000<inline-formula> <tex-math>$I_{Q}$ </tex-math></inline-formula>\u0000 of 3.2 \u0000<inline-formula> <tex-math>$mu text{A}$ </tex-math></inline-formula>\u0000 and a peak efficiency of 95.5% (93.3%) at \u0000<inline-formula> <tex-math>$V_{mathrm{ IN}},,=$ </tex-math></inline-formula>\u0000 24 V (42 V), with demonstrated stability of \u0000<inline-formula> <tex-math>$V_{B}$ </tex-math></inline-formula>\u0000 from −40 °C to +125 °C.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"261-264"},"PeriodicalIF":2.7,"publicationDate":"2023-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68079039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CMOS 16FF Digital Power Amplifier RF Reliability Characterization CMOS 16FF数字功率放大器射频可靠性表征

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-09-12 DOI: 10.1109/LSSC.2023.3314458

L. Zohar;I. Shternberg;B. Khamaisi;A. Nazimov;A. Ben-Bassat;O. Degani

{"title":"CMOS 16FF Digital Power Amplifier RF Reliability Characterization","authors":"L. Zohar;I. Shternberg;B. Khamaisi;A. Nazimov;A. Ben-Bassat;O. Degani","doi":"10.1109/LSSC.2023.3314458","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3314458","url":null,"abstract":"This letter describes the reliability characterization process of switched capacitor digital power amplifier (SCDPA) manufactured in CMOS acrlong 16FF technology. Power amplifiers (PAs) operate at RF frequencies (2.4 and 5–7 GHz) in which the instantaneous voltage on the transistor terminals might exceed the maximum rated voltage, Vmax allowed by the process technology. Since the available technology models for reliability degradation under RF conditions are limited, a detailed design analysis for possible failure mechanisms was done, followed by product data collection while operating in RF. In this letter, we describe this process, including SCDPA reliability risk assessment and stress experiments. We explain how in SCDPA the VDD voltage is critical for failure acceleration and not the output power (as in analog power amplifier (PA). We also show that the initial design suffered from pMOS negative bias temperature instability (NBTI) which resulted in 2nd harmonics degradation. The NBTI issue was overcome by a novel design in which the bulk voltage is dynamically changed to lower the effective source–gate voltage (Vsg) on the SCDPA pMOS transistors. To stress the SCDPA, we used a setup in which the SCDPA transmits a continuous waveform (CW) along with voltage and temperature acceleration. Finally, we show how the dynamic bulk voltage solution was successful in overcoming the NBTI degradation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"253-256"},"PeriodicalIF":2.7,"publicationDate":"2023-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68080233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Energy-Efficient Capacitive Sensor Readout Circuit With Zoomed Time-Domain Quantization 一种具有放大时域量化的高效电容式传感器读出电路

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-09-12 DOI: 10.1109/LSSC.2023.3314457

Zilong Shen;Xiyuan Tang;Zhongyi Wu;Haoyang Luo;Zongnan Wang;Xiangxing Yang;Xing Zhang;Yuan Wang

引用次数: 0

A Fetal-Movement Circuit Harvesting High-Energy Plasma During Fabrication, Concept, and Its Application to Self-Programming PUF 一种在制作过程中采集高能等离子体的胎儿运动电路，概念及其在PUF自编程中的应用

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-09-12 DOI: 10.1109/LSSC.2023.3313966

Kotaro Naruse;Takayuki Ueda;Jun Shiomi;Yoshihiro Midoh;Noriyuki Miura

引用次数: 0