IEEE Solid-State Circuits Letters最新文献_第10页

A Low-Power Highly Reconfigurable Analog FIR Filter With 11-Bit Charge-Domain DAC for Narrowband Receivers 用于窄带接收机的带 11 位电荷域 DAC 的低功耗、高可重构模拟 FIR 滤波器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-01 DOI: 10.1109/LSSC.2024.3361380

Chien-Wei Tseng;Zhen Feng;Zichen Fan;Hyochan An;Yunfan Wang;Hun-Seok Kim;David Blaauw

引用次数: 0

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array 针对非易失性铁电电容式交叉排列的动态只需电源的内存计算宏程序与两功率非线性 SAR ADC

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-02-01 DOI: 10.1109/LSSC.2024.3361011

Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo

{"title":"A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array","authors":"Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo","doi":"10.1109/LSSC.2024.3361011","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3361011","url":null,"abstract":"Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the challenges of resistive NVM CIMs. The proposed CIM macro involves encoding ternary input activations and weights into voltages, and enabling parasitic insensitive charge readout. A power-of-two nonlinear SAR ADC is introduced, designed for energy-efficiency and hardware-friendliness. This ADC employs adaptive conversion skipping based on input voltage, resulting in fine precision for concentrated input levels and coarse conversion for sparse input levels. The proposed FCA-based CIM macro in 180-nm CMOS demonstrates \u0000<inline-formula> <tex-math>$16times 8$ </tex-math></inline-formula>\u0000 analog MAC operation with an energy efficiency of 1.75 TOPS/W and classification accuracy of 90.2% is obtained for the CIFAR-10 dataset.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"70-73"},"PeriodicalIF":2.7,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139916647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Depth-Noise Indirect Time-of-Flight CMOS Image Sensor With Tap-Rotating Technique for Extended Range and Enhanced Imaging Quality 采用分接旋转技术的低深度噪声间接飞行时间 CMOS 图像传感器，可扩展成像范围并提高成像质量

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-30 DOI: 10.1109/LSSC.2024.3360243

Fei Wang;Siyu Huang;Zhigang Wu;Cheng Ma;Xinyang Wang;Zeyu Cai

引用次数: 0

Miniaturized Stepped Impedance Transmission Lines for D-Band Wideband Power Divider With Isolation Capacitor 用于带隔离电容器 D 波段宽带功率分配器的小型化阶跃阻抗传输线

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-29 DOI: 10.1109/LSSC.2024.3359315

Seonjeong Park;Songcheol Hong

引用次数: 0

A Bootstrapped 250-nm GaN MMIC N-Path Filter With a 31 dBm In-Band P1dB 带内 P1dB 为 31 dBm 的自举式 250-nm GaN MMIC N-Path 滤波器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-24 DOI: 10.1109/LSSC.2024.3358083

Netanel Desta;Emanuel Cohen

引用次数: 0

Compact Multifunctional 180° Hybrid-Based 300-GHz Subharmonic I/Q Downconversion Resistive Mixers in 130-nm SiGe Process 基于 180° 混合技术的紧凑型多功能 300-GHz 次谐波 I/Q 下变频电阻混频器，采用 130 纳米硅锗工艺制造

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-24 DOI: 10.1109/LSSC.2024.3357810

Liang Zhang;Fengjun Chen;Xu Cheng;Jiang-An Han;Xianhu Luo;Changxing Lin;Wei Su

{"title":"Compact Multifunctional 180° Hybrid-Based 300-GHz Subharmonic I/Q Downconversion Resistive Mixers in 130-nm SiGe Process","authors":"Liang Zhang;Fengjun Chen;Xu Cheng;Jiang-An Han;Xianhu Luo;Changxing Lin;Wei Su","doi":"10.1109/LSSC.2024.3357810","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3357810","url":null,"abstract":"In this letter, a compact multifunctional 180° hybrid suitable for subharmonic in-phase/quadrature (I/Q) mixers is proposed. To feed LO and RF signals at different frequencies and distribute dc supply, the hybrid combines an out-of-phase dual balun, two in-phase power dividers based on T-junction and coupled lines, and four zero-ohm transmission lines (ZTLs) into a single passive component. Chip size, insertion loss, and bandwidth can all be improved by reducing the number of passive components cascaded in the circuit. The proposed hybrid’s footprint is further minimized by employing redundant line and compensation capacitor techniques. In a 130-nm SiGe BiCMOS technology, two proof-of-concept subharmonic I/Q downconversion resistive mixers with/without an on-chip LO quadrupler are implemented. Both mixers feature wideband HBT-based IF amplifiers and emitter followers, which eliminate the need for dc-blocking capacitors that constrict the IF bandwidth. The mixer, without an integrated LO multiplier, occupies an area of \u0000<inline-formula> <tex-math>$0.685times 0.692,,{mathrm{ mm}}^{2}$ </tex-math></inline-formula>\u0000 and achieves a measured conversion gain of approximately 0 dB from 255 to 310 GHz. The mixer with an on-chip LO quadrupler exhibits a conversion gain of approximately −1 dB from 270 to 300 GHz and a 3-dB IF bandwidth from 0.01 to 7 GHz. Additionally, the measured image rejection ratio (IRR) is greater than 20 dB within the operating frequencies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"86-89"},"PeriodicalIF":2.7,"publicationDate":"2024-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139942713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 28-GHz Low-Power Variable-Gain Low-Noise Amplifier Using Twice Current Reuse Technique 使用两倍电流重复使用技术的 28 千兆赫低功耗可变增益低噪声放大器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-15 DOI: 10.1109/LSSC.2024.3354037

Yu-Teng Chang;Wen-Jie Lin

{"title":"A 28-GHz Low-Power Variable-Gain Low-Noise Amplifier Using Twice Current Reuse Technique","authors":"Yu-Teng Chang;Wen-Jie Lin","doi":"10.1109/LSSC.2024.3354037","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3354037","url":null,"abstract":"In this letter, a 28-GHz low-power variable-gain low-noise amplifier (VGLNA) is designed for fifth-generation millimeter-wave applications and implemented using the twice current reuse (CR) technique and a tunable load. This amplifier employing the twice CR technique exhibits low dc power while delivering enhanced gain. The gain control (GC) range of the amplifier is extended using a tunable load, which is composed of a pMOS device and an inductance, and the phase variation is improved by resonating the inductance with the parasitic capacitance of the intrastage CR amplifier. Because the tunable load selectively attenuates only ac signals, \u0000<inline-formula> <tex-math>${mathrm{ IP}}_{1 rm dB}$ </tex-math></inline-formula>\u0000 can be proportionally increased by reducing the gain. At 28 GHz, the measured gain and GC range are 21.2 and 13.8 dB, respectively. In the entire GC range, the measured \u0000<inline-formula> <tex-math>${mathrm{ IP}}_{1 rm dB}$ </tex-math></inline-formula>\u0000 ranges from −20 to −7 dBm, the noise figure (NF) ranges from 3.7 to 6.8 dB, and the RMS phase error is 1.05° at 28 GHz. At a supply voltage of 1.2 V, the dc power of the proposed VGLNA is only 5.0 mW. These results highlight that the proposed VGLNA has the lowest dc power, higher gain, and better figure of merit compared to other works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"58-61"},"PeriodicalIF":2.7,"publicationDate":"2024-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Photovoltaic Energy Harvester/Image Sensor Platform With Event Detection Capability in 180 nm 具有事件检测能力的 180 纳米光伏能量收集器/图像传感器平台

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-12 DOI: 10.1109/LSSC.2024.3353381

D. Zagouri;A. Rimer;E. Emanovic;Y. Ninio;Y. Slezak;D. Jurisic;A. Fish;J. Shor

引用次数: 0

A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range 基于高能效环形振荡器的大调谐范围 DTC 的完全可合成分数 N MDLL

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-11 DOI: 10.1109/LSSC.2024.3352736

Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada

{"title":"A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range","authors":"Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3352736","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3352736","url":null,"abstract":"This letter describes a fully synthesizable fractional-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 and fractional-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"54-57"},"PeriodicalIF":2.7,"publicationDate":"2024-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10391060","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Mixer-First Receiver With On-Demand Passive Harmonic Rejection 具有按需无源谐波抑制功能的混频器优先接收器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-09 DOI: 10.1109/LSSC.2024.3351671

Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier

引用次数: 0