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IEEE Solid-State Circuits Letters最新文献

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A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter 一种采用16nm FinFET的四核VCO的19.5 ghz抗辐射次采样锁相环，实现了低于50秒的抖动
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-17 DOI: 10.1109/LSSC.2025.3610901
David Dolt;Samuel Palermo
{"title":"A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter","authors":"David Dolt;Samuel Palermo","doi":"10.1109/LSSC.2025.3610901","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3610901","url":null,"abstract":"This letter presents a radiation-hardened (rad-hard) subsampled phase-locked loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techniques to mitigate single-event-upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL subblock which include a rad-hard charge-pump Gm cell, a pulser circuit with triple modular redundancy (TMR), and a quad-core voltage-controlled oscillator (VCO) with varactor hardening and LC tail filters. Implemented in a 16-nm FinFET process, the PLL consumes 36.5 mW of power and achieves a jitter of 45.82 fs at 19.5 GHz. Testing at a cyclotron facility verifies robust SEU performance up to an LET of 55 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"285-288"},"PeriodicalIF":2.0,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation 一种用于植入式神经刺激的线性动态电压缩放技术及自适应最小电压净空跟踪
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608096
Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma
{"title":"A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation","authors":"Kai Cui;Honglei Xu;Yingduo Duan;Yan Lu;Xiaoya Fan;Yanzhao Ma","doi":"10.1109/LSSC.2025.3608096","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608096","url":null,"abstract":"This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the linear region under different stimulus currents. Furthermore, a simple mode-switched control is introduced to improve the loop response of charge-pump. The design has been fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m BCD process. The DVS technique increases the measured stimulus efficiency up to 52.8% higher than a fixed supply voltage with a peak efficiency of 89.6% in the range of the stimulus current from 0.5 mA to 0.9 mA.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"261-264"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm 一款800GbE PAM-4 PHY收发器，适用于42 dB铜和7 nm直接驱动光学应用
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608134
Chang Liu;Burak Catli;Yong Liu;Anand Vasani;Guansheng Li;Kun Chuai;Lakshmi Rao;Yang Liu;Xin Meng;Jiawen Zhang;Tim He;Batu Dayanik;Vadim Milirud;Meisam Honarvar Nazari;Hyo Gyuem Rhew;Derui Kong;Arvindh Iyer;Nan Wang;Alireza Nilchi;Aminghasem Safarian;Ray Wang;Hyung-Joon Jeon;Xiaochen Yang;Boyu Hu;Jerry Han;Adesh Garg;Kumar Thasari;Heng Zhang;Namik Kocaman;Ali Nazemi;Delong Cui;Afshin Momtaz;Jun Cao
{"title":"An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm","authors":"Chang Liu;Burak Catli;Yong Liu;Anand Vasani;Guansheng Li;Kun Chuai;Lakshmi Rao;Yang Liu;Xin Meng;Jiawen Zhang;Tim He;Batu Dayanik;Vadim Milirud;Meisam Honarvar Nazari;Hyo Gyuem Rhew;Derui Kong;Arvindh Iyer;Nan Wang;Alireza Nilchi;Aminghasem Safarian;Ray Wang;Hyung-Joon Jeon;Xiaochen Yang;Boyu Hu;Jerry Han;Adesh Garg;Kumar Thasari;Heng Zhang;Namik Kocaman;Ali Nazemi;Delong Cui;Afshin Momtaz;Jun Cao","doi":"10.1109/LSSC.2025.3608134","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608134","url":null,"abstract":"This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"281-284"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation 一种38.1 fJ/Bit电容锁存真随机数发生器，具有逆变器自动归零失配和加速评估功能
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608187
Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim
{"title":"A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation","authors":"Woojin Lee;Changmin Sim;Changjoo Kim;Jinwoo Jeon;Hyundo Jung;Taihyun Kim;Chulwoo Kim","doi":"10.1109/LSSC.2025.3608187","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608187","url":null,"abstract":"This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4-V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"265-268"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions 串联三阱型低寄生MOS电容器的设计与验证
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-10 DOI: 10.1109/LSSC.2025.3608282
Zhendong Li;Yongjuan Shi;Yifan Jiang;Chen Hu;Junting Chen;Mengyuan Hua;Xun Liu;Junmin Jiang
{"title":"Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions","authors":"Zhendong Li;Yongjuan Shi;Yifan Jiang;Chen Hu;Junting Chen;Mengyuan Hua;Xun Liu;Junmin Jiang","doi":"10.1109/LSSC.2025.3608282","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3608282","url":null,"abstract":"This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias voltage is applied using a sufficiently large resistor to further reduce parasitic capacitance. Furthermore, we also present a simple and effective method for testing very small parasitic capacitance using off-chip inverters. The test chip was fabricated using the 180-nm BCD process. The measurement results indicate that the ratio of parasitic to flying capacitance can be reduced to as low as 0.67% for 1.8-V MOS capacitors through series-connected tri-well junctions with effective biasing while only increasing a 7.7% the chip area overhead compared to the dual-well junctions.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"277-280"},"PeriodicalIF":2.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS 1.53 GSamples/s 40nm CMOS噪声发生器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-09-02 DOI: 10.1109/LSSC.2025.3605369
Cheng-Bin Chen;Tsung Chen;Yuan-Hao Huang
{"title":"24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS","authors":"Cheng-Bin Chen;Tsung Chen;Yuan-Hao Huang","doi":"10.1109/LSSC.2025.3605369","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3605369","url":null,"abstract":"This letter presents a fully digital true random number generator (TRNG) and noise generator (NG) based on a chaos system. We design the chaos random number generator (CRNG) using the proposed Euler-based modified Lorenz system with periodic perturbation and modified modulo unit. The chaos NG (CNG) processor integrates the CRNG with Box-Muller modules to produce Gaussian noise signals. This letter also analyzes the impact of step size on the infinite divergence phenomenon and performs the NIST test to ensure CRNG’s mathematical stability and reliability. The chip was designed and fabricated using TSMC 40 nm CMOS technology. The proposed CRNG chip achieves a throughput of 24.86 Gb/s at a maximum clock frequency of 259 MHz, with a core power consumption of 17.82 mW and an energy efficiency of 0.717 pJ/bit. This performance achieves the highest throughput among state-of-the-art ASIC-based true RNGs (TRNGs). Additionally, the proposed processor achieves a throughput of 1.53 Gsamples/s with a clock frequency of 255 MHz, a core power consumption of 62.73 mW, and an energy efficiency of 41 pJ/sample. This performance achieves the highest throughput and the best energy efficiency in state-of-the-art works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"253-256"},"PeriodicalIF":2.0,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS 一个0.32 pj /b的100gb /s PAM-4 TIA在28纳米CMOS
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-29 DOI: 10.1109/LSSC.2025.3603569
Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue
{"title":"A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS","authors":"Chongyun Zhang;Li Wang;Fuzhan Chen;C. Patrick Yue","doi":"10.1109/LSSC.2025.3603569","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3603569","url":null,"abstract":"This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An inverter-based single-ended continuous-time linear equalizer (CTLE) enhanced with a Q-shaping inductor is used to further extend the BW. Moreover, a current reuse variable gain amplifier (VGA) based on a transadmittance stage (TAS)-transimpedance stage (TAS-TIS) topology is proposed to provide a dynamic range of 9 dB while maintaining the overall BW and linearity. Implemented in 28-nm CMOS, the TIA achieves a 28-GHz BW with a 65 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> dc transimpedance, while showing an input referred noise density of 16 pA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz and a total harmonic distortion (THD) < 5% up to <inline-formula> <tex-math>$640~mu $ </tex-math></inline-formula>App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"273-276"},"PeriodicalIF":2.0,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP 基于弱反转电荷供电环振荡器的LIF神经元实现201fj /SOP
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-27 DOI: 10.1109/LSSC.2025.3603335
Javier Granizo;Ruben Garvi;Ricardo Carrero;Luis Hernandez
{"title":"LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP","authors":"Javier Granizo;Ruben Garvi;Ricardo Carrero;Luis Hernandez","doi":"10.1109/LSSC.2025.3603335","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3603335","url":null,"abstract":"This letter presents the experimental results of a leaky-integrate-and-fire neuron (LIF) neuron based on time-domain analog circuitry. This kind of neuron is the core of spiking neural network (SNN) used in edge applications. Edge applications require power-efficient neuron designs whose power consumption is extremely low when idle, and low when in dynamic operation. The proposed neuron complies with the aforementioned requisites by transforming the voltage-based threshold of conventional LIF neurons into a time domain threshold on a quadrature oscillator. In conjunction with a charge-sharing integrator, the proposed neuron shows an energy efficiency of 201 fJ/SOP implemented in <inline-formula> <tex-math>$0.13mathbf {mu m}$ </tex-math></inline-formula> process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"249-252"},"PeriodicalIF":2.0,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112–170 GHz for 6G Transceivers 一种覆盖112-170 GHz的160gb /s d波段双向CMOS混频器，用于6G收发器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-11 DOI: 10.1109/LSSC.2025.3597690
Chenxin Liu;Yudai Yamazaki;Anyi Tian;Chun Wang;Hans Herdian;Abanob Shehata;Han Nie;Minzhe Tang;Hiroyuki Sakai;Kazuaki Kunihiro;Atsushi Shirane;Kenichi Okada
{"title":"A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112–170 GHz for 6G Transceivers","authors":"Chenxin Liu;Yudai Yamazaki;Anyi Tian;Chun Wang;Hans Herdian;Abanob Shehata;Han Nie;Minzhe Tang;Hiroyuki Sakai;Kazuaki Kunihiro;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2025.3597690","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3597690","url":null,"abstract":"This work presents a D-band bi-directional CMOS double-balanced mixer (DBM) supporting data rates over 160 Gb/s with a 58-GHz RF bandwidth (112–170 GHz). The mixer employs four identical NMOS passive switches (<inline-formula> <tex-math>$12~mu $ </tex-math></inline-formula>m/60 nm) in a DBM topology, providing the isolation between RF, LO, and IF ports. Both IF and RF are bi-directional, enabling up conversion and down conversion. The proposed mixer is fabricated in a 65-nm CMOS process with an integrated LO-driver amplifier. LO amplifier has a 9.5-dB simulated gain and an 8-dBm saturated output power. The total area, including RF and DC pads is 0.7749 mm2. The measurement result shows a −12.5-dB conversion gain in both directions with differential signals and a 3-dB extra loss in a single-ended configuration. <inline-formula> <tex-math>$mathrm { OP_{1dB}}$ </tex-math></inline-formula> is −13.5 dBm for up conversion and −5.5 dBm for down conversion. In modulated signal measurements, the mixer handles a 40-GHz bandwidth OFDM 16-QAM signal centered at 135 GHz, demonstrating a 160-Gb/s data rate in both up conversion and down conversion.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"241-244"},"PeriodicalIF":2.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency 一个0到- 10μF的片外输出电容可扩展升压变换器，实现96.68%的峰值效率
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-08-01 DOI: 10.1109/LSSC.2025.3594739
Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong
{"title":"A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency","authors":"Hyeon-Ji Choi;Joo-Mi Cho;Hyo-Jin Park;Seok-Jun Lee;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3594739","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3594739","url":null,"abstract":"This letter presents an off-chip output capacitor (CO)-scalable (OCS) boost converter. The proposed OCS boost converter is possible to operate both with and without the off-chip CO. In addition, it operates in a whole conversion ratio (CR) range over 1 while maintaining a small current ripple of an inductor, resulting in a high efficiency with an inductor of which inductance is small, irrespective of the <inline-formula> <tex-math>$C_{O}$ </tex-math></inline-formula> capacitance. The converter was fabricated in 130-nm BCD process and shows a peak efficiency of 96.68% at <inline-formula> <tex-math>$V_{IN}{=}5.5$ </tex-math></inline-formula> V, <inline-formula> <tex-math>$V_{O}{=}7$ </tex-math></inline-formula> V, and I<inline-formula> <tex-math>${_{text {O}}} {=}200$ </tex-math></inline-formula> mA which has the CR of 1.27.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"233-236"},"PeriodicalIF":2.0,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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