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A 4-Element Ka-Band Phased-Array Receiver With Code-Domain Hybrid Beamforming 具有码域混合波束成形功能的 4 元 Ka 波段相控阵接收器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-20 DOI: 10.1109/LSSC.2024.3379562
Ziyi Lin;Haikun Jia;Chuanming Zhu;Wei Deng;Huabing Liao;Bao Shi;Lujie Hao;Xiangrong Huang;Baoyong Chi
{"title":"A 4-Element Ka-Band Phased-Array Receiver With Code-Domain Hybrid Beamforming","authors":"Ziyi Lin;Haikun Jia;Chuanming Zhu;Wei Deng;Huabing Liao;Bao Shi;Lujie Hao;Xiangrong Huang;Baoyong Chi","doi":"10.1109/LSSC.2024.3379562","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3379562","url":null,"abstract":"This letter presents a 4-element phased-array receiver with code-domain hybrid beamforming (CDHBF) in 65-nm CMOS technology. Code-division multiplexing is used to fully preserve the flexibility in the digital domain while using a single RF interface, which reduces the RF chain complexity, reduces the chip area, and improves power efficiency. Phase and amplitude control circuits are also integrated into each path to keep the flexibility to use the receiver as a traditional 4-element phased-array. The phased-array and code modulator can be turned on or off to reconfigure this structure into an analog beamformer, hybrid beamformer, and digital beamformer according to applications. An over-the-air wireless measurement is set up and two streams from different directions are simultaneously received and processed by the proposed receiver. The measured EVMs in CDHBF mode are -22.7 and -20.5 dB for 100 and 200-Ms/s data streams, respectively, without any digital domain equalization.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"123-126"},"PeriodicalIF":2.7,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gain 宽带低噪声线性激光雷达模拟前端，实现 1.6 GHz 带宽、2.7-pA/Hz0.5 输入参考噪声和 103-dBΩ 跨阻增益
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-19 DOI: 10.1109/LSSC.2024.3378093
Zhao Zhang;Yidan Zhang;Yiqing Xu;Xinyu Shen;Guike Li;Nan Qi;Jian Liu;Nanjian Wu;Liyuan Liu
{"title":"A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gain","authors":"Zhao Zhang;Yidan Zhang;Yiqing Xu;Xinyu Shen;Guike Li;Nan Qi;Jian Liu;Nanjian Wu;Liyuan Liu","doi":"10.1109/LSSC.2024.3378093","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3378093","url":null,"abstract":"This letter presents a low-noise wideband analog front-end (AFE) circuit for long-range linear LiDAR. The nMOS feedforward transimpedance amplifier with inner feedback resistor (NFFR-TIA) is proposed to extend the bandwidth to around 400 MHz and reduce the input referred noise (IRN) concurrently with high-transimpedance gain and improved stability. Two stage continuous-time linear feedback circuits are introduced to further boost the bandwidth to over-1 GHz with flatten in-band AC response and negligible extra noise. Fabricated in a 40-nm CMOS process, our AFE achieves an average IRN of 2.7 pA/Hz \u0000<inline-formula> <tex-math>$^{mathrm{ 0.5}}$ </tex-math></inline-formula>\u0000, 1.6-GHz bandwidth, 103-dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 transimpedance gain, and 10-mW power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"131-134"},"PeriodicalIF":2.7,"publicationDate":"2024-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems 采用倍频桥接芯片的 6.4 GB/s/针 nand 闪存多芯片封装，用于可扩展性能和容量的存储系统
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-14 DOI: 10.1109/LSSC.2024.3377263
Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama
{"title":"A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems","authors":"Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama","doi":"10.1109/LSSC.2024.3377263","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3377263","url":null,"abstract":"This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple packages on each printed circuit board (PCB) channel. This NAND MCP allows to reduce the number of NAND IF channels on the PCB while retaining the total bandwidth of the SSD and increasing the capacity. The Bridge Chip employs a 2:1 frequency multiplying function to bridge the speed gap, a fast-lock phase-locked loop (PLL) with an extended pull-in range and 16-cycle lock time to enhance the IF performance with its input-jitter filtering effect, and equalizers to compensate for intersymbol interference and reflected noise in up to a 4-drop configuration. The Bridge Chip implemented in a 12-nm CMOS process is demonstrated at 6.4 Gb/s/pin with 2.85-pJ/b I/O energy efficiency in a read operation. The NAND MCP incorporating the Bridge Chip and eight 1-Tb NAND dies achieves data transmission to and from field-programmable gate array (FPGA) at twice the speed of the NAND IF in a 2-drop configuration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"115-118"},"PeriodicalIF":2.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140348399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier 带电流模式边缘合成功率放大器的多通道注入锁定 OOK 发射机
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-11 DOI: 10.1109/LSSC.2024.3375329
Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng
{"title":"A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier","authors":"Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng","doi":"10.1109/LSSC.2024.3375329","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375329","url":null,"abstract":"This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for Internet of Things (IoT) applications, the prototype incorporates a low-frequency phase-rotation-based frequency synthesizer. To mitigate the quantization noise in \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator of the synthesizer, the design combines an N-path filter and injection-locked ring oscillators to effectively filter out the shaped far-out phase noise. The prototype, fabricated in TSMC 90-nm CMOS, achieves an output power of −6.9 dBm with a power consumption of \u0000<inline-formula> <tex-math>$890~mu text{W}$ </tex-math></inline-formula>\u0000 at a 0.75-V supply voltage. It supports data rates of up to 40 Mb/s under OOK modulation, resulting in an energy efficiency of 22 pJ/bit and a global efficiency of 23%, showcasing its effectiveness in balancing performance and power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"111-114"},"PeriodicalIF":2.7,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140310160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network 针对非理想去耦网络的稳健隐含共模共振 VCO
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-10 DOI: 10.1109/LSSC.2024.3399228
Dingxin Xu;Zheng Sun;Yuang Xiong;Yuncheng Zhang;Hongye Huang;Zezheng Liu;Ashbir Aviat Fadila;Atsushi Shirane;Kenichi Okada
{"title":"A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network","authors":"Dingxin Xu;Zheng Sun;Yuang Xiong;Yuncheng Zhang;Hongye Huang;Zezheng Liu;Ashbir Aviat Fadila;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3399228","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3399228","url":null,"abstract":"This letter describes a voltage-controlled oscillator (VCO) that can achieve robust flicker noise suppression when the decoupling network is not ideal. Utilizing a multitap transformer, the implicit common-mode (CM) impedance quality factor (Q factor) degradation from the parasitic resistance of the decoupling network can be avoided. Fabricated in 65-nm CMOS, the proposed VCO realizes a flicker corner (1/f3 corner) from 70 to 230 kHz across the tuning range from 4.24 to 4.80 GHz. The proposed VCO achieves a phase noise (PN) of -127.4 dBc/Hz at 1 MHz offset frequency fofst and a Figure of Merit (FoM) of 193.1 dB. The core area of the VCO is 0.29 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"171-174"},"PeriodicalIF":2.7,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141181903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bidirectional 6-Bit Active Phase Shifter in W-Band W 波段双向 6 位有源移相器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-09 DOI: 10.1109/LSSC.2024.3398779
Kateryna Smirnova;Mark van der Heijden;Domine Leenaerts;Ahmet Çağrı Ulusoy
{"title":"Bidirectional 6-Bit Active Phase Shifter in W-Band","authors":"Kateryna Smirnova;Mark van der Heijden;Domine Leenaerts;Ahmet Çağrı Ulusoy","doi":"10.1109/LSSC.2024.3398779","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3398779","url":null,"abstract":"In this letter, a novel W-band switchless bidirectional active phase shifter with 6-bit resolution is proposed. The circuit is implemented in the SiGe:C BiCMOS technology using a Gilbert-cell core configured in a way to combine the reciprocity of passive phase shifters with the compactness of active topologies. The circuit exhibits a maximum average gain of –7.4 and –8.2 dB in two directions while maintaining the RMS amplitude and phase error lower than 0.84 dB and 3.4° within 85– 100 GHz, respectively. The phase shifter uses 0.04 mm2 of the IC area and the DC power of 38 mW in each direction from a 2.4-V supply voltage, excluding the phase control circuitry.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"175-178"},"PeriodicalIF":2.7,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141187374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design 用于实时 DVS 数据压缩的三维传感器内计算：65 纳米硬件-算法协同设计
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-08 DOI: 10.1109/LSSC.2024.3375110
Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao
{"title":"3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design","authors":"Gopikrishnan R. Nair;Pragnya S. Nalla;Gokul Krishnan;Anupreetham;Jonghyun Oh;Ahmed Hassan;Injune Yeo;Kishore Kasichainula;Mingoo Seok;Jae-Sun Seo;Yu Cao","doi":"10.1109/LSSC.2024.3375110","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375110","url":null,"abstract":"Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this design, we adopt a 4-bit autoencoder algorithm and implement it on an AI computing layer with in-memory computing (IMC) to enable real-time compression of DVS data. To support 3-D integration, this architecture is optimized to handle the unique constraints, including footprint to match the size of the sensor array, low latency to manage the continuous data stream, and low-power consumption to avoid thermal issues. Our prototype chip in 65-nm CMOS demonstrates the new concept of 3-D in-sensor computing, achieving < 6 mW power consumption at 1–10 MHz operating frequency, and\u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 compression ratio on \u0000<inline-formula> <tex-math>$256times 256$ </tex-math></inline-formula>\u0000 DVS pixels.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"119-122"},"PeriodicalIF":2.7,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140544255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems 用于自主视觉系统的级联内动态范围为 640 × 480 的堆叠式图像传感器，1 帧/秒时功耗为 90 µW，30 帧/秒时功耗为 1.33 mW，动态范围为 120 分贝
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-02-27 DOI: 10.1109/LSSC.2024.3370797
Pierre-François Rüedi;Riccardo Quaglia;Hans-Rudolf Graf
{"title":"A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems","authors":"Pierre-François Rüedi;Riccardo Quaglia;Hans-Rudolf Graf","doi":"10.1109/LSSC.2024.3370797","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3370797","url":null,"abstract":"We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc current consumption. The 120-dB intrascene DR of the sensor, encoded on 10 bits, makes use of a logarithmic data representation. Thanks to the high intrascene DR, no adaptation to the local illumination is necessary. The sensor has a sensitivity of 6.4 V/lux/s, an FPN of 0.6%, and a temporal noise of 11 e−, with a pixel pitch of \u0000<inline-formula> <tex-math>$6.3 , mu text{m}$ </tex-math></inline-formula>\u0000 and a fill factor of 86%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"106-109"},"PeriodicalIF":2.7,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140161094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultrasound Receiver With Bandwidth-Enhanced Current Conveyor and Element-Level Ultrasound Transmitter for Ultrasound Imaging Systems 用于超声波成像系统的带带宽增强型电流传输器和元件级超声波发射器的超声波接收器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-02-23 DOI: 10.1109/LSSC.2024.3369605
Gichan Yun;Kyeongwon Jeong;Haidam Choi;Seunghyun Nam;Chaerin Oh;Hyunjoo Jenny Lee;Sohmyung Ha;Minkyu Je
{"title":"An Ultrasound Receiver With Bandwidth-Enhanced Current Conveyor and Element-Level Ultrasound Transmitter for Ultrasound Imaging Systems","authors":"Gichan Yun;Kyeongwon Jeong;Haidam Choi;Seunghyun Nam;Chaerin Oh;Hyunjoo Jenny Lee;Sohmyung Ha;Minkyu Je","doi":"10.1109/LSSC.2024.3369605","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3369605","url":null,"abstract":"In this letter, we present an ultrasound (US) imaging system with a low-noise US receiver (RX) and an element-level US transmitter (TX) for a capacitive micromachined ultrasonic transducer (CMUT). The proposed US RX isolates the input parasitic capacitance \u0000<inline-formula> <tex-math>$(C_{P})$ </tex-math></inline-formula>\u0000 from the front-end transimpedance stage by using a bandwidth-enhanced current conveyor. By reducing the effects of the \u0000<inline-formula> <tex-math>$C_{P}$ </tex-math></inline-formula>\u0000, the noise and power efficiency are improved compared to the conventional current readout circuits. Also, a US TX having a class-D output stage is implemented to excite the CMUT with 30-V unipolar pulses. Fabricated in a 180-nm BCD process, the proposed US RX achieves input-referred noise of 2.0 pA/\u0000<inline-formula> <tex-math>$sqrt {textit {Hz}}$ </tex-math></inline-formula>\u0000 at 7.5 MHz and a bandwidth of 18 MHz with 25-pF CMUT capacitance while consuming 3.62 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"98-101"},"PeriodicalIF":2.7,"publicationDate":"2024-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140104292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs PS-IMC：针对 DNN 的具有位并行输入和可分解权重的 2385.7-TOPS/W/b 精度可扩展内存计算宏
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-02-23 DOI: 10.1109/LSSC.2024.3369058
Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan
{"title":"PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs","authors":"Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan","doi":"10.1109/LSSC.2024.3369058","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3369058","url":null,"abstract":"We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the number of shift–accumulate operations, bringing down the overall adder hardware cost by \u0000<inline-formula> <tex-math>$1.57times $ </tex-math></inline-formula>\u0000 while maintaining 100% utilization for all supported precision. It also employs a carry save adder tree that saves 21% of adder hardware. The 28-nm prototype chip achieves a speed-up of \u0000<inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$10.8times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$2.42times $ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$3.22times $ </tex-math></inline-formula>\u0000 over prior SoTA in 1bW:1bI, 1bW:4bI, 4bW:4bI, and 8bW:8bI MACs, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"102-105"},"PeriodicalIF":2.7,"publicationDate":"2024-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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