IEEE Solid-State Circuits Letters最新文献_第9页

A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology Cryo-CMOS动态比较器在40纳米体CMOS技术中的基准测试

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IEEE Solid-State Circuits Letters Pub Date : 2025-10-06 DOI: 10.1109/LSSC.2025.3618161

Bram Veraverbeke;Filip Tavernier

{"title":"A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology","authors":"Bram Veraverbeke;Filip Tavernier","doi":"10.1109/LSSC.2025.3618161","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3618161","url":null,"abstract":"All cryo-CMOS quantum-classical control interfaces require an analog-to-digital converter (ADC) bridging the analog qubits and the digital control logic. Dynamic comparators play a crucial role in the precision, speed, and power consumption of these ADCs. Yet, their performance is severely impacted by the cryogenic environment. Therefore, this letter benchmarks, for the first time in the literature, four comparator topologies at room temperature (RT) and 6K. Their noise, delay, and energy consumption are characterized, allowing the identification of the best topology for a given application. This analysis shows that the strongARM (SA) comparator is the most energy efficient, closely followed by the double tail comparator. However, the reduced voltage headroom at 6K almost doubles the SA’s delay compared to RT and leaves it susceptible to common-mode and supply voltage variations. In contrast, the recently proposed triple tail comparator with capacitive over-neutralization limits the delay increase to only 13ps by separating the preamplifier and the latch. Furthermore, its boosted preamplification gain makes it notably more resilient to voltage variations, ensuring a highly robust cryogenic operation favorable for scaled technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"317-320"},"PeriodicalIF":2.0,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit 基于高熵类比的强物理不可克隆函数，面积熵比为166f2 /bit

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-30 DOI: 10.1109/LSSC.2025.3616263

Alessandro Catania;Sebastiano Strangio;Maksym Paliy;Christian Sbrana;Michele Bertozzi;Giuseppe Iannaccone

引用次数: 0

Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI 采用两级18ghz 18pa /√Hz TIA的22nm FDSOI双结单片集成监测光电二极管

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-29 DOI: 10.1109/LSSC.2025.3615656

Jelle H. T. Bakker;Nimit Jain;Paul Klatser;Mark S. Oude Alink;Bram Nauta

引用次数: 0

An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation 8.5 MHz 42 ppm/°C弛豫振荡器与电荷泵延迟抵消和数字斩波解调

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-29 DOI: 10.1109/LSSC.2025.3615833

Yongjia Li;Jianlin Xia;Feng Cheng;Yifan Cao;Jin Wu;Encheng Zhu;Xiaofeng Sun;Dejin Wang;Long Zhang;Zhongyuan Fang;Weifeng Sun

{"title":"An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation","authors":"Yongjia Li;Jianlin Xia;Feng Cheng;Yifan Cao;Jin Wu;Encheng Zhu;Xiaofeng Sun;Dejin Wang;Long Zhang;Zhongyuan Fang;Weifeng Sun","doi":"10.1109/LSSC.2025.3615833","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3615833","url":null,"abstract":"This letter presents an RC oscillator featuring a mixed-signal compensation loop that simultaneously mitigates comparator offset, loop delay, switch on-resistance, and temperature dependency. The oscillator employs an auxiliary comparator, a charge pump, and a differential difference amplifier (DDA)-based main comparator to suppress ramping voltage overshoots caused by device and loop imperfections. Moreover, the auxiliary comparator employs chopper and digital demodulation techniques to suppress its own offset, further enhancing the accuracy of the calibration loop. By generating both ramping and reference voltages, the proportional-to-absolute-temperature (PTAT) core ensures that the temperature coefficient (TC) of the oscillation frequency primarily depends on passive RC components. Fabricated in a <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m BCD process, the design achieves an average frequency TC of 42 ppm/°C from −20 °C to 125 °C across ten samples. Benefiting from the proposed architecture, the oscillator operates at 8.45 MHz with a fast startup calibration time of <inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>s.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"333-336"},"PeriodicalIF":2.0,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 一个紧凑的电流复用6mw 66 - 92ghz频率四倍器，峰值功率增加效率5%，谐波抑制> 36dbc，采用22nm FDSOI CMOS

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-24 DOI: 10.1109/LSSC.2025.3614381

Shankkar Balasubramanian;Kristof Vaesen;Piet Wambacq;Carsten Wulff

引用次数: 0

A Battery-Free BLE Backscatter Communication Chip for Wearable Systems 一种用于可穿戴系统的无电池BLE反向散射通信芯片

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-22 DOI: 10.1109/LSSC.2025.3612423

Yongling Zhang;Ji Xiong;Junzai Chen;Xiaoyu Li;Jinrui Zuo;Yan Wang;Xiaoyi Wang;Miao Meng

引用次数: 0

Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications Opal：用于全稀疏机器学习应用的16nm粗粒度可重构阵列SoC

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-22 DOI: 10.1109/LSSC.2025.3613245

Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina

{"title":"Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications","authors":"Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina","doi":"10.1109/LSSC.2025.3613245","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3613245","url":null,"abstract":"Sparsity has recently attracted increased attention in the machine learning (ML) community due to its potential to improve performance and energy efficiency by eliminating ineffectual computations. As ML models evolve rapidly, reconfigurable architectures, such as coarse-grained reconfigurable arrays (CGRAs), are being explored to adapt to and accelerate emerging models. Previous CGRA designs have supported unstructured sparsity and reported promising speedups and energy savings for compute-intensive kernels. However, these approaches still face performance bottlenecks when accelerating entire sparse ML networks. In this letter, we identify the primary sources of inefficiency in prior CGRA-based approaches and present Opal, a CGRA SoC with three key contributions: 1) flexible dataflow architecture supporting Gustavson’s dataflow for sparse matrix multiplication; 2) high-throughput sparse hardware primitives; and 3) enhanced processing elements to support mapping all ML operations on the CGRA. As a result, Opal achieves a 66% to 79% reduction in runtime and energy consumption across our evaluated sparse graph neural network benchmarks compared to prior CGRA solutions which only target kernel acceleration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"293-296"},"PeriodicalIF":2.0,"publicationDate":"2025-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145223703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Fully Dynamic Capacitive Touch Sensor With Tri-Level Energy Recycling and Compressive Sensing Technique 基于三能级能量回收和压缩传感技术的全动态电容式触摸传感器

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-19 DOI: 10.1109/LSSC.2025.3612093

Xiangdong Feng;Zhiyu Wang;Haoyang Li;Jiaqing Li;Wei-Chin Lin;Xin Hu;Zhong Tang;Yuyan Liu;Qinwen Fan;Yuxuan Luo;Bo Zhao

{"title":"A Fully Dynamic Capacitive Touch Sensor With Tri-Level Energy Recycling and Compressive Sensing Technique","authors":"Xiangdong Feng;Zhiyu Wang;Haoyang Li;Jiaqing Li;Wei-Chin Lin;Xin Hu;Zhong Tang;Yuyan Liu;Qinwen Fan;Yuxuan Luo;Bo Zhao","doi":"10.1109/LSSC.2025.3612093","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3612093","url":null,"abstract":"Capacitive touch screens have become the dominant user interface over the past decade. Achieving high framerates with low power consumption remains a critical design goal for touch systems. The conventional charge-recycling technique reduces driving power by 64%, but it relies on off-chip capacitors. To address this issue, we propose a tri-level energy recycling scheme, in which energy released during the 2-to-1 transition is recycled to power the 0-to-1 transition on the complementary channel. This approach achieves a 25% power reduction using on-chip transmission gates. Additionally, a compressive sensing method is introduced to selectively process touched RX channels while bypassing the others, reducing the number of fine ADCs by a factor of four compared to conventional two-step sensing. The proposed techniques are implemented in a 65-nm CMOS process and integrated into a <inline-formula> <tex-math>$32times 20$ </tex-math></inline-formula> channel prototype occupying 2.4 mm2. Measurement results show that the chip consumes only 2.6 mW at a framerate of 1513 Hz. The signal-to-noise ratio (SNR) reaches 49.7 dB for finger touch and 28.7 dB for a 1-mm <inline-formula> <tex-math>$Phi $ </tex-math></inline-formula> stylus, resulting in an energy efficiency of 10.66 pJ/step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"337-340"},"PeriodicalIF":2.0,"publicationDate":"2025-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants 一个40.68 mhz， 200-ns沉降有源整流器毫米大小的植入物

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-18 DOI: 10.1109/LSSC.2025.3611484

Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore

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A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication 具有异步100/167 Mb/s ASK/FSK全双工通信的栅极驱动器的完全集成电隔离器

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IEEE Solid-State Circuits Letters Pub Date : 2025-09-17 DOI: 10.1109/LSSC.2025.3611018

Lucrezia Navarin;Karl Norling;Marco Parenzan;Stefano Ruzzu;Andrea Neviani;Andrea Bevilacqua

引用次数: 0